2 ******************************************************************************
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3 * @file stm32f407xx.h
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4 * @author MCD Application Team
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6 * @date 18-February-2014
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7 * @brief CMSIS STM32F407xx Device Peripheral Access Layer Header File.
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9 * This file contains:
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10 * - Data structures and the address mapping for all peripherals
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11 * - Peripheral's registers declarations and bits definition
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12 * - Macros to access peripheral�s registers hardware
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14 ******************************************************************************
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17 * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
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19 * Redistribution and use in source and binary forms, with or without modification,
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20 * are permitted provided that the following conditions are met:
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21 * 1. Redistributions of source code must retain the above copyright notice,
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22 * this list of conditions and the following disclaimer.
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23 * 2. Redistributions in binary form must reproduce the above copyright notice,
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24 * this list of conditions and the following disclaimer in the documentation
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25 * and/or other materials provided with the distribution.
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26 * 3. Neither the name of STMicroelectronics nor the names of its contributors
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27 * may be used to endorse or promote products derived from this software
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28 * without specific prior written permission.
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30 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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31 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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32 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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33 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
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34 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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35 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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36 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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37 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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38 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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41 ******************************************************************************
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44 /** @addtogroup CMSIS
\r
48 /** @addtogroup stm32f407xx
\r
52 #ifndef __STM32F407xx_H
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53 #define __STM32F407xx_H
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57 #endif /* __cplusplus */
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60 /** @addtogroup Configuration_section_for_CMSIS
\r
65 * @brief Configuration of the Cortex-M4 Processor and Core Peripherals
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67 #define __CM4_REV 0x0001 /*!< Core revision r0p1 */
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68 #define __MPU_PRESENT 1 /*!< STM32F4XX provides an MPU */
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69 #define __NVIC_PRIO_BITS 4 /*!< STM32F4XX uses 4 Bits for the Priority Levels */
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70 #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
\r
71 #define __FPU_PRESENT 1 /*!< FPU present */
\r
77 /** @addtogroup Peripheral_interrupt_number_definition
\r
82 * @brief STM32F4XX Interrupt Number Definition, according to the selected device
\r
83 * in @ref Library_configuration_section
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87 /****** Cortex-M4 Processor Exceptions Numbers ****************************************************************/
\r
88 NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
\r
89 MemoryManagement_IRQn = -12, /*!< 4 Cortex-M4 Memory Management Interrupt */
\r
90 BusFault_IRQn = -11, /*!< 5 Cortex-M4 Bus Fault Interrupt */
\r
91 UsageFault_IRQn = -10, /*!< 6 Cortex-M4 Usage Fault Interrupt */
\r
92 SVCall_IRQn = -5, /*!< 11 Cortex-M4 SV Call Interrupt */
\r
93 DebugMonitor_IRQn = -4, /*!< 12 Cortex-M4 Debug Monitor Interrupt */
\r
94 PendSV_IRQn = -2, /*!< 14 Cortex-M4 Pend SV Interrupt */
\r
95 SysTick_IRQn = -1, /*!< 15 Cortex-M4 System Tick Interrupt */
\r
96 /****** STM32 specific Interrupt Numbers **********************************************************************/
\r
97 WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */
\r
98 PVD_IRQn = 1, /*!< PVD through EXTI Line detection Interrupt */
\r
99 TAMP_STAMP_IRQn = 2, /*!< Tamper and TimeStamp interrupts through the EXTI line */
\r
100 RTC_WKUP_IRQn = 3, /*!< RTC Wakeup interrupt through the EXTI line */
\r
101 FLASH_IRQn = 4, /*!< FLASH global Interrupt */
\r
102 RCC_IRQn = 5, /*!< RCC global Interrupt */
\r
103 EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */
\r
104 EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */
\r
105 EXTI2_IRQn = 8, /*!< EXTI Line2 Interrupt */
\r
106 EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */
\r
107 EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */
\r
108 DMA1_Stream0_IRQn = 11, /*!< DMA1 Stream 0 global Interrupt */
\r
109 DMA1_Stream1_IRQn = 12, /*!< DMA1 Stream 1 global Interrupt */
\r
110 DMA1_Stream2_IRQn = 13, /*!< DMA1 Stream 2 global Interrupt */
\r
111 DMA1_Stream3_IRQn = 14, /*!< DMA1 Stream 3 global Interrupt */
\r
112 DMA1_Stream4_IRQn = 15, /*!< DMA1 Stream 4 global Interrupt */
\r
113 DMA1_Stream5_IRQn = 16, /*!< DMA1 Stream 5 global Interrupt */
\r
114 DMA1_Stream6_IRQn = 17, /*!< DMA1 Stream 6 global Interrupt */
\r
115 ADC_IRQn = 18, /*!< ADC1, ADC2 and ADC3 global Interrupts */
\r
116 CAN1_TX_IRQn = 19, /*!< CAN1 TX Interrupt */
\r
117 CAN1_RX0_IRQn = 20, /*!< CAN1 RX0 Interrupt */
\r
118 CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */
\r
119 CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */
\r
120 EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */
\r
121 TIM1_BRK_TIM9_IRQn = 24, /*!< TIM1 Break interrupt and TIM9 global interrupt */
\r
122 TIM1_UP_TIM10_IRQn = 25, /*!< TIM1 Update Interrupt and TIM10 global interrupt */
\r
123 TIM1_TRG_COM_TIM11_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt and TIM11 global interrupt */
\r
124 TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */
\r
125 TIM2_IRQn = 28, /*!< TIM2 global Interrupt */
\r
126 TIM3_IRQn = 29, /*!< TIM3 global Interrupt */
\r
127 TIM4_IRQn = 30, /*!< TIM4 global Interrupt */
\r
128 I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */
\r
129 I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */
\r
130 I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */
\r
131 I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */
\r
132 SPI1_IRQn = 35, /*!< SPI1 global Interrupt */
\r
133 SPI2_IRQn = 36, /*!< SPI2 global Interrupt */
\r
134 USART1_IRQn = 37, /*!< USART1 global Interrupt */
\r
135 USART2_IRQn = 38, /*!< USART2 global Interrupt */
\r
136 USART3_IRQn = 39, /*!< USART3 global Interrupt */
\r
137 EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */
\r
138 RTC_Alarm_IRQn = 41, /*!< RTC Alarm (A and B) through EXTI Line Interrupt */
\r
139 OTG_FS_WKUP_IRQn = 42, /*!< USB OTG FS Wakeup through EXTI line interrupt */
\r
140 TIM8_BRK_TIM12_IRQn = 43, /*!< TIM8 Break Interrupt and TIM12 global interrupt */
\r
141 TIM8_UP_TIM13_IRQn = 44, /*!< TIM8 Update Interrupt and TIM13 global interrupt */
\r
142 TIM8_TRG_COM_TIM14_IRQn = 45, /*!< TIM8 Trigger and Commutation Interrupt and TIM14 global interrupt */
\r
143 TIM8_CC_IRQn = 46, /*!< TIM8 Capture Compare Interrupt */
\r
144 DMA1_Stream7_IRQn = 47, /*!< DMA1 Stream7 Interrupt */
\r
145 FSMC_IRQn = 48, /*!< FSMC global Interrupt */
\r
146 SDIO_IRQn = 49, /*!< SDIO global Interrupt */
\r
147 TIM5_IRQn = 50, /*!< TIM5 global Interrupt */
\r
148 SPI3_IRQn = 51, /*!< SPI3 global Interrupt */
\r
149 UART4_IRQn = 52, /*!< UART4 global Interrupt */
\r
150 UART5_IRQn = 53, /*!< UART5 global Interrupt */
\r
151 TIM6_DAC_IRQn = 54, /*!< TIM6 global and DAC1&2 underrun error interrupts */
\r
152 TIM7_IRQn = 55, /*!< TIM7 global interrupt */
\r
153 DMA2_Stream0_IRQn = 56, /*!< DMA2 Stream 0 global Interrupt */
\r
154 DMA2_Stream1_IRQn = 57, /*!< DMA2 Stream 1 global Interrupt */
\r
155 DMA2_Stream2_IRQn = 58, /*!< DMA2 Stream 2 global Interrupt */
\r
156 DMA2_Stream3_IRQn = 59, /*!< DMA2 Stream 3 global Interrupt */
\r
157 DMA2_Stream4_IRQn = 60, /*!< DMA2 Stream 4 global Interrupt */
\r
158 ETH_IRQn = 61, /*!< Ethernet global Interrupt */
\r
159 ETH_WKUP_IRQn = 62, /*!< Ethernet Wakeup through EXTI line Interrupt */
\r
160 CAN2_TX_IRQn = 63, /*!< CAN2 TX Interrupt */
\r
161 CAN2_RX0_IRQn = 64, /*!< CAN2 RX0 Interrupt */
\r
162 CAN2_RX1_IRQn = 65, /*!< CAN2 RX1 Interrupt */
\r
163 CAN2_SCE_IRQn = 66, /*!< CAN2 SCE Interrupt */
\r
164 OTG_FS_IRQn = 67, /*!< USB OTG FS global Interrupt */
\r
165 DMA2_Stream5_IRQn = 68, /*!< DMA2 Stream 5 global interrupt */
\r
166 DMA2_Stream6_IRQn = 69, /*!< DMA2 Stream 6 global interrupt */
\r
167 DMA2_Stream7_IRQn = 70, /*!< DMA2 Stream 7 global interrupt */
\r
168 USART6_IRQn = 71, /*!< USART6 global interrupt */
\r
169 I2C3_EV_IRQn = 72, /*!< I2C3 event interrupt */
\r
170 I2C3_ER_IRQn = 73, /*!< I2C3 error interrupt */
\r
171 OTG_HS_EP1_OUT_IRQn = 74, /*!< USB OTG HS End Point 1 Out global interrupt */
\r
172 OTG_HS_EP1_IN_IRQn = 75, /*!< USB OTG HS End Point 1 In global interrupt */
\r
173 OTG_HS_WKUP_IRQn = 76, /*!< USB OTG HS Wakeup through EXTI interrupt */
\r
174 OTG_HS_IRQn = 77, /*!< USB OTG HS global interrupt */
\r
175 DCMI_IRQn = 78, /*!< DCMI global interrupt */
\r
176 HASH_RNG_IRQn = 80, /*!< Hash and RNG global interrupt */
\r
177 FPU_IRQn = 81 /*!< FPU global interrupt */
\r
184 #include "core_cm4.h" /* Cortex-M4 processor and core peripherals */
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185 #include "system_stm32f4xx.h"
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186 #include <stdint.h>
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188 /** @addtogroup Peripheral_registers_structures
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193 * @brief Analog to Digital Converter
\r
198 __IO uint32_t SR; /*!< ADC status register, Address offset: 0x00 */
\r
199 __IO uint32_t CR1; /*!< ADC control register 1, Address offset: 0x04 */
\r
200 __IO uint32_t CR2; /*!< ADC control register 2, Address offset: 0x08 */
\r
201 __IO uint32_t SMPR1; /*!< ADC sample time register 1, Address offset: 0x0C */
\r
202 __IO uint32_t SMPR2; /*!< ADC sample time register 2, Address offset: 0x10 */
\r
203 __IO uint32_t JOFR1; /*!< ADC injected channel data offset register 1, Address offset: 0x14 */
\r
204 __IO uint32_t JOFR2; /*!< ADC injected channel data offset register 2, Address offset: 0x18 */
\r
205 __IO uint32_t JOFR3; /*!< ADC injected channel data offset register 3, Address offset: 0x1C */
\r
206 __IO uint32_t JOFR4; /*!< ADC injected channel data offset register 4, Address offset: 0x20 */
\r
207 __IO uint32_t HTR; /*!< ADC watchdog higher threshold register, Address offset: 0x24 */
\r
208 __IO uint32_t LTR; /*!< ADC watchdog lower threshold register, Address offset: 0x28 */
\r
209 __IO uint32_t SQR1; /*!< ADC regular sequence register 1, Address offset: 0x2C */
\r
210 __IO uint32_t SQR2; /*!< ADC regular sequence register 2, Address offset: 0x30 */
\r
211 __IO uint32_t SQR3; /*!< ADC regular sequence register 3, Address offset: 0x34 */
\r
212 __IO uint32_t JSQR; /*!< ADC injected sequence register, Address offset: 0x38*/
\r
213 __IO uint32_t JDR1; /*!< ADC injected data register 1, Address offset: 0x3C */
\r
214 __IO uint32_t JDR2; /*!< ADC injected data register 2, Address offset: 0x40 */
\r
215 __IO uint32_t JDR3; /*!< ADC injected data register 3, Address offset: 0x44 */
\r
216 __IO uint32_t JDR4; /*!< ADC injected data register 4, Address offset: 0x48 */
\r
217 __IO uint32_t DR; /*!< ADC regular data register, Address offset: 0x4C */
\r
222 __IO uint32_t CSR; /*!< ADC Common status register, Address offset: ADC1 base address + 0x300 */
\r
223 __IO uint32_t CCR; /*!< ADC common control register, Address offset: ADC1 base address + 0x304 */
\r
224 __IO uint32_t CDR; /*!< ADC common regular data register for dual
\r
225 AND triple modes, Address offset: ADC1 base address + 0x308 */
\r
226 } ADC_Common_TypeDef;
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230 * @brief Controller Area Network TxMailBox
\r
235 __IO uint32_t TIR; /*!< CAN TX mailbox identifier register */
\r
236 __IO uint32_t TDTR; /*!< CAN mailbox data length control and time stamp register */
\r
237 __IO uint32_t TDLR; /*!< CAN mailbox data low register */
\r
238 __IO uint32_t TDHR; /*!< CAN mailbox data high register */
\r
239 } CAN_TxMailBox_TypeDef;
\r
242 * @brief Controller Area Network FIFOMailBox
\r
247 __IO uint32_t RIR; /*!< CAN receive FIFO mailbox identifier register */
\r
248 __IO uint32_t RDTR; /*!< CAN receive FIFO mailbox data length control and time stamp register */
\r
249 __IO uint32_t RDLR; /*!< CAN receive FIFO mailbox data low register */
\r
250 __IO uint32_t RDHR; /*!< CAN receive FIFO mailbox data high register */
\r
251 } CAN_FIFOMailBox_TypeDef;
\r
254 * @brief Controller Area Network FilterRegister
\r
259 __IO uint32_t FR1; /*!< CAN Filter bank register 1 */
\r
260 __IO uint32_t FR2; /*!< CAN Filter bank register 1 */
\r
261 } CAN_FilterRegister_TypeDef;
\r
264 * @brief Controller Area Network
\r
269 __IO uint32_t MCR; /*!< CAN master control register, Address offset: 0x00 */
\r
270 __IO uint32_t MSR; /*!< CAN master status register, Address offset: 0x04 */
\r
271 __IO uint32_t TSR; /*!< CAN transmit status register, Address offset: 0x08 */
\r
272 __IO uint32_t RF0R; /*!< CAN receive FIFO 0 register, Address offset: 0x0C */
\r
273 __IO uint32_t RF1R; /*!< CAN receive FIFO 1 register, Address offset: 0x10 */
\r
274 __IO uint32_t IER; /*!< CAN interrupt enable register, Address offset: 0x14 */
\r
275 __IO uint32_t ESR; /*!< CAN error status register, Address offset: 0x18 */
\r
276 __IO uint32_t BTR; /*!< CAN bit timing register, Address offset: 0x1C */
\r
277 uint32_t RESERVED0[88]; /*!< Reserved, 0x020 - 0x17F */
\r
278 CAN_TxMailBox_TypeDef sTxMailBox[3]; /*!< CAN Tx MailBox, Address offset: 0x180 - 0x1AC */
\r
279 CAN_FIFOMailBox_TypeDef sFIFOMailBox[2]; /*!< CAN FIFO MailBox, Address offset: 0x1B0 - 0x1CC */
\r
280 uint32_t RESERVED1[12]; /*!< Reserved, 0x1D0 - 0x1FF */
\r
281 __IO uint32_t FMR; /*!< CAN filter master register, Address offset: 0x200 */
\r
282 __IO uint32_t FM1R; /*!< CAN filter mode register, Address offset: 0x204 */
\r
283 uint32_t RESERVED2; /*!< Reserved, 0x208 */
\r
284 __IO uint32_t FS1R; /*!< CAN filter scale register, Address offset: 0x20C */
\r
285 uint32_t RESERVED3; /*!< Reserved, 0x210 */
\r
286 __IO uint32_t FFA1R; /*!< CAN filter FIFO assignment register, Address offset: 0x214 */
\r
287 uint32_t RESERVED4; /*!< Reserved, 0x218 */
\r
288 __IO uint32_t FA1R; /*!< CAN filter activation register, Address offset: 0x21C */
\r
289 uint32_t RESERVED5[8]; /*!< Reserved, 0x220-0x23F */
\r
290 CAN_FilterRegister_TypeDef sFilterRegister[28]; /*!< CAN Filter Register, Address offset: 0x240-0x31C */
\r
294 * @brief CRC calculation unit
\r
299 __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */
\r
300 __IO uint8_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */
\r
301 uint8_t RESERVED0; /*!< Reserved, 0x05 */
\r
302 uint16_t RESERVED1; /*!< Reserved, 0x06 */
\r
303 __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */
\r
307 * @brief Digital to Analog Converter
\r
312 __IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */
\r
313 __IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */
\r
314 __IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */
\r
315 __IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */
\r
316 __IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */
\r
317 __IO uint32_t DHR12R2; /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */
\r
318 __IO uint32_t DHR12L2; /*!< DAC channel2 12-bit left aligned data holding register, Address offset: 0x18 */
\r
319 __IO uint32_t DHR8R2; /*!< DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C */
\r
320 __IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 */
\r
321 __IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 */
\r
322 __IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 */
\r
323 __IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */
\r
324 __IO uint32_t DOR2; /*!< DAC channel2 data output register, Address offset: 0x30 */
\r
325 __IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */
\r
334 __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */
\r
335 __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */
\r
336 __IO uint32_t APB1FZ; /*!< Debug MCU APB1 freeze register, Address offset: 0x08 */
\r
337 __IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x0C */
\r
346 __IO uint32_t CR; /*!< DCMI control register 1, Address offset: 0x00 */
\r
347 __IO uint32_t SR; /*!< DCMI status register, Address offset: 0x04 */
\r
348 __IO uint32_t RISR; /*!< DCMI raw interrupt status register, Address offset: 0x08 */
\r
349 __IO uint32_t IER; /*!< DCMI interrupt enable register, Address offset: 0x0C */
\r
350 __IO uint32_t MISR; /*!< DCMI masked interrupt status register, Address offset: 0x10 */
\r
351 __IO uint32_t ICR; /*!< DCMI interrupt clear register, Address offset: 0x14 */
\r
352 __IO uint32_t ESCR; /*!< DCMI embedded synchronization code register, Address offset: 0x18 */
\r
353 __IO uint32_t ESUR; /*!< DCMI embedded synchronization unmask register, Address offset: 0x1C */
\r
354 __IO uint32_t CWSTRTR; /*!< DCMI crop window start, Address offset: 0x20 */
\r
355 __IO uint32_t CWSIZER; /*!< DCMI crop window size, Address offset: 0x24 */
\r
356 __IO uint32_t DR; /*!< DCMI data register, Address offset: 0x28 */
\r
360 * @brief DMA Controller
\r
365 __IO uint32_t CR; /*!< DMA stream x configuration register */
\r
366 __IO uint32_t NDTR; /*!< DMA stream x number of data register */
\r
367 __IO uint32_t PAR; /*!< DMA stream x peripheral address register */
\r
368 __IO uint32_t M0AR; /*!< DMA stream x memory 0 address register */
\r
369 __IO uint32_t M1AR; /*!< DMA stream x memory 1 address register */
\r
370 __IO uint32_t FCR; /*!< DMA stream x FIFO control register */
\r
371 } DMA_Stream_TypeDef;
\r
375 __IO uint32_t LISR; /*!< DMA low interrupt status register, Address offset: 0x00 */
\r
376 __IO uint32_t HISR; /*!< DMA high interrupt status register, Address offset: 0x04 */
\r
377 __IO uint32_t LIFCR; /*!< DMA low interrupt flag clear register, Address offset: 0x08 */
\r
378 __IO uint32_t HIFCR; /*!< DMA high interrupt flag clear register, Address offset: 0x0C */
\r
383 * @brief Ethernet MAC
\r
388 __IO uint32_t MACCR;
\r
389 __IO uint32_t MACFFR;
\r
390 __IO uint32_t MACHTHR;
\r
391 __IO uint32_t MACHTLR;
\r
392 __IO uint32_t MACMIIAR;
\r
393 __IO uint32_t MACMIIDR;
\r
394 __IO uint32_t MACFCR;
\r
395 __IO uint32_t MACVLANTR; /* 8 */
\r
396 uint32_t RESERVED0[2];
\r
397 __IO uint32_t MACRWUFFR; /* 11 */
\r
398 __IO uint32_t MACPMTCSR;
\r
399 uint32_t RESERVED1[2];
\r
400 __IO uint32_t MACSR; /* 15 */
\r
401 __IO uint32_t MACIMR;
\r
402 __IO uint32_t MACA0HR;
\r
403 __IO uint32_t MACA0LR;
\r
404 __IO uint32_t MACA1HR;
\r
405 __IO uint32_t MACA1LR;
\r
406 __IO uint32_t MACA2HR;
\r
407 __IO uint32_t MACA2LR;
\r
408 __IO uint32_t MACA3HR;
\r
409 __IO uint32_t MACA3LR; /* 24 */
\r
410 uint32_t RESERVED2[40];
\r
411 __IO uint32_t MMCCR; /* 65 */
\r
412 __IO uint32_t MMCRIR;
\r
413 __IO uint32_t MMCTIR;
\r
414 __IO uint32_t MMCRIMR;
\r
415 __IO uint32_t MMCTIMR; /* 69 */
\r
416 uint32_t RESERVED3[14];
\r
417 __IO uint32_t MMCTGFSCCR; /* 84 */
\r
418 __IO uint32_t MMCTGFMSCCR;
\r
419 uint32_t RESERVED4[5];
\r
420 __IO uint32_t MMCTGFCR;
\r
421 uint32_t RESERVED5[10];
\r
422 __IO uint32_t MMCRFCECR;
\r
423 __IO uint32_t MMCRFAECR;
\r
424 uint32_t RESERVED6[10];
\r
425 __IO uint32_t MMCRGUFCR;
\r
426 uint32_t RESERVED7[334];
\r
427 __IO uint32_t PTPTSCR;
\r
428 __IO uint32_t PTPSSIR;
\r
429 __IO uint32_t PTPTSHR;
\r
430 __IO uint32_t PTPTSLR;
\r
431 __IO uint32_t PTPTSHUR;
\r
432 __IO uint32_t PTPTSLUR;
\r
433 __IO uint32_t PTPTSAR;
\r
434 __IO uint32_t PTPTTHR;
\r
435 __IO uint32_t PTPTTLR;
\r
436 __IO uint32_t RESERVED8;
\r
437 __IO uint32_t PTPTSSR;
\r
438 uint32_t RESERVED9[565];
\r
439 __IO uint32_t DMABMR;
\r
440 __IO uint32_t DMATPDR;
\r
441 __IO uint32_t DMARPDR;
\r
442 __IO uint32_t DMARDLAR;
\r
443 __IO uint32_t DMATDLAR;
\r
444 __IO uint32_t DMASR;
\r
445 __IO uint32_t DMAOMR;
\r
446 __IO uint32_t DMAIER;
\r
447 __IO uint32_t DMAMFBOCR;
\r
448 __IO uint32_t DMARSWTR;
\r
449 uint32_t RESERVED10[8];
\r
450 __IO uint32_t DMACHTDR;
\r
451 __IO uint32_t DMACHRDR;
\r
452 __IO uint32_t DMACHTBAR;
\r
453 __IO uint32_t DMACHRBAR;
\r
457 * @brief External Interrupt/Event Controller
\r
462 __IO uint32_t IMR; /*!< EXTI Interrupt mask register, Address offset: 0x00 */
\r
463 __IO uint32_t EMR; /*!< EXTI Event mask register, Address offset: 0x04 */
\r
464 __IO uint32_t RTSR; /*!< EXTI Rising trigger selection register, Address offset: 0x08 */
\r
465 __IO uint32_t FTSR; /*!< EXTI Falling trigger selection register, Address offset: 0x0C */
\r
466 __IO uint32_t SWIER; /*!< EXTI Software interrupt event register, Address offset: 0x10 */
\r
467 __IO uint32_t PR; /*!< EXTI Pending register, Address offset: 0x14 */
\r
471 * @brief FLASH Registers
\r
476 __IO uint32_t ACR; /*!< FLASH access control register, Address offset: 0x00 */
\r
477 __IO uint32_t KEYR; /*!< FLASH key register, Address offset: 0x04 */
\r
478 __IO uint32_t OPTKEYR; /*!< FLASH option key register, Address offset: 0x08 */
\r
479 __IO uint32_t SR; /*!< FLASH status register, Address offset: 0x0C */
\r
480 __IO uint32_t CR; /*!< FLASH control register, Address offset: 0x10 */
\r
481 __IO uint32_t OPTCR; /*!< FLASH option control register , Address offset: 0x14 */
\r
482 __IO uint32_t OPTCR1; /*!< FLASH option control register 1, Address offset: 0x18 */
\r
487 * @brief Flexible Static Memory Controller
\r
492 __IO uint32_t BTCR[8]; /*!< NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR), Address offset: 0x00-1C */
\r
493 } FSMC_Bank1_TypeDef;
\r
496 * @brief Flexible Static Memory Controller Bank1E
\r
501 __IO uint32_t BWTR[7]; /*!< NOR/PSRAM write timing registers, Address offset: 0x104-0x11C */
\r
502 } FSMC_Bank1E_TypeDef;
\r
505 * @brief Flexible Static Memory Controller Bank2
\r
510 __IO uint32_t PCR2; /*!< NAND Flash control register 2, Address offset: 0x60 */
\r
511 __IO uint32_t SR2; /*!< NAND Flash FIFO status and interrupt register 2, Address offset: 0x64 */
\r
512 __IO uint32_t PMEM2; /*!< NAND Flash Common memory space timing register 2, Address offset: 0x68 */
\r
513 __IO uint32_t PATT2; /*!< NAND Flash Attribute memory space timing register 2, Address offset: 0x6C */
\r
514 uint32_t RESERVED0; /*!< Reserved, 0x70 */
\r
515 __IO uint32_t ECCR2; /*!< NAND Flash ECC result registers 2, Address offset: 0x74 */
\r
516 uint32_t RESERVED1; /*!< Reserved, 0x78 */
\r
517 uint32_t RESERVED2; /*!< Reserved, 0x7C */
\r
518 __IO uint32_t PCR3; /*!< NAND Flash control register 3, Address offset: 0x80 */
\r
519 __IO uint32_t SR3; /*!< NAND Flash FIFO status and interrupt register 3, Address offset: 0x84 */
\r
520 __IO uint32_t PMEM3; /*!< NAND Flash Common memory space timing register 3, Address offset: 0x88 */
\r
521 __IO uint32_t PATT3; /*!< NAND Flash Attribute memory space timing register 3, Address offset: 0x8C */
\r
522 uint32_t RESERVED3; /*!< Reserved, 0x90 */
\r
523 __IO uint32_t ECCR3; /*!< NAND Flash ECC result registers 3, Address offset: 0x94 */
\r
524 } FSMC_Bank2_3_TypeDef;
\r
527 * @brief Flexible Static Memory Controller Bank4
\r
532 __IO uint32_t PCR4; /*!< PC Card control register 4, Address offset: 0xA0 */
\r
533 __IO uint32_t SR4; /*!< PC Card FIFO status and interrupt register 4, Address offset: 0xA4 */
\r
534 __IO uint32_t PMEM4; /*!< PC Card Common memory space timing register 4, Address offset: 0xA8 */
\r
535 __IO uint32_t PATT4; /*!< PC Card Attribute memory space timing register 4, Address offset: 0xAC */
\r
536 __IO uint32_t PIO4; /*!< PC Card I/O space timing register 4, Address offset: 0xB0 */
\r
537 } FSMC_Bank4_TypeDef;
\r
541 * @brief General Purpose I/O
\r
546 __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */
\r
547 __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */
\r
548 __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */
\r
549 __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */
\r
550 __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */
\r
551 __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */
\r
552 __IO uint16_t BSRRL; /*!< GPIO port bit set/reset low register, Address offset: 0x18 */
\r
553 __IO uint16_t BSRRH; /*!< GPIO port bit set/reset high register, Address offset: 0x1A */
\r
554 __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */
\r
555 __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */
\r
559 * @brief System configuration controller
\r
564 __IO uint32_t MEMRMP; /*!< SYSCFG memory remap register, Address offset: 0x00 */
\r
565 __IO uint32_t PMC; /*!< SYSCFG peripheral mode configuration register, Address offset: 0x04 */
\r
566 __IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14 */
\r
567 uint32_t RESERVED[2]; /*!< Reserved, 0x18-0x1C */
\r
568 __IO uint32_t CMPCR; /*!< SYSCFG Compensation cell control register, Address offset: 0x20 */
\r
572 * @brief Inter-integrated Circuit Interface
\r
577 __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */
\r
578 __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */
\r
579 __IO uint32_t OAR1; /*!< I2C Own address register 1, Address offset: 0x08 */
\r
580 __IO uint32_t OAR2; /*!< I2C Own address register 2, Address offset: 0x0C */
\r
581 __IO uint32_t DR; /*!< I2C Data register, Address offset: 0x10 */
\r
582 __IO uint32_t SR1; /*!< I2C Status register 1, Address offset: 0x14 */
\r
583 __IO uint32_t SR2; /*!< I2C Status register 2, Address offset: 0x18 */
\r
584 __IO uint32_t CCR; /*!< I2C Clock control register, Address offset: 0x1C */
\r
585 __IO uint32_t TRISE; /*!< I2C TRISE register, Address offset: 0x20 */
\r
586 __IO uint32_t FLTR; /*!< I2C FLTR register, Address offset: 0x24 */
\r
590 * @brief Independent WATCHDOG
\r
595 __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */
\r
596 __IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */
\r
597 __IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */
\r
598 __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */
\r
602 * @brief Power Control
\r
607 __IO uint32_t CR; /*!< PWR power control register, Address offset: 0x00 */
\r
608 __IO uint32_t CSR; /*!< PWR power control/status register, Address offset: 0x04 */
\r
612 * @brief Reset and Clock Control
\r
617 __IO uint32_t CR; /*!< RCC clock control register, Address offset: 0x00 */
\r
618 __IO uint32_t PLLCFGR; /*!< RCC PLL configuration register, Address offset: 0x04 */
\r
619 __IO uint32_t CFGR; /*!< RCC clock configuration register, Address offset: 0x08 */
\r
620 __IO uint32_t CIR; /*!< RCC clock interrupt register, Address offset: 0x0C */
\r
621 __IO uint32_t AHB1RSTR; /*!< RCC AHB1 peripheral reset register, Address offset: 0x10 */
\r
622 __IO uint32_t AHB2RSTR; /*!< RCC AHB2 peripheral reset register, Address offset: 0x14 */
\r
623 __IO uint32_t AHB3RSTR; /*!< RCC AHB3 peripheral reset register, Address offset: 0x18 */
\r
624 uint32_t RESERVED0; /*!< Reserved, 0x1C */
\r
625 __IO uint32_t APB1RSTR; /*!< RCC APB1 peripheral reset register, Address offset: 0x20 */
\r
626 __IO uint32_t APB2RSTR; /*!< RCC APB2 peripheral reset register, Address offset: 0x24 */
\r
627 uint32_t RESERVED1[2]; /*!< Reserved, 0x28-0x2C */
\r
628 __IO uint32_t AHB1ENR; /*!< RCC AHB1 peripheral clock register, Address offset: 0x30 */
\r
629 __IO uint32_t AHB2ENR; /*!< RCC AHB2 peripheral clock register, Address offset: 0x34 */
\r
630 __IO uint32_t AHB3ENR; /*!< RCC AHB3 peripheral clock register, Address offset: 0x38 */
\r
631 uint32_t RESERVED2; /*!< Reserved, 0x3C */
\r
632 __IO uint32_t APB1ENR; /*!< RCC APB1 peripheral clock enable register, Address offset: 0x40 */
\r
633 __IO uint32_t APB2ENR; /*!< RCC APB2 peripheral clock enable register, Address offset: 0x44 */
\r
634 uint32_t RESERVED3[2]; /*!< Reserved, 0x48-0x4C */
\r
635 __IO uint32_t AHB1LPENR; /*!< RCC AHB1 peripheral clock enable in low power mode register, Address offset: 0x50 */
\r
636 __IO uint32_t AHB2LPENR; /*!< RCC AHB2 peripheral clock enable in low power mode register, Address offset: 0x54 */
\r
637 __IO uint32_t AHB3LPENR; /*!< RCC AHB3 peripheral clock enable in low power mode register, Address offset: 0x58 */
\r
638 uint32_t RESERVED4; /*!< Reserved, 0x5C */
\r
639 __IO uint32_t APB1LPENR; /*!< RCC APB1 peripheral clock enable in low power mode register, Address offset: 0x60 */
\r
640 __IO uint32_t APB2LPENR; /*!< RCC APB2 peripheral clock enable in low power mode register, Address offset: 0x64 */
\r
641 uint32_t RESERVED5[2]; /*!< Reserved, 0x68-0x6C */
\r
642 __IO uint32_t BDCR; /*!< RCC Backup domain control register, Address offset: 0x70 */
\r
643 __IO uint32_t CSR; /*!< RCC clock control & status register, Address offset: 0x74 */
\r
644 uint32_t RESERVED6[2]; /*!< Reserved, 0x78-0x7C */
\r
645 __IO uint32_t SSCGR; /*!< RCC spread spectrum clock generation register, Address offset: 0x80 */
\r
646 __IO uint32_t PLLI2SCFGR; /*!< RCC PLLI2S configuration register, Address offset: 0x84 */
\r
651 * @brief Real-Time Clock
\r
656 __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */
\r
657 __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */
\r
658 __IO uint32_t CR; /*!< RTC control register, Address offset: 0x08 */
\r
659 __IO uint32_t ISR; /*!< RTC initialization and status register, Address offset: 0x0C */
\r
660 __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */
\r
661 __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */
\r
662 __IO uint32_t CALIBR; /*!< RTC calibration register, Address offset: 0x18 */
\r
663 __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x1C */
\r
664 __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x20 */
\r
665 __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */
\r
666 __IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x28 */
\r
667 __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */
\r
668 __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */
\r
669 __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */
\r
670 __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */
\r
671 __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x3C */
\r
672 __IO uint32_t TAFCR; /*!< RTC tamper and alternate function configuration register, Address offset: 0x40 */
\r
673 __IO uint32_t ALRMASSR;/*!< RTC alarm A sub second register, Address offset: 0x44 */
\r
674 __IO uint32_t ALRMBSSR;/*!< RTC alarm B sub second register, Address offset: 0x48 */
\r
675 uint32_t RESERVED7; /*!< Reserved, 0x4C */
\r
676 __IO uint32_t BKP0R; /*!< RTC backup register 1, Address offset: 0x50 */
\r
677 __IO uint32_t BKP1R; /*!< RTC backup register 1, Address offset: 0x54 */
\r
678 __IO uint32_t BKP2R; /*!< RTC backup register 2, Address offset: 0x58 */
\r
679 __IO uint32_t BKP3R; /*!< RTC backup register 3, Address offset: 0x5C */
\r
680 __IO uint32_t BKP4R; /*!< RTC backup register 4, Address offset: 0x60 */
\r
681 __IO uint32_t BKP5R; /*!< RTC backup register 5, Address offset: 0x64 */
\r
682 __IO uint32_t BKP6R; /*!< RTC backup register 6, Address offset: 0x68 */
\r
683 __IO uint32_t BKP7R; /*!< RTC backup register 7, Address offset: 0x6C */
\r
684 __IO uint32_t BKP8R; /*!< RTC backup register 8, Address offset: 0x70 */
\r
685 __IO uint32_t BKP9R; /*!< RTC backup register 9, Address offset: 0x74 */
\r
686 __IO uint32_t BKP10R; /*!< RTC backup register 10, Address offset: 0x78 */
\r
687 __IO uint32_t BKP11R; /*!< RTC backup register 11, Address offset: 0x7C */
\r
688 __IO uint32_t BKP12R; /*!< RTC backup register 12, Address offset: 0x80 */
\r
689 __IO uint32_t BKP13R; /*!< RTC backup register 13, Address offset: 0x84 */
\r
690 __IO uint32_t BKP14R; /*!< RTC backup register 14, Address offset: 0x88 */
\r
691 __IO uint32_t BKP15R; /*!< RTC backup register 15, Address offset: 0x8C */
\r
692 __IO uint32_t BKP16R; /*!< RTC backup register 16, Address offset: 0x90 */
\r
693 __IO uint32_t BKP17R; /*!< RTC backup register 17, Address offset: 0x94 */
\r
694 __IO uint32_t BKP18R; /*!< RTC backup register 18, Address offset: 0x98 */
\r
695 __IO uint32_t BKP19R; /*!< RTC backup register 19, Address offset: 0x9C */
\r
700 * @brief SD host Interface
\r
705 __IO uint32_t POWER; /*!< SDIO power control register, Address offset: 0x00 */
\r
706 __IO uint32_t CLKCR; /*!< SDI clock control register, Address offset: 0x04 */
\r
707 __IO uint32_t ARG; /*!< SDIO argument register, Address offset: 0x08 */
\r
708 __IO uint32_t CMD; /*!< SDIO command register, Address offset: 0x0C */
\r
709 __I uint32_t RESPCMD; /*!< SDIO command response register, Address offset: 0x10 */
\r
710 __I uint32_t RESP1; /*!< SDIO response 1 register, Address offset: 0x14 */
\r
711 __I uint32_t RESP2; /*!< SDIO response 2 register, Address offset: 0x18 */
\r
712 __I uint32_t RESP3; /*!< SDIO response 3 register, Address offset: 0x1C */
\r
713 __I uint32_t RESP4; /*!< SDIO response 4 register, Address offset: 0x20 */
\r
714 __IO uint32_t DTIMER; /*!< SDIO data timer register, Address offset: 0x24 */
\r
715 __IO uint32_t DLEN; /*!< SDIO data length register, Address offset: 0x28 */
\r
716 __IO uint32_t DCTRL; /*!< SDIO data control register, Address offset: 0x2C */
\r
717 __I uint32_t DCOUNT; /*!< SDIO data counter register, Address offset: 0x30 */
\r
718 __I uint32_t STA; /*!< SDIO status register, Address offset: 0x34 */
\r
719 __IO uint32_t ICR; /*!< SDIO interrupt clear register, Address offset: 0x38 */
\r
720 __IO uint32_t MASK; /*!< SDIO mask register, Address offset: 0x3C */
\r
721 uint32_t RESERVED0[2]; /*!< Reserved, 0x40-0x44 */
\r
722 __I uint32_t FIFOCNT; /*!< SDIO FIFO counter register, Address offset: 0x48 */
\r
723 uint32_t RESERVED1[13]; /*!< Reserved, 0x4C-0x7C */
\r
724 __IO uint32_t FIFO; /*!< SDIO data FIFO register, Address offset: 0x80 */
\r
728 * @brief Serial Peripheral Interface
\r
733 __IO uint32_t CR1; /*!< SPI control register 1 (not used in I2S mode), Address offset: 0x00 */
\r
734 __IO uint32_t CR2; /*!< SPI control register 2, Address offset: 0x04 */
\r
735 __IO uint32_t SR; /*!< SPI status register, Address offset: 0x08 */
\r
736 __IO uint32_t DR; /*!< SPI data register, Address offset: 0x0C */
\r
737 __IO uint32_t CRCPR; /*!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 */
\r
738 __IO uint32_t RXCRCR; /*!< SPI RX CRC register (not used in I2S mode), Address offset: 0x14 */
\r
739 __IO uint32_t TXCRCR; /*!< SPI TX CRC register (not used in I2S mode), Address offset: 0x18 */
\r
740 __IO uint32_t I2SCFGR; /*!< SPI_I2S configuration register, Address offset: 0x1C */
\r
741 __IO uint32_t I2SPR; /*!< SPI_I2S prescaler register, Address offset: 0x20 */
\r
750 __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */
\r
751 __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */
\r
752 __IO uint32_t SMCR; /*!< TIM slave mode control register, Address offset: 0x08 */
\r
753 __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */
\r
754 __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */
\r
755 __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */
\r
756 __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */
\r
757 __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */
\r
758 __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */
\r
759 __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */
\r
760 __IO uint32_t PSC; /*!< TIM prescaler, Address offset: 0x28 */
\r
761 __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */
\r
762 __IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */
\r
763 __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */
\r
764 __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */
\r
765 __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */
\r
766 __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */
\r
767 __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */
\r
768 __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */
\r
769 __IO uint32_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x4C */
\r
770 __IO uint32_t OR; /*!< TIM option register, Address offset: 0x50 */
\r
774 * @brief Universal Synchronous Asynchronous Receiver Transmitter
\r
779 __IO uint32_t SR; /*!< USART Status register, Address offset: 0x00 */
\r
780 __IO uint32_t DR; /*!< USART Data register, Address offset: 0x04 */
\r
781 __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x08 */
\r
782 __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x0C */
\r
783 __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x10 */
\r
784 __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x14 */
\r
785 __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x18 */
\r
789 * @brief Window WATCHDOG
\r
794 __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */
\r
795 __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */
\r
796 __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */
\r
805 __IO uint32_t CR; /*!< RNG control register, Address offset: 0x00 */
\r
806 __IO uint32_t SR; /*!< RNG status register, Address offset: 0x04 */
\r
807 __IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */
\r
813 * @brief __USB_OTG_Core_register
\r
817 __IO uint32_t GOTGCTL; /*!< USB_OTG Control and Status Register 000h*/
\r
818 __IO uint32_t GOTGINT; /*!< USB_OTG Interrupt Register 004h*/
\r
819 __IO uint32_t GAHBCFG; /*!< Core AHB Configuration Register 008h*/
\r
820 __IO uint32_t GUSBCFG; /*!< Core USB Configuration Register 00Ch*/
\r
821 __IO uint32_t GRSTCTL; /*!< Core Reset Register 010h*/
\r
822 __IO uint32_t GINTSTS; /*!< Core Interrupt Register 014h*/
\r
823 __IO uint32_t GINTMSK; /*!< Core Interrupt Mask Register 018h*/
\r
824 __IO uint32_t GRXSTSR; /*!< Receive Sts Q Read Register 01Ch*/
\r
825 __IO uint32_t GRXSTSP; /*!< Receive Sts Q Read & POP Register 020h*/
\r
826 __IO uint32_t GRXFSIZ; /* Receive FIFO Size Register 024h*/
\r
827 __IO uint32_t DIEPTXF0_HNPTXFSIZ; /*!< EP0 / Non Periodic Tx FIFO Size Register 028h*/
\r
828 __IO uint32_t HNPTXSTS; /*!< Non Periodic Tx FIFO/Queue Sts reg 02Ch*/
\r
829 uint32_t Reserved30[2]; /* Reserved 030h*/
\r
830 __IO uint32_t GCCFG; /* General Purpose IO Register 038h*/
\r
831 __IO uint32_t CID; /* User ID Register 03Ch*/
\r
832 uint32_t Reserved40[48]; /* Reserved 040h-0FFh*/
\r
833 __IO uint32_t HPTXFSIZ; /* Host Periodic Tx FIFO Size Reg 100h*/
\r
834 __IO uint32_t DIEPTXF[0x0F];/* dev Periodic Transmit FIFO */
\r
836 USB_OTG_GlobalTypeDef;
\r
841 * @brief __device_Registers
\r
845 __IO uint32_t DCFG; /* dev Configuration Register 800h*/
\r
846 __IO uint32_t DCTL; /* dev Control Register 804h*/
\r
847 __IO uint32_t DSTS; /* dev Status Register (RO) 808h*/
\r
848 uint32_t Reserved0C; /* Reserved 80Ch*/
\r
849 __IO uint32_t DIEPMSK; /* dev IN Endpoint Mask 810h*/
\r
850 __IO uint32_t DOEPMSK; /* dev OUT Endpoint Mask 814h*/
\r
851 __IO uint32_t DAINT; /* dev All Endpoints Itr Reg 818h*/
\r
852 __IO uint32_t DAINTMSK; /* dev All Endpoints Itr Mask 81Ch*/
\r
853 uint32_t Reserved20; /* Reserved 820h*/
\r
854 uint32_t Reserved9; /* Reserved 824h*/
\r
855 __IO uint32_t DVBUSDIS; /* dev VBUS discharge Register 828h*/
\r
856 __IO uint32_t DVBUSPULSE; /* dev VBUS Pulse Register 82Ch*/
\r
857 __IO uint32_t DTHRCTL; /* dev thr 830h*/
\r
858 __IO uint32_t DIEPEMPMSK; /* dev empty msk 834h*/
\r
859 __IO uint32_t DEACHINT; /* dedicated EP interrupt 838h*/
\r
860 __IO uint32_t DEACHMSK; /* dedicated EP msk 83Ch*/
\r
861 uint32_t Reserved40; /* dedicated EP mask 840h*/
\r
862 __IO uint32_t DINEP1MSK; /* dedicated EP mask 844h*/
\r
863 uint32_t Reserved44[15]; /* Reserved 844-87Ch*/
\r
864 __IO uint32_t DOUTEP1MSK; /* dedicated EP msk 884h*/
\r
866 USB_OTG_DeviceTypeDef;
\r
870 * @brief __IN_Endpoint-Specific_Register
\r
874 __IO uint32_t DIEPCTL; /* dev IN Endpoint Control Reg 900h + (ep_num * 20h) + 00h*/
\r
875 uint32_t Reserved04; /* Reserved 900h + (ep_num * 20h) + 04h*/
\r
876 __IO uint32_t DIEPINT; /* dev IN Endpoint Itr Reg 900h + (ep_num * 20h) + 08h*/
\r
877 uint32_t Reserved0C; /* Reserved 900h + (ep_num * 20h) + 0Ch*/
\r
878 __IO uint32_t DIEPTSIZ; /* IN Endpoint Txfer Size 900h + (ep_num * 20h) + 10h*/
\r
879 __IO uint32_t DIEPDMA; /* IN Endpoint DMA Address Reg 900h + (ep_num * 20h) + 14h*/
\r
880 __IO uint32_t DTXFSTS;/*IN Endpoint Tx FIFO Status Reg 900h + (ep_num * 20h) + 18h*/
\r
881 uint32_t Reserved18; /* Reserved 900h+(ep_num*20h)+1Ch-900h+ (ep_num * 20h) + 1Ch*/
\r
883 USB_OTG_INEndpointTypeDef;
\r
887 * @brief __OUT_Endpoint-Specific_Registers
\r
891 __IO uint32_t DOEPCTL; /* dev OUT Endpoint Control Reg B00h + (ep_num * 20h) + 00h*/
\r
892 uint32_t Reserved04; /* Reserved B00h + (ep_num * 20h) + 04h*/
\r
893 __IO uint32_t DOEPINT; /* dev OUT Endpoint Itr Reg B00h + (ep_num * 20h) + 08h*/
\r
894 uint32_t Reserved0C; /* Reserved B00h + (ep_num * 20h) + 0Ch*/
\r
895 __IO uint32_t DOEPTSIZ; /* dev OUT Endpoint Txfer Size B00h + (ep_num * 20h) + 10h*/
\r
896 __IO uint32_t DOEPDMA; /* dev OUT Endpoint DMA Address B00h + (ep_num * 20h) + 14h*/
\r
897 uint32_t Reserved18[2]; /* Reserved B00h + (ep_num * 20h) + 18h - B00h + (ep_num * 20h) + 1Ch*/
\r
899 USB_OTG_OUTEndpointTypeDef;
\r
903 * @brief __Host_Mode_Register_Structures
\r
907 __IO uint32_t HCFG; /* Host Configuration Register 400h*/
\r
908 __IO uint32_t HFIR; /* Host Frame Interval Register 404h*/
\r
909 __IO uint32_t HFNUM; /* Host Frame Nbr/Frame Remaining 408h*/
\r
910 uint32_t Reserved40C; /* Reserved 40Ch*/
\r
911 __IO uint32_t HPTXSTS; /* Host Periodic Tx FIFO/ Queue Status 410h*/
\r
912 __IO uint32_t HAINT; /* Host All Channels Interrupt Register 414h*/
\r
913 __IO uint32_t HAINTMSK; /* Host All Channels Interrupt Mask 418h*/
\r
915 USB_OTG_HostTypeDef;
\r
919 * @brief __Host_Channel_Specific_Registers
\r
923 __IO uint32_t HCCHAR;
\r
924 __IO uint32_t HCSPLT;
\r
925 __IO uint32_t HCINT;
\r
926 __IO uint32_t HCINTMSK;
\r
927 __IO uint32_t HCTSIZ;
\r
928 __IO uint32_t HCDMA;
\r
929 uint32_t Reserved[2];
\r
931 USB_OTG_HostChannelTypeDef;
\r
935 * @brief Peripheral_memory_map
\r
937 #define FLASH_BASE ((uint32_t)0x08000000) /*!< FLASH(up to 1 MB) base address in the alias region */
\r
938 #define CCMDATARAM_BASE ((uint32_t)0x10000000) /*!< CCM(core coupled memory) data RAM(64 KB) base address in the alias region */
\r
939 #define SRAM1_BASE ((uint32_t)0x20000000) /*!< SRAM1(112 KB) base address in the alias region */
\r
940 #define SRAM2_BASE ((uint32_t)0x2001C000) /*!< SRAM2(16 KB) base address in the alias region */
\r
941 #define SRAM3_BASE ((uint32_t)0x20020000) /*!< SRAM3(64 KB) base address in the alias region */
\r
942 #define PERIPH_BASE ((uint32_t)0x40000000) /*!< Peripheral base address in the alias region */
\r
943 #define BKPSRAM_BASE ((uint32_t)0x40024000) /*!< Backup SRAM(4 KB) base address in the alias region */
\r
944 #define FSMC_R_BASE ((uint32_t)0xA0000000) /*!< FSMC registers base address */
\r
945 #define CCMDATARAM_BB_BASE ((uint32_t)0x12000000) /*!< CCM(core coupled memory) data RAM(64 KB) base address in the bit-band region */
\r
946 #define SRAM1_BB_BASE ((uint32_t)0x22000000) /*!< SRAM1(112 KB) base address in the bit-band region */
\r
947 #define SRAM2_BB_BASE ((uint32_t)0x2201C000) /*!< SRAM2(16 KB) base address in the bit-band region */
\r
948 #define SRAM3_BB_BASE ((uint32_t)0x22020000) /*!< SRAM3(64 KB) base address in the bit-band region */
\r
949 #define PERIPH_BB_BASE ((uint32_t)0x42000000) /*!< Peripheral base address in the bit-band region */
\r
950 #define BKPSRAM_BB_BASE ((uint32_t)0x42024000) /*!< Backup SRAM(4 KB) base address in the bit-band region */
\r
952 /* Legacy defines */
\r
953 #define SRAM_BASE SRAM1_BASE
\r
954 #define SRAM_BB_BASE SRAM1_BB_BASE
\r
957 /*!< Peripheral memory map */
\r
958 #define APB1PERIPH_BASE PERIPH_BASE
\r
959 #define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000)
\r
960 #define AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000)
\r
961 #define AHB2PERIPH_BASE (PERIPH_BASE + 0x10000000)
\r
963 /*!< APB1 peripherals */
\r
964 #define TIM2_BASE (APB1PERIPH_BASE + 0x0000)
\r
965 #define TIM3_BASE (APB1PERIPH_BASE + 0x0400)
\r
966 #define TIM4_BASE (APB1PERIPH_BASE + 0x0800)
\r
967 #define TIM5_BASE (APB1PERIPH_BASE + 0x0C00)
\r
968 #define TIM6_BASE (APB1PERIPH_BASE + 0x1000)
\r
969 #define TIM7_BASE (APB1PERIPH_BASE + 0x1400)
\r
970 #define TIM12_BASE (APB1PERIPH_BASE + 0x1800)
\r
971 #define TIM13_BASE (APB1PERIPH_BASE + 0x1C00)
\r
972 #define TIM14_BASE (APB1PERIPH_BASE + 0x2000)
\r
973 #define RTC_BASE (APB1PERIPH_BASE + 0x2800)
\r
974 #define WWDG_BASE (APB1PERIPH_BASE + 0x2C00)
\r
975 #define IWDG_BASE (APB1PERIPH_BASE + 0x3000)
\r
976 #define I2S2ext_BASE (APB1PERIPH_BASE + 0x3400)
\r
977 #define SPI2_BASE (APB1PERIPH_BASE + 0x3800)
\r
978 #define SPI3_BASE (APB1PERIPH_BASE + 0x3C00)
\r
979 #define I2S3ext_BASE (APB1PERIPH_BASE + 0x4000)
\r
980 #define USART2_BASE (APB1PERIPH_BASE + 0x4400)
\r
981 #define USART3_BASE (APB1PERIPH_BASE + 0x4800)
\r
982 #define UART4_BASE (APB1PERIPH_BASE + 0x4C00)
\r
983 #define UART5_BASE (APB1PERIPH_BASE + 0x5000)
\r
984 #define I2C1_BASE (APB1PERIPH_BASE + 0x5400)
\r
985 #define I2C2_BASE (APB1PERIPH_BASE + 0x5800)
\r
986 #define I2C3_BASE (APB1PERIPH_BASE + 0x5C00)
\r
987 #define CAN1_BASE (APB1PERIPH_BASE + 0x6400)
\r
988 #define CAN2_BASE (APB1PERIPH_BASE + 0x6800)
\r
989 #define PWR_BASE (APB1PERIPH_BASE + 0x7000)
\r
990 #define DAC_BASE (APB1PERIPH_BASE + 0x7400)
\r
992 /*!< APB2 peripherals */
\r
993 #define TIM1_BASE (APB2PERIPH_BASE + 0x0000)
\r
994 #define TIM8_BASE (APB2PERIPH_BASE + 0x0400)
\r
995 #define USART1_BASE (APB2PERIPH_BASE + 0x1000)
\r
996 #define USART6_BASE (APB2PERIPH_BASE + 0x1400)
\r
997 #define ADC1_BASE (APB2PERIPH_BASE + 0x2000)
\r
998 #define ADC2_BASE (APB2PERIPH_BASE + 0x2100)
\r
999 #define ADC3_BASE (APB2PERIPH_BASE + 0x2200)
\r
1000 #define ADC_BASE (APB2PERIPH_BASE + 0x2300)
\r
1001 #define SDIO_BASE (APB2PERIPH_BASE + 0x2C00)
\r
1002 #define SPI1_BASE (APB2PERIPH_BASE + 0x3000)
\r
1003 #define SYSCFG_BASE (APB2PERIPH_BASE + 0x3800)
\r
1004 #define EXTI_BASE (APB2PERIPH_BASE + 0x3C00)
\r
1005 #define TIM9_BASE (APB2PERIPH_BASE + 0x4000)
\r
1006 #define TIM10_BASE (APB2PERIPH_BASE + 0x4400)
\r
1007 #define TIM11_BASE (APB2PERIPH_BASE + 0x4800)
\r
1009 /*!< AHB1 peripherals */
\r
1010 #define GPIOA_BASE (AHB1PERIPH_BASE + 0x0000)
\r
1011 #define GPIOB_BASE (AHB1PERIPH_BASE + 0x0400)
\r
1012 #define GPIOC_BASE (AHB1PERIPH_BASE + 0x0800)
\r
1013 #define GPIOD_BASE (AHB1PERIPH_BASE + 0x0C00)
\r
1014 #define GPIOE_BASE (AHB1PERIPH_BASE + 0x1000)
\r
1015 #define GPIOF_BASE (AHB1PERIPH_BASE + 0x1400)
\r
1016 #define GPIOG_BASE (AHB1PERIPH_BASE + 0x1800)
\r
1017 #define GPIOH_BASE (AHB1PERIPH_BASE + 0x1C00)
\r
1018 #define GPIOI_BASE (AHB1PERIPH_BASE + 0x2000)
\r
1019 #define CRC_BASE (AHB1PERIPH_BASE + 0x3000)
\r
1020 #define RCC_BASE (AHB1PERIPH_BASE + 0x3800)
\r
1021 #define FLASH_R_BASE (AHB1PERIPH_BASE + 0x3C00)
\r
1022 #define DMA1_BASE (AHB1PERIPH_BASE + 0x6000)
\r
1023 #define DMA1_Stream0_BASE (DMA1_BASE + 0x010)
\r
1024 #define DMA1_Stream1_BASE (DMA1_BASE + 0x028)
\r
1025 #define DMA1_Stream2_BASE (DMA1_BASE + 0x040)
\r
1026 #define DMA1_Stream3_BASE (DMA1_BASE + 0x058)
\r
1027 #define DMA1_Stream4_BASE (DMA1_BASE + 0x070)
\r
1028 #define DMA1_Stream5_BASE (DMA1_BASE + 0x088)
\r
1029 #define DMA1_Stream6_BASE (DMA1_BASE + 0x0A0)
\r
1030 #define DMA1_Stream7_BASE (DMA1_BASE + 0x0B8)
\r
1031 #define DMA2_BASE (AHB1PERIPH_BASE + 0x6400)
\r
1032 #define DMA2_Stream0_BASE (DMA2_BASE + 0x010)
\r
1033 #define DMA2_Stream1_BASE (DMA2_BASE + 0x028)
\r
1034 #define DMA2_Stream2_BASE (DMA2_BASE + 0x040)
\r
1035 #define DMA2_Stream3_BASE (DMA2_BASE + 0x058)
\r
1036 #define DMA2_Stream4_BASE (DMA2_BASE + 0x070)
\r
1037 #define DMA2_Stream5_BASE (DMA2_BASE + 0x088)
\r
1038 #define DMA2_Stream6_BASE (DMA2_BASE + 0x0A0)
\r
1039 #define DMA2_Stream7_BASE (DMA2_BASE + 0x0B8)
\r
1040 #define ETH_BASE (AHB1PERIPH_BASE + 0x8000)
\r
1041 #define ETH_MAC_BASE (ETH_BASE)
\r
1042 #define ETH_MMC_BASE (ETH_BASE + 0x0100)
\r
1043 #define ETH_PTP_BASE (ETH_BASE + 0x0700)
\r
1044 #define ETH_DMA_BASE (ETH_BASE + 0x1000)
\r
1046 /*!< AHB2 peripherals */
\r
1047 #define DCMI_BASE (AHB2PERIPH_BASE + 0x50000)
\r
1048 #define RNG_BASE (AHB2PERIPH_BASE + 0x60800)
\r
1050 /*!< FSMC Bankx registers base address */
\r
1051 #define FSMC_Bank1_R_BASE (FSMC_R_BASE + 0x0000)
\r
1052 #define FSMC_Bank1E_R_BASE (FSMC_R_BASE + 0x0104)
\r
1053 #define FSMC_Bank2_3_R_BASE (FSMC_R_BASE + 0x0060)
\r
1054 #define FSMC_Bank4_R_BASE (FSMC_R_BASE + 0x00A0)
\r
1056 /* Debug MCU registers base address */
\r
1057 #define DBGMCU_BASE ((uint32_t )0xE0042000)
\r
1059 /*!< USB registers base address */
\r
1060 #define USB_OTG_HS_PERIPH_BASE ((uint32_t )0x40040000)
\r
1061 #define USB_OTG_FS_PERIPH_BASE ((uint32_t )0x50000000)
\r
1063 #define USB_OTG_GLOBAL_BASE ((uint32_t )0x000)
\r
1064 #define USB_OTG_DEVICE_BASE ((uint32_t )0x800)
\r
1065 #define USB_OTG_IN_ENDPOINT_BASE ((uint32_t )0x900)
\r
1066 #define USB_OTG_OUT_ENDPOINT_BASE ((uint32_t )0xB00)
\r
1067 #define USB_OTG_EP_REG_SIZE ((uint32_t )0x20)
\r
1068 #define USB_OTG_HOST_BASE ((uint32_t )0x400)
\r
1069 #define USB_OTG_HOST_PORT_BASE ((uint32_t )0x440)
\r
1070 #define USB_OTG_HOST_CHANNEL_BASE ((uint32_t )0x500)
\r
1071 #define USB_OTG_HOST_CHANNEL_SIZE ((uint32_t )0x20)
\r
1072 #define USB_OTG_PCGCCTL_BASE ((uint32_t )0xE00)
\r
1073 #define USB_OTG_FIFO_BASE ((uint32_t )0x1000)
\r
1074 #define USB_OTG_FIFO_SIZE ((uint32_t )0x1000)
\r
1080 /** @addtogroup Peripheral_declaration
\r
1083 #define TIM2 ((TIM_TypeDef *) TIM2_BASE)
\r
1084 #define TIM3 ((TIM_TypeDef *) TIM3_BASE)
\r
1085 #define TIM4 ((TIM_TypeDef *) TIM4_BASE)
\r
1086 #define TIM5 ((TIM_TypeDef *) TIM5_BASE)
\r
1087 #define TIM6 ((TIM_TypeDef *) TIM6_BASE)
\r
1088 #define TIM7 ((TIM_TypeDef *) TIM7_BASE)
\r
1089 #define TIM12 ((TIM_TypeDef *) TIM12_BASE)
\r
1090 #define TIM13 ((TIM_TypeDef *) TIM13_BASE)
\r
1091 #define TIM14 ((TIM_TypeDef *) TIM14_BASE)
\r
1092 #define RTC ((RTC_TypeDef *) RTC_BASE)
\r
1093 #define WWDG ((WWDG_TypeDef *) WWDG_BASE)
\r
1094 #define IWDG ((IWDG_TypeDef *) IWDG_BASE)
\r
1095 #define I2S2ext ((SPI_TypeDef *) I2S2ext_BASE)
\r
1096 #define SPI2 ((SPI_TypeDef *) SPI2_BASE)
\r
1097 #define SPI3 ((SPI_TypeDef *) SPI3_BASE)
\r
1098 #define I2S3ext ((SPI_TypeDef *) I2S3ext_BASE)
\r
1099 #define USART2 ((USART_TypeDef *) USART2_BASE)
\r
1100 #define USART3 ((USART_TypeDef *) USART3_BASE)
\r
1101 #define UART4 ((USART_TypeDef *) UART4_BASE)
\r
1102 #define UART5 ((USART_TypeDef *) UART5_BASE)
\r
1103 #define I2C1 ((I2C_TypeDef *) I2C1_BASE)
\r
1104 #define I2C2 ((I2C_TypeDef *) I2C2_BASE)
\r
1105 #define I2C3 ((I2C_TypeDef *) I2C3_BASE)
\r
1106 #define CAN1 ((CAN_TypeDef *) CAN1_BASE)
\r
1107 #define CAN2 ((CAN_TypeDef *) CAN2_BASE)
\r
1108 #define PWR ((PWR_TypeDef *) PWR_BASE)
\r
1109 #define DAC ((DAC_TypeDef *) DAC_BASE)
\r
1110 #define TIM1 ((TIM_TypeDef *) TIM1_BASE)
\r
1111 #define TIM8 ((TIM_TypeDef *) TIM8_BASE)
\r
1112 #define USART1 ((USART_TypeDef *) USART1_BASE)
\r
1113 #define USART6 ((USART_TypeDef *) USART6_BASE)
\r
1114 #define ADC ((ADC_Common_TypeDef *) ADC_BASE)
\r
1115 #define ADC1 ((ADC_TypeDef *) ADC1_BASE)
\r
1116 #define ADC2 ((ADC_TypeDef *) ADC2_BASE)
\r
1117 #define ADC3 ((ADC_TypeDef *) ADC3_BASE)
\r
1118 #define SDIO ((SDIO_TypeDef *) SDIO_BASE)
\r
1119 #define SPI1 ((SPI_TypeDef *) SPI1_BASE)
\r
1120 #define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE)
\r
1121 #define EXTI ((EXTI_TypeDef *) EXTI_BASE)
\r
1122 #define TIM9 ((TIM_TypeDef *) TIM9_BASE)
\r
1123 #define TIM10 ((TIM_TypeDef *) TIM10_BASE)
\r
1124 #define TIM11 ((TIM_TypeDef *) TIM11_BASE)
\r
1125 #define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)
\r
1126 #define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)
\r
1127 #define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)
\r
1128 #define GPIOD ((GPIO_TypeDef *) GPIOD_BASE)
\r
1129 #define GPIOE ((GPIO_TypeDef *) GPIOE_BASE)
\r
1130 #define GPIOF ((GPIO_TypeDef *) GPIOF_BASE)
\r
1131 #define GPIOG ((GPIO_TypeDef *) GPIOG_BASE)
\r
1132 #define GPIOH ((GPIO_TypeDef *) GPIOH_BASE)
\r
1133 #define GPIOI ((GPIO_TypeDef *) GPIOI_BASE)
\r
1134 #define CRC ((CRC_TypeDef *) CRC_BASE)
\r
1135 #define RCC ((RCC_TypeDef *) RCC_BASE)
\r
1136 #define FLASH ((FLASH_TypeDef *) FLASH_R_BASE)
\r
1137 #define DMA1 ((DMA_TypeDef *) DMA1_BASE)
\r
1138 #define DMA1_Stream0 ((DMA_Stream_TypeDef *) DMA1_Stream0_BASE)
\r
1139 #define DMA1_Stream1 ((DMA_Stream_TypeDef *) DMA1_Stream1_BASE)
\r
1140 #define DMA1_Stream2 ((DMA_Stream_TypeDef *) DMA1_Stream2_BASE)
\r
1141 #define DMA1_Stream3 ((DMA_Stream_TypeDef *) DMA1_Stream3_BASE)
\r
1142 #define DMA1_Stream4 ((DMA_Stream_TypeDef *) DMA1_Stream4_BASE)
\r
1143 #define DMA1_Stream5 ((DMA_Stream_TypeDef *) DMA1_Stream5_BASE)
\r
1144 #define DMA1_Stream6 ((DMA_Stream_TypeDef *) DMA1_Stream6_BASE)
\r
1145 #define DMA1_Stream7 ((DMA_Stream_TypeDef *) DMA1_Stream7_BASE)
\r
1146 #define DMA2 ((DMA_TypeDef *) DMA2_BASE)
\r
1147 #define DMA2_Stream0 ((DMA_Stream_TypeDef *) DMA2_Stream0_BASE)
\r
1148 #define DMA2_Stream1 ((DMA_Stream_TypeDef *) DMA2_Stream1_BASE)
\r
1149 #define DMA2_Stream2 ((DMA_Stream_TypeDef *) DMA2_Stream2_BASE)
\r
1150 #define DMA2_Stream3 ((DMA_Stream_TypeDef *) DMA2_Stream3_BASE)
\r
1151 #define DMA2_Stream4 ((DMA_Stream_TypeDef *) DMA2_Stream4_BASE)
\r
1152 #define DMA2_Stream5 ((DMA_Stream_TypeDef *) DMA2_Stream5_BASE)
\r
1153 #define DMA2_Stream6 ((DMA_Stream_TypeDef *) DMA2_Stream6_BASE)
\r
1154 #define DMA2_Stream7 ((DMA_Stream_TypeDef *) DMA2_Stream7_BASE)
\r
1155 #define ETH ((ETH_TypeDef *) ETH_BASE)
\r
1156 #define DCMI ((DCMI_TypeDef *) DCMI_BASE)
\r
1157 #define RNG ((RNG_TypeDef *) RNG_BASE)
\r
1158 #define FSMC_Bank1 ((FSMC_Bank1_TypeDef *) FSMC_Bank1_R_BASE)
\r
1159 #define FSMC_Bank1E ((FSMC_Bank1E_TypeDef *) FSMC_Bank1E_R_BASE)
\r
1160 #define FSMC_Bank2_3 ((FSMC_Bank2_3_TypeDef *) FSMC_Bank2_3_R_BASE)
\r
1161 #define FSMC_Bank4 ((FSMC_Bank4_TypeDef *) FSMC_Bank4_R_BASE)
\r
1163 #define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)
\r
1165 #define USB_OTG_FS ((USB_OTG_GlobalTypeDef *) USB_OTG_FS_PERIPH_BASE)
\r
1166 #define USB_OTG_HS ((USB_OTG_GlobalTypeDef *) USB_OTG_HS_PERIPH_BASE)
\r
1172 /** @addtogroup Exported_constants
\r
1176 /** @addtogroup Peripheral_Registers_Bits_Definition
\r
1180 /******************************************************************************/
\r
1181 /* Peripheral Registers_Bits_Definition */
\r
1182 /******************************************************************************/
\r
1184 /******************************************************************************/
\r
1186 /* Analog to Digital Converter */
\r
1188 /******************************************************************************/
\r
1189 /******************** Bit definition for ADC_SR register ********************/
\r
1190 #define ADC_SR_AWD ((uint32_t)0x00000001) /*!<Analog watchdog flag */
\r
1191 #define ADC_SR_EOC ((uint32_t)0x00000002) /*!<End of conversion */
\r
1192 #define ADC_SR_JEOC ((uint32_t)0x00000004) /*!<Injected channel end of conversion */
\r
1193 #define ADC_SR_JSTRT ((uint32_t)0x00000008) /*!<Injected channel Start flag */
\r
1194 #define ADC_SR_STRT ((uint32_t)0x00000010) /*!<Regular channel Start flag */
\r
1195 #define ADC_SR_OVR ((uint32_t)0x00000020) /*!<Overrun flag */
\r
1197 /******************* Bit definition for ADC_CR1 register ********************/
\r
1198 #define ADC_CR1_AWDCH ((uint32_t)0x0000001F) /*!<AWDCH[4:0] bits (Analog watchdog channel select bits) */
\r
1199 #define ADC_CR1_AWDCH_0 ((uint32_t)0x00000001) /*!<Bit 0 */
\r
1200 #define ADC_CR1_AWDCH_1 ((uint32_t)0x00000002) /*!<Bit 1 */
\r
1201 #define ADC_CR1_AWDCH_2 ((uint32_t)0x00000004) /*!<Bit 2 */
\r
1202 #define ADC_CR1_AWDCH_3 ((uint32_t)0x00000008) /*!<Bit 3 */
\r
1203 #define ADC_CR1_AWDCH_4 ((uint32_t)0x00000010) /*!<Bit 4 */
\r
1204 #define ADC_CR1_EOCIE ((uint32_t)0x00000020) /*!<Interrupt enable for EOC */
\r
1205 #define ADC_CR1_AWDIE ((uint32_t)0x00000040) /*!<AAnalog Watchdog interrupt enable */
\r
1206 #define ADC_CR1_JEOCIE ((uint32_t)0x00000080) /*!<Interrupt enable for injected channels */
\r
1207 #define ADC_CR1_SCAN ((uint32_t)0x00000100) /*!<Scan mode */
\r
1208 #define ADC_CR1_AWDSGL ((uint32_t)0x00000200) /*!<Enable the watchdog on a single channel in scan mode */
\r
1209 #define ADC_CR1_JAUTO ((uint32_t)0x00000400) /*!<Automatic injected group conversion */
\r
1210 #define ADC_CR1_DISCEN ((uint32_t)0x00000800) /*!<Discontinuous mode on regular channels */
\r
1211 #define ADC_CR1_JDISCEN ((uint32_t)0x00001000) /*!<Discontinuous mode on injected channels */
\r
1212 #define ADC_CR1_DISCNUM ((uint32_t)0x0000E000) /*!<DISCNUM[2:0] bits (Discontinuous mode channel count) */
\r
1213 #define ADC_CR1_DISCNUM_0 ((uint32_t)0x00002000) /*!<Bit 0 */
\r
1214 #define ADC_CR1_DISCNUM_1 ((uint32_t)0x00004000) /*!<Bit 1 */
\r
1215 #define ADC_CR1_DISCNUM_2 ((uint32_t)0x00008000) /*!<Bit 2 */
\r
1216 #define ADC_CR1_JAWDEN ((uint32_t)0x00400000) /*!<Analog watchdog enable on injected channels */
\r
1217 #define ADC_CR1_AWDEN ((uint32_t)0x00800000) /*!<Analog watchdog enable on regular channels */
\r
1218 #define ADC_CR1_RES ((uint32_t)0x03000000) /*!<RES[2:0] bits (Resolution) */
\r
1219 #define ADC_CR1_RES_0 ((uint32_t)0x01000000) /*!<Bit 0 */
\r
1220 #define ADC_CR1_RES_1 ((uint32_t)0x02000000) /*!<Bit 1 */
\r
1221 #define ADC_CR1_OVRIE ((uint32_t)0x04000000) /*!<overrun interrupt enable */
\r
1223 /******************* Bit definition for ADC_CR2 register ********************/
\r
1224 #define ADC_CR2_ADON ((uint32_t)0x00000001) /*!<A/D Converter ON / OFF */
\r
1225 #define ADC_CR2_CONT ((uint32_t)0x00000002) /*!<Continuous Conversion */
\r
1226 #define ADC_CR2_DMA ((uint32_t)0x00000100) /*!<Direct Memory access mode */
\r
1227 #define ADC_CR2_DDS ((uint32_t)0x00000200) /*!<DMA disable selection (Single ADC) */
\r
1228 #define ADC_CR2_EOCS ((uint32_t)0x00000400) /*!<End of conversion selection */
\r
1229 #define ADC_CR2_ALIGN ((uint32_t)0x00000800) /*!<Data Alignment */
\r
1230 #define ADC_CR2_JEXTSEL ((uint32_t)0x000F0000) /*!<JEXTSEL[3:0] bits (External event select for injected group) */
\r
1231 #define ADC_CR2_JEXTSEL_0 ((uint32_t)0x00010000) /*!<Bit 0 */
\r
1232 #define ADC_CR2_JEXTSEL_1 ((uint32_t)0x00020000) /*!<Bit 1 */
\r
1233 #define ADC_CR2_JEXTSEL_2 ((uint32_t)0x00040000) /*!<Bit 2 */
\r
1234 #define ADC_CR2_JEXTSEL_3 ((uint32_t)0x00080000) /*!<Bit 3 */
\r
1235 #define ADC_CR2_JEXTEN ((uint32_t)0x00300000) /*!<JEXTEN[1:0] bits (External Trigger Conversion mode for injected channelsp) */
\r
1236 #define ADC_CR2_JEXTEN_0 ((uint32_t)0x00100000) /*!<Bit 0 */
\r
1237 #define ADC_CR2_JEXTEN_1 ((uint32_t)0x00200000) /*!<Bit 1 */
\r
1238 #define ADC_CR2_JSWSTART ((uint32_t)0x00400000) /*!<Start Conversion of injected channels */
\r
1239 #define ADC_CR2_EXTSEL ((uint32_t)0x0F000000) /*!<EXTSEL[3:0] bits (External Event Select for regular group) */
\r
1240 #define ADC_CR2_EXTSEL_0 ((uint32_t)0x01000000) /*!<Bit 0 */
\r
1241 #define ADC_CR2_EXTSEL_1 ((uint32_t)0x02000000) /*!<Bit 1 */
\r
1242 #define ADC_CR2_EXTSEL_2 ((uint32_t)0x04000000) /*!<Bit 2 */
\r
1243 #define ADC_CR2_EXTSEL_3 ((uint32_t)0x08000000) /*!<Bit 3 */
\r
1244 #define ADC_CR2_EXTEN ((uint32_t)0x30000000) /*!<EXTEN[1:0] bits (External Trigger Conversion mode for regular channelsp) */
\r
1245 #define ADC_CR2_EXTEN_0 ((uint32_t)0x10000000) /*!<Bit 0 */
\r
1246 #define ADC_CR2_EXTEN_1 ((uint32_t)0x20000000) /*!<Bit 1 */
\r
1247 #define ADC_CR2_SWSTART ((uint32_t)0x40000000) /*!<Start Conversion of regular channels */
\r
1249 /****************** Bit definition for ADC_SMPR1 register *******************/
\r
1250 #define ADC_SMPR1_SMP10 ((uint32_t)0x00000007) /*!<SMP10[2:0] bits (Channel 10 Sample time selection) */
\r
1251 #define ADC_SMPR1_SMP10_0 ((uint32_t)0x00000001) /*!<Bit 0 */
\r
1252 #define ADC_SMPR1_SMP10_1 ((uint32_t)0x00000002) /*!<Bit 1 */
\r
1253 #define ADC_SMPR1_SMP10_2 ((uint32_t)0x00000004) /*!<Bit 2 */
\r
1254 #define ADC_SMPR1_SMP11 ((uint32_t)0x00000038) /*!<SMP11[2:0] bits (Channel 11 Sample time selection) */
\r
1255 #define ADC_SMPR1_SMP11_0 ((uint32_t)0x00000008) /*!<Bit 0 */
\r
1256 #define ADC_SMPR1_SMP11_1 ((uint32_t)0x00000010) /*!<Bit 1 */
\r
1257 #define ADC_SMPR1_SMP11_2 ((uint32_t)0x00000020) /*!<Bit 2 */
\r
1258 #define ADC_SMPR1_SMP12 ((uint32_t)0x000001C0) /*!<SMP12[2:0] bits (Channel 12 Sample time selection) */
\r
1259 #define ADC_SMPR1_SMP12_0 ((uint32_t)0x00000040) /*!<Bit 0 */
\r
1260 #define ADC_SMPR1_SMP12_1 ((uint32_t)0x00000080) /*!<Bit 1 */
\r
1261 #define ADC_SMPR1_SMP12_2 ((uint32_t)0x00000100) /*!<Bit 2 */
\r
1262 #define ADC_SMPR1_SMP13 ((uint32_t)0x00000E00) /*!<SMP13[2:0] bits (Channel 13 Sample time selection) */
\r
1263 #define ADC_SMPR1_SMP13_0 ((uint32_t)0x00000200) /*!<Bit 0 */
\r
1264 #define ADC_SMPR1_SMP13_1 ((uint32_t)0x00000400) /*!<Bit 1 */
\r
1265 #define ADC_SMPR1_SMP13_2 ((uint32_t)0x00000800) /*!<Bit 2 */
\r
1266 #define ADC_SMPR1_SMP14 ((uint32_t)0x00007000) /*!<SMP14[2:0] bits (Channel 14 Sample time selection) */
\r
1267 #define ADC_SMPR1_SMP14_0 ((uint32_t)0x00001000) /*!<Bit 0 */
\r
1268 #define ADC_SMPR1_SMP14_1 ((uint32_t)0x00002000) /*!<Bit 1 */
\r
1269 #define ADC_SMPR1_SMP14_2 ((uint32_t)0x00004000) /*!<Bit 2 */
\r
1270 #define ADC_SMPR1_SMP15 ((uint32_t)0x00038000) /*!<SMP15[2:0] bits (Channel 15 Sample time selection) */
\r
1271 #define ADC_SMPR1_SMP15_0 ((uint32_t)0x00008000) /*!<Bit 0 */
\r
1272 #define ADC_SMPR1_SMP15_1 ((uint32_t)0x00010000) /*!<Bit 1 */
\r
1273 #define ADC_SMPR1_SMP15_2 ((uint32_t)0x00020000) /*!<Bit 2 */
\r
1274 #define ADC_SMPR1_SMP16 ((uint32_t)0x001C0000) /*!<SMP16[2:0] bits (Channel 16 Sample time selection) */
\r
1275 #define ADC_SMPR1_SMP16_0 ((uint32_t)0x00040000) /*!<Bit 0 */
\r
1276 #define ADC_SMPR1_SMP16_1 ((uint32_t)0x00080000) /*!<Bit 1 */
\r
1277 #define ADC_SMPR1_SMP16_2 ((uint32_t)0x00100000) /*!<Bit 2 */
\r
1278 #define ADC_SMPR1_SMP17 ((uint32_t)0x00E00000) /*!<SMP17[2:0] bits (Channel 17 Sample time selection) */
\r
1279 #define ADC_SMPR1_SMP17_0 ((uint32_t)0x00200000) /*!<Bit 0 */
\r
1280 #define ADC_SMPR1_SMP17_1 ((uint32_t)0x00400000) /*!<Bit 1 */
\r
1281 #define ADC_SMPR1_SMP17_2 ((uint32_t)0x00800000) /*!<Bit 2 */
\r
1282 #define ADC_SMPR1_SMP18 ((uint32_t)0x07000000) /*!<SMP18[2:0] bits (Channel 18 Sample time selection) */
\r
1283 #define ADC_SMPR1_SMP18_0 ((uint32_t)0x01000000) /*!<Bit 0 */
\r
1284 #define ADC_SMPR1_SMP18_1 ((uint32_t)0x02000000) /*!<Bit 1 */
\r
1285 #define ADC_SMPR1_SMP18_2 ((uint32_t)0x04000000) /*!<Bit 2 */
\r
1287 /****************** Bit definition for ADC_SMPR2 register *******************/
\r
1288 #define ADC_SMPR2_SMP0 ((uint32_t)0x00000007) /*!<SMP0[2:0] bits (Channel 0 Sample time selection) */
\r
1289 #define ADC_SMPR2_SMP0_0 ((uint32_t)0x00000001) /*!<Bit 0 */
\r
1290 #define ADC_SMPR2_SMP0_1 ((uint32_t)0x00000002) /*!<Bit 1 */
\r
1291 #define ADC_SMPR2_SMP0_2 ((uint32_t)0x00000004) /*!<Bit 2 */
\r
1292 #define ADC_SMPR2_SMP1 ((uint32_t)0x00000038) /*!<SMP1[2:0] bits (Channel 1 Sample time selection) */
\r
1293 #define ADC_SMPR2_SMP1_0 ((uint32_t)0x00000008) /*!<Bit 0 */
\r
1294 #define ADC_SMPR2_SMP1_1 ((uint32_t)0x00000010) /*!<Bit 1 */
\r
1295 #define ADC_SMPR2_SMP1_2 ((uint32_t)0x00000020) /*!<Bit 2 */
\r
1296 #define ADC_SMPR2_SMP2 ((uint32_t)0x000001C0) /*!<SMP2[2:0] bits (Channel 2 Sample time selection) */
\r
1297 #define ADC_SMPR2_SMP2_0 ((uint32_t)0x00000040) /*!<Bit 0 */
\r
1298 #define ADC_SMPR2_SMP2_1 ((uint32_t)0x00000080) /*!<Bit 1 */
\r
1299 #define ADC_SMPR2_SMP2_2 ((uint32_t)0x00000100) /*!<Bit 2 */
\r
1300 #define ADC_SMPR2_SMP3 ((uint32_t)0x00000E00) /*!<SMP3[2:0] bits (Channel 3 Sample time selection) */
\r
1301 #define ADC_SMPR2_SMP3_0 ((uint32_t)0x00000200) /*!<Bit 0 */
\r
1302 #define ADC_SMPR2_SMP3_1 ((uint32_t)0x00000400) /*!<Bit 1 */
\r
1303 #define ADC_SMPR2_SMP3_2 ((uint32_t)0x00000800) /*!<Bit 2 */
\r
1304 #define ADC_SMPR2_SMP4 ((uint32_t)0x00007000) /*!<SMP4[2:0] bits (Channel 4 Sample time selection) */
\r
1305 #define ADC_SMPR2_SMP4_0 ((uint32_t)0x00001000) /*!<Bit 0 */
\r
1306 #define ADC_SMPR2_SMP4_1 ((uint32_t)0x00002000) /*!<Bit 1 */
\r
1307 #define ADC_SMPR2_SMP4_2 ((uint32_t)0x00004000) /*!<Bit 2 */
\r
1308 #define ADC_SMPR2_SMP5 ((uint32_t)0x00038000) /*!<SMP5[2:0] bits (Channel 5 Sample time selection) */
\r
1309 #define ADC_SMPR2_SMP5_0 ((uint32_t)0x00008000) /*!<Bit 0 */
\r
1310 #define ADC_SMPR2_SMP5_1 ((uint32_t)0x00010000) /*!<Bit 1 */
\r
1311 #define ADC_SMPR2_SMP5_2 ((uint32_t)0x00020000) /*!<Bit 2 */
\r
1312 #define ADC_SMPR2_SMP6 ((uint32_t)0x001C0000) /*!<SMP6[2:0] bits (Channel 6 Sample time selection) */
\r
1313 #define ADC_SMPR2_SMP6_0 ((uint32_t)0x00040000) /*!<Bit 0 */
\r
1314 #define ADC_SMPR2_SMP6_1 ((uint32_t)0x00080000) /*!<Bit 1 */
\r
1315 #define ADC_SMPR2_SMP6_2 ((uint32_t)0x00100000) /*!<Bit 2 */
\r
1316 #define ADC_SMPR2_SMP7 ((uint32_t)0x00E00000) /*!<SMP7[2:0] bits (Channel 7 Sample time selection) */
\r
1317 #define ADC_SMPR2_SMP7_0 ((uint32_t)0x00200000) /*!<Bit 0 */
\r
1318 #define ADC_SMPR2_SMP7_1 ((uint32_t)0x00400000) /*!<Bit 1 */
\r
1319 #define ADC_SMPR2_SMP7_2 ((uint32_t)0x00800000) /*!<Bit 2 */
\r
1320 #define ADC_SMPR2_SMP8 ((uint32_t)0x07000000) /*!<SMP8[2:0] bits (Channel 8 Sample time selection) */
\r
1321 #define ADC_SMPR2_SMP8_0 ((uint32_t)0x01000000) /*!<Bit 0 */
\r
1322 #define ADC_SMPR2_SMP8_1 ((uint32_t)0x02000000) /*!<Bit 1 */
\r
1323 #define ADC_SMPR2_SMP8_2 ((uint32_t)0x04000000) /*!<Bit 2 */
\r
1324 #define ADC_SMPR2_SMP9 ((uint32_t)0x38000000) /*!<SMP9[2:0] bits (Channel 9 Sample time selection) */
\r
1325 #define ADC_SMPR2_SMP9_0 ((uint32_t)0x08000000) /*!<Bit 0 */
\r
1326 #define ADC_SMPR2_SMP9_1 ((uint32_t)0x10000000) /*!<Bit 1 */
\r
1327 #define ADC_SMPR2_SMP9_2 ((uint32_t)0x20000000) /*!<Bit 2 */
\r
1329 /****************** Bit definition for ADC_JOFR1 register *******************/
\r
1330 #define ADC_JOFR1_JOFFSET1 ((uint32_t)0x0FFF) /*!<Data offset for injected channel 1 */
\r
1332 /****************** Bit definition for ADC_JOFR2 register *******************/
\r
1333 #define ADC_JOFR2_JOFFSET2 ((uint32_t)0x0FFF) /*!<Data offset for injected channel 2 */
\r
1335 /****************** Bit definition for ADC_JOFR3 register *******************/
\r
1336 #define ADC_JOFR3_JOFFSET3 ((uint32_t)0x0FFF) /*!<Data offset for injected channel 3 */
\r
1338 /****************** Bit definition for ADC_JOFR4 register *******************/
\r
1339 #define ADC_JOFR4_JOFFSET4 ((uint32_t)0x0FFF) /*!<Data offset for injected channel 4 */
\r
1341 /******************* Bit definition for ADC_HTR register ********************/
\r
1342 #define ADC_HTR_HT ((uint32_t)0x0FFF) /*!<Analog watchdog high threshold */
\r
1344 /******************* Bit definition for ADC_LTR register ********************/
\r
1345 #define ADC_LTR_LT ((uint32_t)0x0FFF) /*!<Analog watchdog low threshold */
\r
1347 /******************* Bit definition for ADC_SQR1 register *******************/
\r
1348 #define ADC_SQR1_SQ13 ((uint32_t)0x0000001F) /*!<SQ13[4:0] bits (13th conversion in regular sequence) */
\r
1349 #define ADC_SQR1_SQ13_0 ((uint32_t)0x00000001) /*!<Bit 0 */
\r
1350 #define ADC_SQR1_SQ13_1 ((uint32_t)0x00000002) /*!<Bit 1 */
\r
1351 #define ADC_SQR1_SQ13_2 ((uint32_t)0x00000004) /*!<Bit 2 */
\r
1352 #define ADC_SQR1_SQ13_3 ((uint32_t)0x00000008) /*!<Bit 3 */
\r
1353 #define ADC_SQR1_SQ13_4 ((uint32_t)0x00000010) /*!<Bit 4 */
\r
1354 #define ADC_SQR1_SQ14 ((uint32_t)0x000003E0) /*!<SQ14[4:0] bits (14th conversion in regular sequence) */
\r
1355 #define ADC_SQR1_SQ14_0 ((uint32_t)0x00000020) /*!<Bit 0 */
\r
1356 #define ADC_SQR1_SQ14_1 ((uint32_t)0x00000040) /*!<Bit 1 */
\r
1357 #define ADC_SQR1_SQ14_2 ((uint32_t)0x00000080) /*!<Bit 2 */
\r
1358 #define ADC_SQR1_SQ14_3 ((uint32_t)0x00000100) /*!<Bit 3 */
\r
1359 #define ADC_SQR1_SQ14_4 ((uint32_t)0x00000200) /*!<Bit 4 */
\r
1360 #define ADC_SQR1_SQ15 ((uint32_t)0x00007C00) /*!<SQ15[4:0] bits (15th conversion in regular sequence) */
\r
1361 #define ADC_SQR1_SQ15_0 ((uint32_t)0x00000400) /*!<Bit 0 */
\r
1362 #define ADC_SQR1_SQ15_1 ((uint32_t)0x00000800) /*!<Bit 1 */
\r
1363 #define ADC_SQR1_SQ15_2 ((uint32_t)0x00001000) /*!<Bit 2 */
\r
1364 #define ADC_SQR1_SQ15_3 ((uint32_t)0x00002000) /*!<Bit 3 */
\r
1365 #define ADC_SQR1_SQ15_4 ((uint32_t)0x00004000) /*!<Bit 4 */
\r
1366 #define ADC_SQR1_SQ16 ((uint32_t)0x000F8000) /*!<SQ16[4:0] bits (16th conversion in regular sequence) */
\r
1367 #define ADC_SQR1_SQ16_0 ((uint32_t)0x00008000) /*!<Bit 0 */
\r
1368 #define ADC_SQR1_SQ16_1 ((uint32_t)0x00010000) /*!<Bit 1 */
\r
1369 #define ADC_SQR1_SQ16_2 ((uint32_t)0x00020000) /*!<Bit 2 */
\r
1370 #define ADC_SQR1_SQ16_3 ((uint32_t)0x00040000) /*!<Bit 3 */
\r
1371 #define ADC_SQR1_SQ16_4 ((uint32_t)0x00080000) /*!<Bit 4 */
\r
1372 #define ADC_SQR1_L ((uint32_t)0x00F00000) /*!<L[3:0] bits (Regular channel sequence length) */
\r
1373 #define ADC_SQR1_L_0 ((uint32_t)0x00100000) /*!<Bit 0 */
\r
1374 #define ADC_SQR1_L_1 ((uint32_t)0x00200000) /*!<Bit 1 */
\r
1375 #define ADC_SQR1_L_2 ((uint32_t)0x00400000) /*!<Bit 2 */
\r
1376 #define ADC_SQR1_L_3 ((uint32_t)0x00800000) /*!<Bit 3 */
\r
1378 /******************* Bit definition for ADC_SQR2 register *******************/
\r
1379 #define ADC_SQR2_SQ7 ((uint32_t)0x0000001F) /*!<SQ7[4:0] bits (7th conversion in regular sequence) */
\r
1380 #define ADC_SQR2_SQ7_0 ((uint32_t)0x00000001) /*!<Bit 0 */
\r
1381 #define ADC_SQR2_SQ7_1 ((uint32_t)0x00000002) /*!<Bit 1 */
\r
1382 #define ADC_SQR2_SQ7_2 ((uint32_t)0x00000004) /*!<Bit 2 */
\r
1383 #define ADC_SQR2_SQ7_3 ((uint32_t)0x00000008) /*!<Bit 3 */
\r
1384 #define ADC_SQR2_SQ7_4 ((uint32_t)0x00000010) /*!<Bit 4 */
\r
1385 #define ADC_SQR2_SQ8 ((uint32_t)0x000003E0) /*!<SQ8[4:0] bits (8th conversion in regular sequence) */
\r
1386 #define ADC_SQR2_SQ8_0 ((uint32_t)0x00000020) /*!<Bit 0 */
\r
1387 #define ADC_SQR2_SQ8_1 ((uint32_t)0x00000040) /*!<Bit 1 */
\r
1388 #define ADC_SQR2_SQ8_2 ((uint32_t)0x00000080) /*!<Bit 2 */
\r
1389 #define ADC_SQR2_SQ8_3 ((uint32_t)0x00000100) /*!<Bit 3 */
\r
1390 #define ADC_SQR2_SQ8_4 ((uint32_t)0x00000200) /*!<Bit 4 */
\r
1391 #define ADC_SQR2_SQ9 ((uint32_t)0x00007C00) /*!<SQ9[4:0] bits (9th conversion in regular sequence) */
\r
1392 #define ADC_SQR2_SQ9_0 ((uint32_t)0x00000400) /*!<Bit 0 */
\r
1393 #define ADC_SQR2_SQ9_1 ((uint32_t)0x00000800) /*!<Bit 1 */
\r
1394 #define ADC_SQR2_SQ9_2 ((uint32_t)0x00001000) /*!<Bit 2 */
\r
1395 #define ADC_SQR2_SQ9_3 ((uint32_t)0x00002000) /*!<Bit 3 */
\r
1396 #define ADC_SQR2_SQ9_4 ((uint32_t)0x00004000) /*!<Bit 4 */
\r
1397 #define ADC_SQR2_SQ10 ((uint32_t)0x000F8000) /*!<SQ10[4:0] bits (10th conversion in regular sequence) */
\r
1398 #define ADC_SQR2_SQ10_0 ((uint32_t)0x00008000) /*!<Bit 0 */
\r
1399 #define ADC_SQR2_SQ10_1 ((uint32_t)0x00010000) /*!<Bit 1 */
\r
1400 #define ADC_SQR2_SQ10_2 ((uint32_t)0x00020000) /*!<Bit 2 */
\r
1401 #define ADC_SQR2_SQ10_3 ((uint32_t)0x00040000) /*!<Bit 3 */
\r
1402 #define ADC_SQR2_SQ10_4 ((uint32_t)0x00080000) /*!<Bit 4 */
\r
1403 #define ADC_SQR2_SQ11 ((uint32_t)0x01F00000) /*!<SQ11[4:0] bits (11th conversion in regular sequence) */
\r
1404 #define ADC_SQR2_SQ11_0 ((uint32_t)0x00100000) /*!<Bit 0 */
\r
1405 #define ADC_SQR2_SQ11_1 ((uint32_t)0x00200000) /*!<Bit 1 */
\r
1406 #define ADC_SQR2_SQ11_2 ((uint32_t)0x00400000) /*!<Bit 2 */
\r
1407 #define ADC_SQR2_SQ11_3 ((uint32_t)0x00800000) /*!<Bit 3 */
\r
1408 #define ADC_SQR2_SQ11_4 ((uint32_t)0x01000000) /*!<Bit 4 */
\r
1409 #define ADC_SQR2_SQ12 ((uint32_t)0x3E000000) /*!<SQ12[4:0] bits (12th conversion in regular sequence) */
\r
1410 #define ADC_SQR2_SQ12_0 ((uint32_t)0x02000000) /*!<Bit 0 */
\r
1411 #define ADC_SQR2_SQ12_1 ((uint32_t)0x04000000) /*!<Bit 1 */
\r
1412 #define ADC_SQR2_SQ12_2 ((uint32_t)0x08000000) /*!<Bit 2 */
\r
1413 #define ADC_SQR2_SQ12_3 ((uint32_t)0x10000000) /*!<Bit 3 */
\r
1414 #define ADC_SQR2_SQ12_4 ((uint32_t)0x20000000) /*!<Bit 4 */
\r
1416 /******************* Bit definition for ADC_SQR3 register *******************/
\r
1417 #define ADC_SQR3_SQ1 ((uint32_t)0x0000001F) /*!<SQ1[4:0] bits (1st conversion in regular sequence) */
\r
1418 #define ADC_SQR3_SQ1_0 ((uint32_t)0x00000001) /*!<Bit 0 */
\r
1419 #define ADC_SQR3_SQ1_1 ((uint32_t)0x00000002) /*!<Bit 1 */
\r
1420 #define ADC_SQR3_SQ1_2 ((uint32_t)0x00000004) /*!<Bit 2 */
\r
1421 #define ADC_SQR3_SQ1_3 ((uint32_t)0x00000008) /*!<Bit 3 */
\r
1422 #define ADC_SQR3_SQ1_4 ((uint32_t)0x00000010) /*!<Bit 4 */
\r
1423 #define ADC_SQR3_SQ2 ((uint32_t)0x000003E0) /*!<SQ2[4:0] bits (2nd conversion in regular sequence) */
\r
1424 #define ADC_SQR3_SQ2_0 ((uint32_t)0x00000020) /*!<Bit 0 */
\r
1425 #define ADC_SQR3_SQ2_1 ((uint32_t)0x00000040) /*!<Bit 1 */
\r
1426 #define ADC_SQR3_SQ2_2 ((uint32_t)0x00000080) /*!<Bit 2 */
\r
1427 #define ADC_SQR3_SQ2_3 ((uint32_t)0x00000100) /*!<Bit 3 */
\r
1428 #define ADC_SQR3_SQ2_4 ((uint32_t)0x00000200) /*!<Bit 4 */
\r
1429 #define ADC_SQR3_SQ3 ((uint32_t)0x00007C00) /*!<SQ3[4:0] bits (3rd conversion in regular sequence) */
\r
1430 #define ADC_SQR3_SQ3_0 ((uint32_t)0x00000400) /*!<Bit 0 */
\r
1431 #define ADC_SQR3_SQ3_1 ((uint32_t)0x00000800) /*!<Bit 1 */
\r
1432 #define ADC_SQR3_SQ3_2 ((uint32_t)0x00001000) /*!<Bit 2 */
\r
1433 #define ADC_SQR3_SQ3_3 ((uint32_t)0x00002000) /*!<Bit 3 */
\r
1434 #define ADC_SQR3_SQ3_4 ((uint32_t)0x00004000) /*!<Bit 4 */
\r
1435 #define ADC_SQR3_SQ4 ((uint32_t)0x000F8000) /*!<SQ4[4:0] bits (4th conversion in regular sequence) */
\r
1436 #define ADC_SQR3_SQ4_0 ((uint32_t)0x00008000) /*!<Bit 0 */
\r
1437 #define ADC_SQR3_SQ4_1 ((uint32_t)0x00010000) /*!<Bit 1 */
\r
1438 #define ADC_SQR3_SQ4_2 ((uint32_t)0x00020000) /*!<Bit 2 */
\r
1439 #define ADC_SQR3_SQ4_3 ((uint32_t)0x00040000) /*!<Bit 3 */
\r
1440 #define ADC_SQR3_SQ4_4 ((uint32_t)0x00080000) /*!<Bit 4 */
\r
1441 #define ADC_SQR3_SQ5 ((uint32_t)0x01F00000) /*!<SQ5[4:0] bits (5th conversion in regular sequence) */
\r
1442 #define ADC_SQR3_SQ5_0 ((uint32_t)0x00100000) /*!<Bit 0 */
\r
1443 #define ADC_SQR3_SQ5_1 ((uint32_t)0x00200000) /*!<Bit 1 */
\r
1444 #define ADC_SQR3_SQ5_2 ((uint32_t)0x00400000) /*!<Bit 2 */
\r
1445 #define ADC_SQR3_SQ5_3 ((uint32_t)0x00800000) /*!<Bit 3 */
\r
1446 #define ADC_SQR3_SQ5_4 ((uint32_t)0x01000000) /*!<Bit 4 */
\r
1447 #define ADC_SQR3_SQ6 ((uint32_t)0x3E000000) /*!<SQ6[4:0] bits (6th conversion in regular sequence) */
\r
1448 #define ADC_SQR3_SQ6_0 ((uint32_t)0x02000000) /*!<Bit 0 */
\r
1449 #define ADC_SQR3_SQ6_1 ((uint32_t)0x04000000) /*!<Bit 1 */
\r
1450 #define ADC_SQR3_SQ6_2 ((uint32_t)0x08000000) /*!<Bit 2 */
\r
1451 #define ADC_SQR3_SQ6_3 ((uint32_t)0x10000000) /*!<Bit 3 */
\r
1452 #define ADC_SQR3_SQ6_4 ((uint32_t)0x20000000) /*!<Bit 4 */
\r
1454 /******************* Bit definition for ADC_JSQR register *******************/
\r
1455 #define ADC_JSQR_JSQ1 ((uint32_t)0x0000001F) /*!<JSQ1[4:0] bits (1st conversion in injected sequence) */
\r
1456 #define ADC_JSQR_JSQ1_0 ((uint32_t)0x00000001) /*!<Bit 0 */
\r
1457 #define ADC_JSQR_JSQ1_1 ((uint32_t)0x00000002) /*!<Bit 1 */
\r
1458 #define ADC_JSQR_JSQ1_2 ((uint32_t)0x00000004) /*!<Bit 2 */
\r
1459 #define ADC_JSQR_JSQ1_3 ((uint32_t)0x00000008) /*!<Bit 3 */
\r
1460 #define ADC_JSQR_JSQ1_4 ((uint32_t)0x00000010) /*!<Bit 4 */
\r
1461 #define ADC_JSQR_JSQ2 ((uint32_t)0x000003E0) /*!<JSQ2[4:0] bits (2nd conversion in injected sequence) */
\r
1462 #define ADC_JSQR_JSQ2_0 ((uint32_t)0x00000020) /*!<Bit 0 */
\r
1463 #define ADC_JSQR_JSQ2_1 ((uint32_t)0x00000040) /*!<Bit 1 */
\r
1464 #define ADC_JSQR_JSQ2_2 ((uint32_t)0x00000080) /*!<Bit 2 */
\r
1465 #define ADC_JSQR_JSQ2_3 ((uint32_t)0x00000100) /*!<Bit 3 */
\r
1466 #define ADC_JSQR_JSQ2_4 ((uint32_t)0x00000200) /*!<Bit 4 */
\r
1467 #define ADC_JSQR_JSQ3 ((uint32_t)0x00007C00) /*!<JSQ3[4:0] bits (3rd conversion in injected sequence) */
\r
1468 #define ADC_JSQR_JSQ3_0 ((uint32_t)0x00000400) /*!<Bit 0 */
\r
1469 #define ADC_JSQR_JSQ3_1 ((uint32_t)0x00000800) /*!<Bit 1 */
\r
1470 #define ADC_JSQR_JSQ3_2 ((uint32_t)0x00001000) /*!<Bit 2 */
\r
1471 #define ADC_JSQR_JSQ3_3 ((uint32_t)0x00002000) /*!<Bit 3 */
\r
1472 #define ADC_JSQR_JSQ3_4 ((uint32_t)0x00004000) /*!<Bit 4 */
\r
1473 #define ADC_JSQR_JSQ4 ((uint32_t)0x000F8000) /*!<JSQ4[4:0] bits (4th conversion in injected sequence) */
\r
1474 #define ADC_JSQR_JSQ4_0 ((uint32_t)0x00008000) /*!<Bit 0 */
\r
1475 #define ADC_JSQR_JSQ4_1 ((uint32_t)0x00010000) /*!<Bit 1 */
\r
1476 #define ADC_JSQR_JSQ4_2 ((uint32_t)0x00020000) /*!<Bit 2 */
\r
1477 #define ADC_JSQR_JSQ4_3 ((uint32_t)0x00040000) /*!<Bit 3 */
\r
1478 #define ADC_JSQR_JSQ4_4 ((uint32_t)0x00080000) /*!<Bit 4 */
\r
1479 #define ADC_JSQR_JL ((uint32_t)0x00300000) /*!<JL[1:0] bits (Injected Sequence length) */
\r
1480 #define ADC_JSQR_JL_0 ((uint32_t)0x00100000) /*!<Bit 0 */
\r
1481 #define ADC_JSQR_JL_1 ((uint32_t)0x00200000) /*!<Bit 1 */
\r
1483 /******************* Bit definition for ADC_JDR1 register *******************/
\r
1484 #define ADC_JDR1_JDATA ((uint32_t)0xFFFF) /*!<Injected data */
\r
1486 /******************* Bit definition for ADC_JDR2 register *******************/
\r
1487 #define ADC_JDR2_JDATA ((uint32_t)0xFFFF) /*!<Injected data */
\r
1489 /******************* Bit definition for ADC_JDR3 register *******************/
\r
1490 #define ADC_JDR3_JDATA ((uint32_t)0xFFFF) /*!<Injected data */
\r
1492 /******************* Bit definition for ADC_JDR4 register *******************/
\r
1493 #define ADC_JDR4_JDATA ((uint32_t)0xFFFF) /*!<Injected data */
\r
1495 /******************** Bit definition for ADC_DR register ********************/
\r
1496 #define ADC_DR_DATA ((uint32_t)0x0000FFFF) /*!<Regular data */
\r
1497 #define ADC_DR_ADC2DATA ((uint32_t)0xFFFF0000) /*!<ADC2 data */
\r
1499 /******************* Bit definition for ADC_CSR register ********************/
\r
1500 #define ADC_CSR_AWD1 ((uint32_t)0x00000001) /*!<ADC1 Analog watchdog flag */
\r
1501 #define ADC_CSR_EOC1 ((uint32_t)0x00000002) /*!<ADC1 End of conversion */
\r
1502 #define ADC_CSR_JEOC1 ((uint32_t)0x00000004) /*!<ADC1 Injected channel end of conversion */
\r
1503 #define ADC_CSR_JSTRT1 ((uint32_t)0x00000008) /*!<ADC1 Injected channel Start flag */
\r
1504 #define ADC_CSR_STRT1 ((uint32_t)0x00000010) /*!<ADC1 Regular channel Start flag */
\r
1505 #define ADC_CSR_DOVR1 ((uint32_t)0x00000020) /*!<ADC1 DMA overrun flag */
\r
1506 #define ADC_CSR_AWD2 ((uint32_t)0x00000100) /*!<ADC2 Analog watchdog flag */
\r
1507 #define ADC_CSR_EOC2 ((uint32_t)0x00000200) /*!<ADC2 End of conversion */
\r
1508 #define ADC_CSR_JEOC2 ((uint32_t)0x00000400) /*!<ADC2 Injected channel end of conversion */
\r
1509 #define ADC_CSR_JSTRT2 ((uint32_t)0x00000800) /*!<ADC2 Injected channel Start flag */
\r
1510 #define ADC_CSR_STRT2 ((uint32_t)0x00001000) /*!<ADC2 Regular channel Start flag */
\r
1511 #define ADC_CSR_DOVR2 ((uint32_t)0x00002000) /*!<ADC2 DMA overrun flag */
\r
1512 #define ADC_CSR_AWD3 ((uint32_t)0x00010000) /*!<ADC3 Analog watchdog flag */
\r
1513 #define ADC_CSR_EOC3 ((uint32_t)0x00020000) /*!<ADC3 End of conversion */
\r
1514 #define ADC_CSR_JEOC3 ((uint32_t)0x00040000) /*!<ADC3 Injected channel end of conversion */
\r
1515 #define ADC_CSR_JSTRT3 ((uint32_t)0x00080000) /*!<ADC3 Injected channel Start flag */
\r
1516 #define ADC_CSR_STRT3 ((uint32_t)0x00100000) /*!<ADC3 Regular channel Start flag */
\r
1517 #define ADC_CSR_DOVR3 ((uint32_t)0x00200000) /*!<ADC3 DMA overrun flag */
\r
1519 /******************* Bit definition for ADC_CCR register ********************/
\r
1520 #define ADC_CCR_MULTI ((uint32_t)0x0000001F) /*!<MULTI[4:0] bits (Multi-ADC mode selection) */
\r
1521 #define ADC_CCR_MULTI_0 ((uint32_t)0x00000001) /*!<Bit 0 */
\r
1522 #define ADC_CCR_MULTI_1 ((uint32_t)0x00000002) /*!<Bit 1 */
\r
1523 #define ADC_CCR_MULTI_2 ((uint32_t)0x00000004) /*!<Bit 2 */
\r
1524 #define ADC_CCR_MULTI_3 ((uint32_t)0x00000008) /*!<Bit 3 */
\r
1525 #define ADC_CCR_MULTI_4 ((uint32_t)0x00000010) /*!<Bit 4 */
\r
1526 #define ADC_CCR_DELAY ((uint32_t)0x00000F00) /*!<DELAY[3:0] bits (Delay between 2 sampling phases) */
\r
1527 #define ADC_CCR_DELAY_0 ((uint32_t)0x00000100) /*!<Bit 0 */
\r
1528 #define ADC_CCR_DELAY_1 ((uint32_t)0x00000200) /*!<Bit 1 */
\r
1529 #define ADC_CCR_DELAY_2 ((uint32_t)0x00000400) /*!<Bit 2 */
\r
1530 #define ADC_CCR_DELAY_3 ((uint32_t)0x00000800) /*!<Bit 3 */
\r
1531 #define ADC_CCR_DDS ((uint32_t)0x00002000) /*!<DMA disable selection (Multi-ADC mode) */
\r
1532 #define ADC_CCR_DMA ((uint32_t)0x0000C000) /*!<DMA[1:0] bits (Direct Memory Access mode for multimode) */
\r
1533 #define ADC_CCR_DMA_0 ((uint32_t)0x00004000) /*!<Bit 0 */
\r
1534 #define ADC_CCR_DMA_1 ((uint32_t)0x00008000) /*!<Bit 1 */
\r
1535 #define ADC_CCR_ADCPRE ((uint32_t)0x00030000) /*!<ADCPRE[1:0] bits (ADC prescaler) */
\r
1536 #define ADC_CCR_ADCPRE_0 ((uint32_t)0x00010000) /*!<Bit 0 */
\r
1537 #define ADC_CCR_ADCPRE_1 ((uint32_t)0x00020000) /*!<Bit 1 */
\r
1538 #define ADC_CCR_VBATE ((uint32_t)0x00400000) /*!<VBAT Enable */
\r
1539 #define ADC_CCR_TSVREFE ((uint32_t)0x00800000) /*!<Temperature Sensor and VREFINT Enable */
\r
1541 /******************* Bit definition for ADC_CDR register ********************/
\r
1542 #define ADC_CDR_DATA1 ((uint32_t)0x0000FFFF) /*!<1st data of a pair of regular conversions */
\r
1543 #define ADC_CDR_DATA2 ((uint32_t)0xFFFF0000) /*!<2nd data of a pair of regular conversions */
\r
1545 /******************************************************************************/
\r
1547 /* Controller Area Network */
\r
1549 /******************************************************************************/
\r
1550 /*!<CAN control and status registers */
\r
1551 /******************* Bit definition for CAN_MCR register ********************/
\r
1552 #define CAN_MCR_INRQ ((uint32_t)0x00000001) /*!<Initialization Request */
\r
1553 #define CAN_MCR_SLEEP ((uint32_t)0x00000002) /*!<Sleep Mode Request */
\r
1554 #define CAN_MCR_TXFP ((uint32_t)0x00000004) /*!<Transmit FIFO Priority */
\r
1555 #define CAN_MCR_RFLM ((uint32_t)0x00000008) /*!<Receive FIFO Locked Mode */
\r
1556 #define CAN_MCR_NART ((uint32_t)0x00000010) /*!<No Automatic Retransmission */
\r
1557 #define CAN_MCR_AWUM ((uint32_t)0x00000020) /*!<Automatic Wakeup Mode */
\r
1558 #define CAN_MCR_ABOM ((uint32_t)0x00000040) /*!<Automatic Bus-Off Management */
\r
1559 #define CAN_MCR_TTCM ((uint32_t)0x00000080) /*!<Time Triggered Communication Mode */
\r
1560 #define CAN_MCR_RESET ((uint32_t)0x00008000) /*!<bxCAN software master reset */
\r
1561 #define CAN_MCR_DBF ((uint32_t)0x00010000) /*!<bxCAN Debug freeze */
\r
1562 /******************* Bit definition for CAN_MSR register ********************/
\r
1563 #define CAN_MSR_INAK ((uint32_t)0x0001) /*!<Initialization Acknowledge */
\r
1564 #define CAN_MSR_SLAK ((uint32_t)0x0002) /*!<Sleep Acknowledge */
\r
1565 #define CAN_MSR_ERRI ((uint32_t)0x0004) /*!<Error Interrupt */
\r
1566 #define CAN_MSR_WKUI ((uint32_t)0x0008) /*!<Wakeup Interrupt */
\r
1567 #define CAN_MSR_SLAKI ((uint32_t)0x0010) /*!<Sleep Acknowledge Interrupt */
\r
1568 #define CAN_MSR_TXM ((uint32_t)0x0100) /*!<Transmit Mode */
\r
1569 #define CAN_MSR_RXM ((uint32_t)0x0200) /*!<Receive Mode */
\r
1570 #define CAN_MSR_SAMP ((uint32_t)0x0400) /*!<Last Sample Point */
\r
1571 #define CAN_MSR_RX ((uint32_t)0x0800) /*!<CAN Rx Signal */
\r
1573 /******************* Bit definition for CAN_TSR register ********************/
\r
1574 #define CAN_TSR_RQCP0 ((uint32_t)0x00000001) /*!<Request Completed Mailbox0 */
\r
1575 #define CAN_TSR_TXOK0 ((uint32_t)0x00000002) /*!<Transmission OK of Mailbox0 */
\r
1576 #define CAN_TSR_ALST0 ((uint32_t)0x00000004) /*!<Arbitration Lost for Mailbox0 */
\r
1577 #define CAN_TSR_TERR0 ((uint32_t)0x00000008) /*!<Transmission Error of Mailbox0 */
\r
1578 #define CAN_TSR_ABRQ0 ((uint32_t)0x00000080) /*!<Abort Request for Mailbox0 */
\r
1579 #define CAN_TSR_RQCP1 ((uint32_t)0x00000100) /*!<Request Completed Mailbox1 */
\r
1580 #define CAN_TSR_TXOK1 ((uint32_t)0x00000200) /*!<Transmission OK of Mailbox1 */
\r
1581 #define CAN_TSR_ALST1 ((uint32_t)0x00000400) /*!<Arbitration Lost for Mailbox1 */
\r
1582 #define CAN_TSR_TERR1 ((uint32_t)0x00000800) /*!<Transmission Error of Mailbox1 */
\r
1583 #define CAN_TSR_ABRQ1 ((uint32_t)0x00008000) /*!<Abort Request for Mailbox 1 */
\r
1584 #define CAN_TSR_RQCP2 ((uint32_t)0x00010000) /*!<Request Completed Mailbox2 */
\r
1585 #define CAN_TSR_TXOK2 ((uint32_t)0x00020000) /*!<Transmission OK of Mailbox 2 */
\r
1586 #define CAN_TSR_ALST2 ((uint32_t)0x00040000) /*!<Arbitration Lost for mailbox 2 */
\r
1587 #define CAN_TSR_TERR2 ((uint32_t)0x00080000) /*!<Transmission Error of Mailbox 2 */
\r
1588 #define CAN_TSR_ABRQ2 ((uint32_t)0x00800000) /*!<Abort Request for Mailbox 2 */
\r
1589 #define CAN_TSR_CODE ((uint32_t)0x03000000) /*!<Mailbox Code */
\r
1591 #define CAN_TSR_TME ((uint32_t)0x1C000000) /*!<TME[2:0] bits */
\r
1592 #define CAN_TSR_TME0 ((uint32_t)0x04000000) /*!<Transmit Mailbox 0 Empty */
\r
1593 #define CAN_TSR_TME1 ((uint32_t)0x08000000) /*!<Transmit Mailbox 1 Empty */
\r
1594 #define CAN_TSR_TME2 ((uint32_t)0x10000000) /*!<Transmit Mailbox 2 Empty */
\r
1596 #define CAN_TSR_LOW ((uint32_t)0xE0000000) /*!<LOW[2:0] bits */
\r
1597 #define CAN_TSR_LOW0 ((uint32_t)0x20000000) /*!<Lowest Priority Flag for Mailbox 0 */
\r
1598 #define CAN_TSR_LOW1 ((uint32_t)0x40000000) /*!<Lowest Priority Flag for Mailbox 1 */
\r
1599 #define CAN_TSR_LOW2 ((uint32_t)0x80000000) /*!<Lowest Priority Flag for Mailbox 2 */
\r
1601 /******************* Bit definition for CAN_RF0R register *******************/
\r
1602 #define CAN_RF0R_FMP0 ((uint32_t)0x03) /*!<FIFO 0 Message Pending */
\r
1603 #define CAN_RF0R_FULL0 ((uint32_t)0x08) /*!<FIFO 0 Full */
\r
1604 #define CAN_RF0R_FOVR0 ((uint32_t)0x10) /*!<FIFO 0 Overrun */
\r
1605 #define CAN_RF0R_RFOM0 ((uint32_t)0x20) /*!<Release FIFO 0 Output Mailbox */
\r
1607 /******************* Bit definition for CAN_RF1R register *******************/
\r
1608 #define CAN_RF1R_FMP1 ((uint32_t)0x03) /*!<FIFO 1 Message Pending */
\r
1609 #define CAN_RF1R_FULL1 ((uint32_t)0x08) /*!<FIFO 1 Full */
\r
1610 #define CAN_RF1R_FOVR1 ((uint32_t)0x10) /*!<FIFO 1 Overrun */
\r
1611 #define CAN_RF1R_RFOM1 ((uint32_t)0x20) /*!<Release FIFO 1 Output Mailbox */
\r
1613 /******************** Bit definition for CAN_IER register *******************/
\r
1614 #define CAN_IER_TMEIE ((uint32_t)0x00000001) /*!<Transmit Mailbox Empty Interrupt Enable */
\r
1615 #define CAN_IER_FMPIE0 ((uint32_t)0x00000002) /*!<FIFO Message Pending Interrupt Enable */
\r
1616 #define CAN_IER_FFIE0 ((uint32_t)0x00000004) /*!<FIFO Full Interrupt Enable */
\r
1617 #define CAN_IER_FOVIE0 ((uint32_t)0x00000008) /*!<FIFO Overrun Interrupt Enable */
\r
1618 #define CAN_IER_FMPIE1 ((uint32_t)0x00000010) /*!<FIFO Message Pending Interrupt Enable */
\r
1619 #define CAN_IER_FFIE1 ((uint32_t)0x00000020) /*!<FIFO Full Interrupt Enable */
\r
1620 #define CAN_IER_FOVIE1 ((uint32_t)0x00000040) /*!<FIFO Overrun Interrupt Enable */
\r
1621 #define CAN_IER_EWGIE ((uint32_t)0x00000100) /*!<Error Warning Interrupt Enable */
\r
1622 #define CAN_IER_EPVIE ((uint32_t)0x00000200) /*!<Error Passive Interrupt Enable */
\r
1623 #define CAN_IER_BOFIE ((uint32_t)0x00000400) /*!<Bus-Off Interrupt Enable */
\r
1624 #define CAN_IER_LECIE ((uint32_t)0x00000800) /*!<Last Error Code Interrupt Enable */
\r
1625 #define CAN_IER_ERRIE ((uint32_t)0x00008000) /*!<Error Interrupt Enable */
\r
1626 #define CAN_IER_WKUIE ((uint32_t)0x00010000) /*!<Wakeup Interrupt Enable */
\r
1627 #define CAN_IER_SLKIE ((uint32_t)0x00020000) /*!<Sleep Interrupt Enable */
\r
1628 #define CAN_IER_EWGIE ((uint32_t)0x00000100) /*!<Error warning interrupt enable */
\r
1629 #define CAN_IER_EPVIE ((uint32_t)0x00000200) /*!<Error passive interrupt enable */
\r
1630 #define CAN_IER_BOFIE ((uint32_t)0x00000400) /*!<Bus-off interrupt enable */
\r
1631 #define CAN_IER_LECIE ((uint32_t)0x00000800) /*!<Last error code interrupt enable */
\r
1632 #define CAN_IER_ERRIE ((uint32_t)0x00008000) /*!<Error interrupt enable */
\r
1635 /******************** Bit definition for CAN_ESR register *******************/
\r
1636 #define CAN_ESR_EWGF ((uint32_t)0x00000001) /*!<Error Warning Flag */
\r
1637 #define CAN_ESR_EPVF ((uint32_t)0x00000002) /*!<Error Passive Flag */
\r
1638 #define CAN_ESR_BOFF ((uint32_t)0x00000004) /*!<Bus-Off Flag */
\r
1640 #define CAN_ESR_LEC ((uint32_t)0x00000070) /*!<LEC[2:0] bits (Last Error Code) */
\r
1641 #define CAN_ESR_LEC_0 ((uint32_t)0x00000010) /*!<Bit 0 */
\r
1642 #define CAN_ESR_LEC_1 ((uint32_t)0x00000020) /*!<Bit 1 */
\r
1643 #define CAN_ESR_LEC_2 ((uint32_t)0x00000040) /*!<Bit 2 */
\r
1645 #define CAN_ESR_TEC ((uint32_t)0x00FF0000) /*!<Least significant byte of the 9-bit Transmit Error Counter */
\r
1646 #define CAN_ESR_REC ((uint32_t)0xFF000000) /*!<Receive Error Counter */
\r
1648 /******************* Bit definition for CAN_BTR register ********************/
\r
1649 #define CAN_BTR_BRP ((uint32_t)0x000003FF) /*!<Baud Rate Prescaler */
\r
1650 #define CAN_BTR_TS1 ((uint32_t)0x000F0000) /*!<Time Segment 1 */
\r
1651 #define CAN_BTR_TS1_0 ((uint32_t)0x00010000) /*!<Bit 0 */
\r
1652 #define CAN_BTR_TS1_1 ((uint32_t)0x00020000) /*!<Bit 1 */
\r
1653 #define CAN_BTR_TS1_2 ((uint32_t)0x00040000) /*!<Bit 2 */
\r
1654 #define CAN_BTR_TS1_3 ((uint32_t)0x00080000) /*!<Bit 3 */
\r
1655 #define CAN_BTR_TS2 ((uint32_t)0x00700000) /*!<Time Segment 2 */
\r
1656 #define CAN_BTR_TS2_0 ((uint32_t)0x00100000) /*!<Bit 0 */
\r
1657 #define CAN_BTR_TS2_1 ((uint32_t)0x00200000) /*!<Bit 1 */
\r
1658 #define CAN_BTR_TS2_2 ((uint32_t)0x00400000) /*!<Bit 2 */
\r
1659 #define CAN_BTR_SJW ((uint32_t)0x03000000) /*!<Resynchronization Jump Width */
\r
1660 #define CAN_BTR_SJW_0 ((uint32_t)0x01000000) /*!<Bit 0 */
\r
1661 #define CAN_BTR_SJW_1 ((uint32_t)0x02000000) /*!<Bit 1 */
\r
1662 #define CAN_BTR_LBKM ((uint32_t)0x40000000) /*!<Loop Back Mode (Debug) */
\r
1663 #define CAN_BTR_SILM ((uint32_t)0x80000000) /*!<Silent Mode */
\r
1666 /*!<Mailbox registers */
\r
1667 /****************** Bit definition for CAN_TI0R register ********************/
\r
1668 #define CAN_TI0R_TXRQ ((uint32_t)0x00000001) /*!<Transmit Mailbox Request */
\r
1669 #define CAN_TI0R_RTR ((uint32_t)0x00000002) /*!<Remote Transmission Request */
\r
1670 #define CAN_TI0R_IDE ((uint32_t)0x00000004) /*!<Identifier Extension */
\r
1671 #define CAN_TI0R_EXID ((uint32_t)0x001FFFF8) /*!<Extended Identifier */
\r
1672 #define CAN_TI0R_STID ((uint32_t)0xFFE00000) /*!<Standard Identifier or Extended Identifier */
\r
1674 /****************** Bit definition for CAN_TDT0R register *******************/
\r
1675 #define CAN_TDT0R_DLC ((uint32_t)0x0000000F) /*!<Data Length Code */
\r
1676 #define CAN_TDT0R_TGT ((uint32_t)0x00000100) /*!<Transmit Global Time */
\r
1677 #define CAN_TDT0R_TIME ((uint32_t)0xFFFF0000) /*!<Message Time Stamp */
\r
1679 /****************** Bit definition for CAN_TDL0R register *******************/
\r
1680 #define CAN_TDL0R_DATA0 ((uint32_t)0x000000FF) /*!<Data byte 0 */
\r
1681 #define CAN_TDL0R_DATA1 ((uint32_t)0x0000FF00) /*!<Data byte 1 */
\r
1682 #define CAN_TDL0R_DATA2 ((uint32_t)0x00FF0000) /*!<Data byte 2 */
\r
1683 #define CAN_TDL0R_DATA3 ((uint32_t)0xFF000000) /*!<Data byte 3 */
\r
1685 /****************** Bit definition for CAN_TDH0R register *******************/
\r
1686 #define CAN_TDH0R_DATA4 ((uint32_t)0x000000FF) /*!<Data byte 4 */
\r
1687 #define CAN_TDH0R_DATA5 ((uint32_t)0x0000FF00) /*!<Data byte 5 */
\r
1688 #define CAN_TDH0R_DATA6 ((uint32_t)0x00FF0000) /*!<Data byte 6 */
\r
1689 #define CAN_TDH0R_DATA7 ((uint32_t)0xFF000000) /*!<Data byte 7 */
\r
1691 /******************* Bit definition for CAN_TI1R register *******************/
\r
1692 #define CAN_TI1R_TXRQ ((uint32_t)0x00000001) /*!<Transmit Mailbox Request */
\r
1693 #define CAN_TI1R_RTR ((uint32_t)0x00000002) /*!<Remote Transmission Request */
\r
1694 #define CAN_TI1R_IDE ((uint32_t)0x00000004) /*!<Identifier Extension */
\r
1695 #define CAN_TI1R_EXID ((uint32_t)0x001FFFF8) /*!<Extended Identifier */
\r
1696 #define CAN_TI1R_STID ((uint32_t)0xFFE00000) /*!<Standard Identifier or Extended Identifier */
\r
1698 /******************* Bit definition for CAN_TDT1R register ******************/
\r
1699 #define CAN_TDT1R_DLC ((uint32_t)0x0000000F) /*!<Data Length Code */
\r
1700 #define CAN_TDT1R_TGT ((uint32_t)0x00000100) /*!<Transmit Global Time */
\r
1701 #define CAN_TDT1R_TIME ((uint32_t)0xFFFF0000) /*!<Message Time Stamp */
\r
1703 /******************* Bit definition for CAN_TDL1R register ******************/
\r
1704 #define CAN_TDL1R_DATA0 ((uint32_t)0x000000FF) /*!<Data byte 0 */
\r
1705 #define CAN_TDL1R_DATA1 ((uint32_t)0x0000FF00) /*!<Data byte 1 */
\r
1706 #define CAN_TDL1R_DATA2 ((uint32_t)0x00FF0000) /*!<Data byte 2 */
\r
1707 #define CAN_TDL1R_DATA3 ((uint32_t)0xFF000000) /*!<Data byte 3 */
\r
1709 /******************* Bit definition for CAN_TDH1R register ******************/
\r
1710 #define CAN_TDH1R_DATA4 ((uint32_t)0x000000FF) /*!<Data byte 4 */
\r
1711 #define CAN_TDH1R_DATA5 ((uint32_t)0x0000FF00) /*!<Data byte 5 */
\r
1712 #define CAN_TDH1R_DATA6 ((uint32_t)0x00FF0000) /*!<Data byte 6 */
\r
1713 #define CAN_TDH1R_DATA7 ((uint32_t)0xFF000000) /*!<Data byte 7 */
\r
1715 /******************* Bit definition for CAN_TI2R register *******************/
\r
1716 #define CAN_TI2R_TXRQ ((uint32_t)0x00000001) /*!<Transmit Mailbox Request */
\r
1717 #define CAN_TI2R_RTR ((uint32_t)0x00000002) /*!<Remote Transmission Request */
\r
1718 #define CAN_TI2R_IDE ((uint32_t)0x00000004) /*!<Identifier Extension */
\r
1719 #define CAN_TI2R_EXID ((uint32_t)0x001FFFF8) /*!<Extended identifier */
\r
1720 #define CAN_TI2R_STID ((uint32_t)0xFFE00000) /*!<Standard Identifier or Extended Identifier */
\r
1722 /******************* Bit definition for CAN_TDT2R register ******************/
\r
1723 #define CAN_TDT2R_DLC ((uint32_t)0x0000000F) /*!<Data Length Code */
\r
1724 #define CAN_TDT2R_TGT ((uint32_t)0x00000100) /*!<Transmit Global Time */
\r
1725 #define CAN_TDT2R_TIME ((uint32_t)0xFFFF0000) /*!<Message Time Stamp */
\r
1727 /******************* Bit definition for CAN_TDL2R register ******************/
\r
1728 #define CAN_TDL2R_DATA0 ((uint32_t)0x000000FF) /*!<Data byte 0 */
\r
1729 #define CAN_TDL2R_DATA1 ((uint32_t)0x0000FF00) /*!<Data byte 1 */
\r
1730 #define CAN_TDL2R_DATA2 ((uint32_t)0x00FF0000) /*!<Data byte 2 */
\r
1731 #define CAN_TDL2R_DATA3 ((uint32_t)0xFF000000) /*!<Data byte 3 */
\r
1733 /******************* Bit definition for CAN_TDH2R register ******************/
\r
1734 #define CAN_TDH2R_DATA4 ((uint32_t)0x000000FF) /*!<Data byte 4 */
\r
1735 #define CAN_TDH2R_DATA5 ((uint32_t)0x0000FF00) /*!<Data byte 5 */
\r
1736 #define CAN_TDH2R_DATA6 ((uint32_t)0x00FF0000) /*!<Data byte 6 */
\r
1737 #define CAN_TDH2R_DATA7 ((uint32_t)0xFF000000) /*!<Data byte 7 */
\r
1739 /******************* Bit definition for CAN_RI0R register *******************/
\r
1740 #define CAN_RI0R_RTR ((uint32_t)0x00000002) /*!<Remote Transmission Request */
\r
1741 #define CAN_RI0R_IDE ((uint32_t)0x00000004) /*!<Identifier Extension */
\r
1742 #define CAN_RI0R_EXID ((uint32_t)0x001FFFF8) /*!<Extended Identifier */
\r
1743 #define CAN_RI0R_STID ((uint32_t)0xFFE00000) /*!<Standard Identifier or Extended Identifier */
\r
1745 /******************* Bit definition for CAN_RDT0R register ******************/
\r
1746 #define CAN_RDT0R_DLC ((uint32_t)0x0000000F) /*!<Data Length Code */
\r
1747 #define CAN_RDT0R_FMI ((uint32_t)0x0000FF00) /*!<Filter Match Index */
\r
1748 #define CAN_RDT0R_TIME ((uint32_t)0xFFFF0000) /*!<Message Time Stamp */
\r
1750 /******************* Bit definition for CAN_RDL0R register ******************/
\r
1751 #define CAN_RDL0R_DATA0 ((uint32_t)0x000000FF) /*!<Data byte 0 */
\r
1752 #define CAN_RDL0R_DATA1 ((uint32_t)0x0000FF00) /*!<Data byte 1 */
\r
1753 #define CAN_RDL0R_DATA2 ((uint32_t)0x00FF0000) /*!<Data byte 2 */
\r
1754 #define CAN_RDL0R_DATA3 ((uint32_t)0xFF000000) /*!<Data byte 3 */
\r
1756 /******************* Bit definition for CAN_RDH0R register ******************/
\r
1757 #define CAN_RDH0R_DATA4 ((uint32_t)0x000000FF) /*!<Data byte 4 */
\r
1758 #define CAN_RDH0R_DATA5 ((uint32_t)0x0000FF00) /*!<Data byte 5 */
\r
1759 #define CAN_RDH0R_DATA6 ((uint32_t)0x00FF0000) /*!<Data byte 6 */
\r
1760 #define CAN_RDH0R_DATA7 ((uint32_t)0xFF000000) /*!<Data byte 7 */
\r
1762 /******************* Bit definition for CAN_RI1R register *******************/
\r
1763 #define CAN_RI1R_RTR ((uint32_t)0x00000002) /*!<Remote Transmission Request */
\r
1764 #define CAN_RI1R_IDE ((uint32_t)0x00000004) /*!<Identifier Extension */
\r
1765 #define CAN_RI1R_EXID ((uint32_t)0x001FFFF8) /*!<Extended identifier */
\r
1766 #define CAN_RI1R_STID ((uint32_t)0xFFE00000) /*!<Standard Identifier or Extended Identifier */
\r
1768 /******************* Bit definition for CAN_RDT1R register ******************/
\r
1769 #define CAN_RDT1R_DLC ((uint32_t)0x0000000F) /*!<Data Length Code */
\r
1770 #define CAN_RDT1R_FMI ((uint32_t)0x0000FF00) /*!<Filter Match Index */
\r
1771 #define CAN_RDT1R_TIME ((uint32_t)0xFFFF0000) /*!<Message Time Stamp */
\r
1773 /******************* Bit definition for CAN_RDL1R register ******************/
\r
1774 #define CAN_RDL1R_DATA0 ((uint32_t)0x000000FF) /*!<Data byte 0 */
\r
1775 #define CAN_RDL1R_DATA1 ((uint32_t)0x0000FF00) /*!<Data byte 1 */
\r
1776 #define CAN_RDL1R_DATA2 ((uint32_t)0x00FF0000) /*!<Data byte 2 */
\r
1777 #define CAN_RDL1R_DATA3 ((uint32_t)0xFF000000) /*!<Data byte 3 */
\r
1779 /******************* Bit definition for CAN_RDH1R register ******************/
\r
1780 #define CAN_RDH1R_DATA4 ((uint32_t)0x000000FF) /*!<Data byte 4 */
\r
1781 #define CAN_RDH1R_DATA5 ((uint32_t)0x0000FF00) /*!<Data byte 5 */
\r
1782 #define CAN_RDH1R_DATA6 ((uint32_t)0x00FF0000) /*!<Data byte 6 */
\r
1783 #define CAN_RDH1R_DATA7 ((uint32_t)0xFF000000) /*!<Data byte 7 */
\r
1785 /*!<CAN filter registers */
\r
1786 /******************* Bit definition for CAN_FMR register ********************/
\r
1787 #define CAN_FMR_FINIT ((uint32_t)0x01) /*!<Filter Init Mode */
\r
1788 #define CAN_FMR_CAN2SB ((uint32_t)0x00003F00) /*!<CAN2 start bank */
\r
1790 /******************* Bit definition for CAN_FM1R register *******************/
\r
1791 #define CAN_FM1R_FBM ((uint32_t)0x3FFF) /*!<Filter Mode */
\r
1792 #define CAN_FM1R_FBM0 ((uint32_t)0x0001) /*!<Filter Init Mode bit 0 */
\r
1793 #define CAN_FM1R_FBM1 ((uint32_t)0x0002) /*!<Filter Init Mode bit 1 */
\r
1794 #define CAN_FM1R_FBM2 ((uint32_t)0x0004) /*!<Filter Init Mode bit 2 */
\r
1795 #define CAN_FM1R_FBM3 ((uint32_t)0x0008) /*!<Filter Init Mode bit 3 */
\r
1796 #define CAN_FM1R_FBM4 ((uint32_t)0x0010) /*!<Filter Init Mode bit 4 */
\r
1797 #define CAN_FM1R_FBM5 ((uint32_t)0x0020) /*!<Filter Init Mode bit 5 */
\r
1798 #define CAN_FM1R_FBM6 ((uint32_t)0x0040) /*!<Filter Init Mode bit 6 */
\r
1799 #define CAN_FM1R_FBM7 ((uint32_t)0x0080) /*!<Filter Init Mode bit 7 */
\r
1800 #define CAN_FM1R_FBM8 ((uint32_t)0x0100) /*!<Filter Init Mode bit 8 */
\r
1801 #define CAN_FM1R_FBM9 ((uint32_t)0x0200) /*!<Filter Init Mode bit 9 */
\r
1802 #define CAN_FM1R_FBM10 ((uint32_t)0x0400) /*!<Filter Init Mode bit 10 */
\r
1803 #define CAN_FM1R_FBM11 ((uint32_t)0x0800) /*!<Filter Init Mode bit 11 */
\r
1804 #define CAN_FM1R_FBM12 ((uint32_t)0x1000) /*!<Filter Init Mode bit 12 */
\r
1805 #define CAN_FM1R_FBM13 ((uint32_t)0x2000) /*!<Filter Init Mode bit 13 */
\r
1807 /******************* Bit definition for CAN_FS1R register *******************/
\r
1808 #define CAN_FS1R_FSC ((uint32_t)0x3FFF) /*!<Filter Scale Configuration */
\r
1809 #define CAN_FS1R_FSC0 ((uint32_t)0x0001) /*!<Filter Scale Configuration bit 0 */
\r
1810 #define CAN_FS1R_FSC1 ((uint32_t)0x0002) /*!<Filter Scale Configuration bit 1 */
\r
1811 #define CAN_FS1R_FSC2 ((uint32_t)0x0004) /*!<Filter Scale Configuration bit 2 */
\r
1812 #define CAN_FS1R_FSC3 ((uint32_t)0x0008) /*!<Filter Scale Configuration bit 3 */
\r
1813 #define CAN_FS1R_FSC4 ((uint32_t)0x0010) /*!<Filter Scale Configuration bit 4 */
\r
1814 #define CAN_FS1R_FSC5 ((uint32_t)0x0020) /*!<Filter Scale Configuration bit 5 */
\r
1815 #define CAN_FS1R_FSC6 ((uint32_t)0x0040) /*!<Filter Scale Configuration bit 6 */
\r
1816 #define CAN_FS1R_FSC7 ((uint32_t)0x0080) /*!<Filter Scale Configuration bit 7 */
\r
1817 #define CAN_FS1R_FSC8 ((uint32_t)0x0100) /*!<Filter Scale Configuration bit 8 */
\r
1818 #define CAN_FS1R_FSC9 ((uint32_t)0x0200) /*!<Filter Scale Configuration bit 9 */
\r
1819 #define CAN_FS1R_FSC10 ((uint32_t)0x0400) /*!<Filter Scale Configuration bit 10 */
\r
1820 #define CAN_FS1R_FSC11 ((uint32_t)0x0800) /*!<Filter Scale Configuration bit 11 */
\r
1821 #define CAN_FS1R_FSC12 ((uint32_t)0x1000) /*!<Filter Scale Configuration bit 12 */
\r
1822 #define CAN_FS1R_FSC13 ((uint32_t)0x2000) /*!<Filter Scale Configuration bit 13 */
\r
1824 /****************** Bit definition for CAN_FFA1R register *******************/
\r
1825 #define CAN_FFA1R_FFA ((uint32_t)0x3FFF) /*!<Filter FIFO Assignment */
\r
1826 #define CAN_FFA1R_FFA0 ((uint32_t)0x0001) /*!<Filter FIFO Assignment for Filter 0 */
\r
1827 #define CAN_FFA1R_FFA1 ((uint32_t)0x0002) /*!<Filter FIFO Assignment for Filter 1 */
\r
1828 #define CAN_FFA1R_FFA2 ((uint32_t)0x0004) /*!<Filter FIFO Assignment for Filter 2 */
\r
1829 #define CAN_FFA1R_FFA3 ((uint32_t)0x0008) /*!<Filter FIFO Assignment for Filter 3 */
\r
1830 #define CAN_FFA1R_FFA4 ((uint32_t)0x0010) /*!<Filter FIFO Assignment for Filter 4 */
\r
1831 #define CAN_FFA1R_FFA5 ((uint32_t)0x0020) /*!<Filter FIFO Assignment for Filter 5 */
\r
1832 #define CAN_FFA1R_FFA6 ((uint32_t)0x0040) /*!<Filter FIFO Assignment for Filter 6 */
\r
1833 #define CAN_FFA1R_FFA7 ((uint32_t)0x0080) /*!<Filter FIFO Assignment for Filter 7 */
\r
1834 #define CAN_FFA1R_FFA8 ((uint32_t)0x0100) /*!<Filter FIFO Assignment for Filter 8 */
\r
1835 #define CAN_FFA1R_FFA9 ((uint32_t)0x0200) /*!<Filter FIFO Assignment for Filter 9 */
\r
1836 #define CAN_FFA1R_FFA10 ((uint32_t)0x0400) /*!<Filter FIFO Assignment for Filter 10 */
\r
1837 #define CAN_FFA1R_FFA11 ((uint32_t)0x0800) /*!<Filter FIFO Assignment for Filter 11 */
\r
1838 #define CAN_FFA1R_FFA12 ((uint32_t)0x1000) /*!<Filter FIFO Assignment for Filter 12 */
\r
1839 #define CAN_FFA1R_FFA13 ((uint32_t)0x2000) /*!<Filter FIFO Assignment for Filter 13 */
\r
1841 /******************* Bit definition for CAN_FA1R register *******************/
\r
1842 #define CAN_FA1R_FACT ((uint32_t)0x3FFF) /*!<Filter Active */
\r
1843 #define CAN_FA1R_FACT0 ((uint32_t)0x0001) /*!<Filter 0 Active */
\r
1844 #define CAN_FA1R_FACT1 ((uint32_t)0x0002) /*!<Filter 1 Active */
\r
1845 #define CAN_FA1R_FACT2 ((uint32_t)0x0004) /*!<Filter 2 Active */
\r
1846 #define CAN_FA1R_FACT3 ((uint32_t)0x0008) /*!<Filter 3 Active */
\r
1847 #define CAN_FA1R_FACT4 ((uint32_t)0x0010) /*!<Filter 4 Active */
\r
1848 #define CAN_FA1R_FACT5 ((uint32_t)0x0020) /*!<Filter 5 Active */
\r
1849 #define CAN_FA1R_FACT6 ((uint32_t)0x0040) /*!<Filter 6 Active */
\r
1850 #define CAN_FA1R_FACT7 ((uint32_t)0x0080) /*!<Filter 7 Active */
\r
1851 #define CAN_FA1R_FACT8 ((uint32_t)0x0100) /*!<Filter 8 Active */
\r
1852 #define CAN_FA1R_FACT9 ((uint32_t)0x0200) /*!<Filter 9 Active */
\r
1853 #define CAN_FA1R_FACT10 ((uint32_t)0x0400) /*!<Filter 10 Active */
\r
1854 #define CAN_FA1R_FACT11 ((uint32_t)0x0800) /*!<Filter 11 Active */
\r
1855 #define CAN_FA1R_FACT12 ((uint32_t)0x1000) /*!<Filter 12 Active */
\r
1856 #define CAN_FA1R_FACT13 ((uint32_t)0x2000) /*!<Filter 13 Active */
\r
1858 /******************* Bit definition for CAN_F0R1 register *******************/
\r
1859 #define CAN_F0R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
\r
1860 #define CAN_F0R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
\r
1861 #define CAN_F0R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
\r
1862 #define CAN_F0R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
\r
1863 #define CAN_F0R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
\r
1864 #define CAN_F0R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
\r
1865 #define CAN_F0R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
\r
1866 #define CAN_F0R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
\r
1867 #define CAN_F0R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
\r
1868 #define CAN_F0R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
\r
1869 #define CAN_F0R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
\r
1870 #define CAN_F0R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
\r
1871 #define CAN_F0R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
\r
1872 #define CAN_F0R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
\r
1873 #define CAN_F0R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
\r
1874 #define CAN_F0R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
\r
1875 #define CAN_F0R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
\r
1876 #define CAN_F0R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
\r
1877 #define CAN_F0R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
\r
1878 #define CAN_F0R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
\r
1879 #define CAN_F0R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
\r
1880 #define CAN_F0R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
\r
1881 #define CAN_F0R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
\r
1882 #define CAN_F0R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
\r
1883 #define CAN_F0R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
\r
1884 #define CAN_F0R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
\r
1885 #define CAN_F0R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
\r
1886 #define CAN_F0R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
\r
1887 #define CAN_F0R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
\r
1888 #define CAN_F0R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
\r
1889 #define CAN_F0R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
\r
1890 #define CAN_F0R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
\r
1892 /******************* Bit definition for CAN_F1R1 register *******************/
\r
1893 #define CAN_F1R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
\r
1894 #define CAN_F1R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
\r
1895 #define CAN_F1R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
\r
1896 #define CAN_F1R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
\r
1897 #define CAN_F1R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
\r
1898 #define CAN_F1R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
\r
1899 #define CAN_F1R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
\r
1900 #define CAN_F1R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
\r
1901 #define CAN_F1R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
\r
1902 #define CAN_F1R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
\r
1903 #define CAN_F1R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
\r
1904 #define CAN_F1R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
\r
1905 #define CAN_F1R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
\r
1906 #define CAN_F1R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
\r
1907 #define CAN_F1R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
\r
1908 #define CAN_F1R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
\r
1909 #define CAN_F1R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
\r
1910 #define CAN_F1R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
\r
1911 #define CAN_F1R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
\r
1912 #define CAN_F1R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
\r
1913 #define CAN_F1R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
\r
1914 #define CAN_F1R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
\r
1915 #define CAN_F1R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
\r
1916 #define CAN_F1R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
\r
1917 #define CAN_F1R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
\r
1918 #define CAN_F1R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
\r
1919 #define CAN_F1R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
\r
1920 #define CAN_F1R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
\r
1921 #define CAN_F1R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
\r
1922 #define CAN_F1R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
\r
1923 #define CAN_F1R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
\r
1924 #define CAN_F1R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
\r
1926 /******************* Bit definition for CAN_F2R1 register *******************/
\r
1927 #define CAN_F2R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
\r
1928 #define CAN_F2R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
\r
1929 #define CAN_F2R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
\r
1930 #define CAN_F2R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
\r
1931 #define CAN_F2R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
\r
1932 #define CAN_F2R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
\r
1933 #define CAN_F2R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
\r
1934 #define CAN_F2R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
\r
1935 #define CAN_F2R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
\r
1936 #define CAN_F2R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
\r
1937 #define CAN_F2R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
\r
1938 #define CAN_F2R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
\r
1939 #define CAN_F2R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
\r
1940 #define CAN_F2R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
\r
1941 #define CAN_F2R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
\r
1942 #define CAN_F2R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
\r
1943 #define CAN_F2R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
\r
1944 #define CAN_F2R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
\r
1945 #define CAN_F2R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
\r
1946 #define CAN_F2R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
\r
1947 #define CAN_F2R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
\r
1948 #define CAN_F2R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
\r
1949 #define CAN_F2R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
\r
1950 #define CAN_F2R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
\r
1951 #define CAN_F2R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
\r
1952 #define CAN_F2R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
\r
1953 #define CAN_F2R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
\r
1954 #define CAN_F2R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
\r
1955 #define CAN_F2R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
\r
1956 #define CAN_F2R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
\r
1957 #define CAN_F2R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
\r
1958 #define CAN_F2R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
\r
1960 /******************* Bit definition for CAN_F3R1 register *******************/
\r
1961 #define CAN_F3R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
\r
1962 #define CAN_F3R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
\r
1963 #define CAN_F3R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
\r
1964 #define CAN_F3R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
\r
1965 #define CAN_F3R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
\r
1966 #define CAN_F3R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
\r
1967 #define CAN_F3R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
\r
1968 #define CAN_F3R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
\r
1969 #define CAN_F3R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
\r
1970 #define CAN_F3R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
\r
1971 #define CAN_F3R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
\r
1972 #define CAN_F3R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
\r
1973 #define CAN_F3R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
\r
1974 #define CAN_F3R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
\r
1975 #define CAN_F3R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
\r
1976 #define CAN_F3R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
\r
1977 #define CAN_F3R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
\r
1978 #define CAN_F3R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
\r
1979 #define CAN_F3R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
\r
1980 #define CAN_F3R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
\r
1981 #define CAN_F3R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
\r
1982 #define CAN_F3R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
\r
1983 #define CAN_F3R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
\r
1984 #define CAN_F3R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
\r
1985 #define CAN_F3R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
\r
1986 #define CAN_F3R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
\r
1987 #define CAN_F3R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
\r
1988 #define CAN_F3R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
\r
1989 #define CAN_F3R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
\r
1990 #define CAN_F3R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
\r
1991 #define CAN_F3R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
\r
1992 #define CAN_F3R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
\r
1994 /******************* Bit definition for CAN_F4R1 register *******************/
\r
1995 #define CAN_F4R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
\r
1996 #define CAN_F4R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
\r
1997 #define CAN_F4R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
\r
1998 #define CAN_F4R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
\r
1999 #define CAN_F4R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
\r
2000 #define CAN_F4R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
\r
2001 #define CAN_F4R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
\r
2002 #define CAN_F4R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
\r
2003 #define CAN_F4R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
\r
2004 #define CAN_F4R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
\r
2005 #define CAN_F4R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
\r
2006 #define CAN_F4R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
\r
2007 #define CAN_F4R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
\r
2008 #define CAN_F4R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
\r
2009 #define CAN_F4R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
\r
2010 #define CAN_F4R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
\r
2011 #define CAN_F4R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
\r
2012 #define CAN_F4R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
\r
2013 #define CAN_F4R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
\r
2014 #define CAN_F4R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
\r
2015 #define CAN_F4R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
\r
2016 #define CAN_F4R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
\r
2017 #define CAN_F4R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
\r
2018 #define CAN_F4R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
\r
2019 #define CAN_F4R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
\r
2020 #define CAN_F4R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
\r
2021 #define CAN_F4R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
\r
2022 #define CAN_F4R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
\r
2023 #define CAN_F4R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
\r
2024 #define CAN_F4R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
\r
2025 #define CAN_F4R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
\r
2026 #define CAN_F4R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
\r
2028 /******************* Bit definition for CAN_F5R1 register *******************/
\r
2029 #define CAN_F5R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
\r
2030 #define CAN_F5R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
\r
2031 #define CAN_F5R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
\r
2032 #define CAN_F5R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
\r
2033 #define CAN_F5R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
\r
2034 #define CAN_F5R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
\r
2035 #define CAN_F5R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
\r
2036 #define CAN_F5R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
\r
2037 #define CAN_F5R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
\r
2038 #define CAN_F5R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
\r
2039 #define CAN_F5R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
\r
2040 #define CAN_F5R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
\r
2041 #define CAN_F5R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
\r
2042 #define CAN_F5R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
\r
2043 #define CAN_F5R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
\r
2044 #define CAN_F5R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
\r
2045 #define CAN_F5R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
\r
2046 #define CAN_F5R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
\r
2047 #define CAN_F5R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
\r
2048 #define CAN_F5R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
\r
2049 #define CAN_F5R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
\r
2050 #define CAN_F5R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
\r
2051 #define CAN_F5R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
\r
2052 #define CAN_F5R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
\r
2053 #define CAN_F5R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
\r
2054 #define CAN_F5R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
\r
2055 #define CAN_F5R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
\r
2056 #define CAN_F5R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
\r
2057 #define CAN_F5R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
\r
2058 #define CAN_F5R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
\r
2059 #define CAN_F5R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
\r
2060 #define CAN_F5R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
\r
2062 /******************* Bit definition for CAN_F6R1 register *******************/
\r
2063 #define CAN_F6R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
\r
2064 #define CAN_F6R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
\r
2065 #define CAN_F6R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
\r
2066 #define CAN_F6R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
\r
2067 #define CAN_F6R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
\r
2068 #define CAN_F6R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
\r
2069 #define CAN_F6R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
\r
2070 #define CAN_F6R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
\r
2071 #define CAN_F6R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
\r
2072 #define CAN_F6R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
\r
2073 #define CAN_F6R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
\r
2074 #define CAN_F6R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
\r
2075 #define CAN_F6R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
\r
2076 #define CAN_F6R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
\r
2077 #define CAN_F6R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
\r
2078 #define CAN_F6R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
\r
2079 #define CAN_F6R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
\r
2080 #define CAN_F6R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
\r
2081 #define CAN_F6R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
\r
2082 #define CAN_F6R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
\r
2083 #define CAN_F6R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
\r
2084 #define CAN_F6R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
\r
2085 #define CAN_F6R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
\r
2086 #define CAN_F6R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
\r
2087 #define CAN_F6R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
\r
2088 #define CAN_F6R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
\r
2089 #define CAN_F6R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
\r
2090 #define CAN_F6R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
\r
2091 #define CAN_F6R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
\r
2092 #define CAN_F6R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
\r
2093 #define CAN_F6R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
\r
2094 #define CAN_F6R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
\r
2096 /******************* Bit definition for CAN_F7R1 register *******************/
\r
2097 #define CAN_F7R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
\r
2098 #define CAN_F7R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
\r
2099 #define CAN_F7R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
\r
2100 #define CAN_F7R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
\r
2101 #define CAN_F7R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
\r
2102 #define CAN_F7R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
\r
2103 #define CAN_F7R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
\r
2104 #define CAN_F7R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
\r
2105 #define CAN_F7R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
\r
2106 #define CAN_F7R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
\r
2107 #define CAN_F7R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
\r
2108 #define CAN_F7R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
\r
2109 #define CAN_F7R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
\r
2110 #define CAN_F7R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
\r
2111 #define CAN_F7R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
\r
2112 #define CAN_F7R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
\r
2113 #define CAN_F7R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
\r
2114 #define CAN_F7R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
\r
2115 #define CAN_F7R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
\r
2116 #define CAN_F7R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
\r
2117 #define CAN_F7R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
\r
2118 #define CAN_F7R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
\r
2119 #define CAN_F7R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
\r
2120 #define CAN_F7R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
\r
2121 #define CAN_F7R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
\r
2122 #define CAN_F7R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
\r
2123 #define CAN_F7R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
\r
2124 #define CAN_F7R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
\r
2125 #define CAN_F7R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
\r
2126 #define CAN_F7R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
\r
2127 #define CAN_F7R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
\r
2128 #define CAN_F7R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
\r
2130 /******************* Bit definition for CAN_F8R1 register *******************/
\r
2131 #define CAN_F8R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
\r
2132 #define CAN_F8R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
\r
2133 #define CAN_F8R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
\r
2134 #define CAN_F8R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
\r
2135 #define CAN_F8R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
\r
2136 #define CAN_F8R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
\r
2137 #define CAN_F8R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
\r
2138 #define CAN_F8R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
\r
2139 #define CAN_F8R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
\r
2140 #define CAN_F8R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
\r
2141 #define CAN_F8R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
\r
2142 #define CAN_F8R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
\r
2143 #define CAN_F8R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
\r
2144 #define CAN_F8R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
\r
2145 #define CAN_F8R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
\r
2146 #define CAN_F8R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
\r
2147 #define CAN_F8R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
\r
2148 #define CAN_F8R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
\r
2149 #define CAN_F8R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
\r
2150 #define CAN_F8R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
\r
2151 #define CAN_F8R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
\r
2152 #define CAN_F8R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
\r
2153 #define CAN_F8R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
\r
2154 #define CAN_F8R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
\r
2155 #define CAN_F8R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
\r
2156 #define CAN_F8R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
\r
2157 #define CAN_F8R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
\r
2158 #define CAN_F8R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
\r
2159 #define CAN_F8R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
\r
2160 #define CAN_F8R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
\r
2161 #define CAN_F8R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
\r
2162 #define CAN_F8R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
\r
2164 /******************* Bit definition for CAN_F9R1 register *******************/
\r
2165 #define CAN_F9R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
\r
2166 #define CAN_F9R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
\r
2167 #define CAN_F9R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
\r
2168 #define CAN_F9R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
\r
2169 #define CAN_F9R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
\r
2170 #define CAN_F9R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
\r
2171 #define CAN_F9R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
\r
2172 #define CAN_F9R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
\r
2173 #define CAN_F9R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
\r
2174 #define CAN_F9R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
\r
2175 #define CAN_F9R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
\r
2176 #define CAN_F9R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
\r
2177 #define CAN_F9R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
\r
2178 #define CAN_F9R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
\r
2179 #define CAN_F9R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
\r
2180 #define CAN_F9R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
\r
2181 #define CAN_F9R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
\r
2182 #define CAN_F9R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
\r
2183 #define CAN_F9R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
\r
2184 #define CAN_F9R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
\r
2185 #define CAN_F9R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
\r
2186 #define CAN_F9R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
\r
2187 #define CAN_F9R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
\r
2188 #define CAN_F9R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
\r
2189 #define CAN_F9R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
\r
2190 #define CAN_F9R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
\r
2191 #define CAN_F9R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
\r
2192 #define CAN_F9R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
\r
2193 #define CAN_F9R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
\r
2194 #define CAN_F9R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
\r
2195 #define CAN_F9R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
\r
2196 #define CAN_F9R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
\r
2198 /******************* Bit definition for CAN_F10R1 register ******************/
\r
2199 #define CAN_F10R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
\r
2200 #define CAN_F10R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
\r
2201 #define CAN_F10R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
\r
2202 #define CAN_F10R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
\r
2203 #define CAN_F10R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
\r
2204 #define CAN_F10R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
\r
2205 #define CAN_F10R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
\r
2206 #define CAN_F10R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
\r
2207 #define CAN_F10R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
\r
2208 #define CAN_F10R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
\r
2209 #define CAN_F10R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
\r
2210 #define CAN_F10R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
\r
2211 #define CAN_F10R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
\r
2212 #define CAN_F10R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
\r
2213 #define CAN_F10R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
\r
2214 #define CAN_F10R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
\r
2215 #define CAN_F10R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
\r
2216 #define CAN_F10R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
\r
2217 #define CAN_F10R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
\r
2218 #define CAN_F10R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
\r
2219 #define CAN_F10R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
\r
2220 #define CAN_F10R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
\r
2221 #define CAN_F10R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
\r
2222 #define CAN_F10R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
\r
2223 #define CAN_F10R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
\r
2224 #define CAN_F10R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
\r
2225 #define CAN_F10R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
\r
2226 #define CAN_F10R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
\r
2227 #define CAN_F10R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
\r
2228 #define CAN_F10R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
\r
2229 #define CAN_F10R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
\r
2230 #define CAN_F10R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
\r
2232 /******************* Bit definition for CAN_F11R1 register ******************/
\r
2233 #define CAN_F11R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
\r
2234 #define CAN_F11R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
\r
2235 #define CAN_F11R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
\r
2236 #define CAN_F11R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
\r
2237 #define CAN_F11R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
\r
2238 #define CAN_F11R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
\r
2239 #define CAN_F11R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
\r
2240 #define CAN_F11R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
\r
2241 #define CAN_F11R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
\r
2242 #define CAN_F11R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
\r
2243 #define CAN_F11R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
\r
2244 #define CAN_F11R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
\r
2245 #define CAN_F11R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
\r
2246 #define CAN_F11R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
\r
2247 #define CAN_F11R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
\r
2248 #define CAN_F11R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
\r
2249 #define CAN_F11R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
\r
2250 #define CAN_F11R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
\r
2251 #define CAN_F11R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
\r
2252 #define CAN_F11R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
\r
2253 #define CAN_F11R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
\r
2254 #define CAN_F11R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
\r
2255 #define CAN_F11R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
\r
2256 #define CAN_F11R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
\r
2257 #define CAN_F11R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
\r
2258 #define CAN_F11R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
\r
2259 #define CAN_F11R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
\r
2260 #define CAN_F11R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
\r
2261 #define CAN_F11R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
\r
2262 #define CAN_F11R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
\r
2263 #define CAN_F11R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
\r
2264 #define CAN_F11R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
\r
2266 /******************* Bit definition for CAN_F12R1 register ******************/
\r
2267 #define CAN_F12R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
\r
2268 #define CAN_F12R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
\r
2269 #define CAN_F12R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
\r
2270 #define CAN_F12R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
\r
2271 #define CAN_F12R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
\r
2272 #define CAN_F12R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
\r
2273 #define CAN_F12R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
\r
2274 #define CAN_F12R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
\r
2275 #define CAN_F12R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
\r
2276 #define CAN_F12R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
\r
2277 #define CAN_F12R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
\r
2278 #define CAN_F12R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
\r
2279 #define CAN_F12R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
\r
2280 #define CAN_F12R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
\r
2281 #define CAN_F12R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
\r
2282 #define CAN_F12R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
\r
2283 #define CAN_F12R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
\r
2284 #define CAN_F12R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
\r
2285 #define CAN_F12R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
\r
2286 #define CAN_F12R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
\r
2287 #define CAN_F12R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
\r
2288 #define CAN_F12R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
\r
2289 #define CAN_F12R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
\r
2290 #define CAN_F12R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
\r
2291 #define CAN_F12R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
\r
2292 #define CAN_F12R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
\r
2293 #define CAN_F12R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
\r
2294 #define CAN_F12R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
\r
2295 #define CAN_F12R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
\r
2296 #define CAN_F12R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
\r
2297 #define CAN_F12R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
\r
2298 #define CAN_F12R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
\r
2300 /******************* Bit definition for CAN_F13R1 register ******************/
\r
2301 #define CAN_F13R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
\r
2302 #define CAN_F13R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
\r
2303 #define CAN_F13R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
\r
2304 #define CAN_F13R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
\r
2305 #define CAN_F13R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
\r
2306 #define CAN_F13R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
\r
2307 #define CAN_F13R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
\r
2308 #define CAN_F13R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
\r
2309 #define CAN_F13R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
\r
2310 #define CAN_F13R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
\r
2311 #define CAN_F13R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
\r
2312 #define CAN_F13R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
\r
2313 #define CAN_F13R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
\r
2314 #define CAN_F13R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
\r
2315 #define CAN_F13R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
\r
2316 #define CAN_F13R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
\r
2317 #define CAN_F13R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
\r
2318 #define CAN_F13R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
\r
2319 #define CAN_F13R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
\r
2320 #define CAN_F13R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
\r
2321 #define CAN_F13R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
\r
2322 #define CAN_F13R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
\r
2323 #define CAN_F13R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
\r
2324 #define CAN_F13R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
\r
2325 #define CAN_F13R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
\r
2326 #define CAN_F13R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
\r
2327 #define CAN_F13R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
\r
2328 #define CAN_F13R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
\r
2329 #define CAN_F13R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
\r
2330 #define CAN_F13R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
\r
2331 #define CAN_F13R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
\r
2332 #define CAN_F13R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
\r
2334 /******************* Bit definition for CAN_F0R2 register *******************/
\r
2335 #define CAN_F0R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
\r
2336 #define CAN_F0R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
\r
2337 #define CAN_F0R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
\r
2338 #define CAN_F0R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
\r
2339 #define CAN_F0R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
\r
2340 #define CAN_F0R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
\r
2341 #define CAN_F0R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
\r
2342 #define CAN_F0R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
\r
2343 #define CAN_F0R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
\r
2344 #define CAN_F0R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
\r
2345 #define CAN_F0R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
\r
2346 #define CAN_F0R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
\r
2347 #define CAN_F0R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
\r
2348 #define CAN_F0R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
\r
2349 #define CAN_F0R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
\r
2350 #define CAN_F0R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
\r
2351 #define CAN_F0R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
\r
2352 #define CAN_F0R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
\r
2353 #define CAN_F0R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
\r
2354 #define CAN_F0R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
\r
2355 #define CAN_F0R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
\r
2356 #define CAN_F0R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
\r
2357 #define CAN_F0R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
\r
2358 #define CAN_F0R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
\r
2359 #define CAN_F0R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
\r
2360 #define CAN_F0R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
\r
2361 #define CAN_F0R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
\r
2362 #define CAN_F0R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
\r
2363 #define CAN_F0R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
\r
2364 #define CAN_F0R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
\r
2365 #define CAN_F0R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
\r
2366 #define CAN_F0R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
\r
2368 /******************* Bit definition for CAN_F1R2 register *******************/
\r
2369 #define CAN_F1R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
\r
2370 #define CAN_F1R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
\r
2371 #define CAN_F1R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
\r
2372 #define CAN_F1R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
\r
2373 #define CAN_F1R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
\r
2374 #define CAN_F1R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
\r
2375 #define CAN_F1R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
\r
2376 #define CAN_F1R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
\r
2377 #define CAN_F1R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
\r
2378 #define CAN_F1R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
\r
2379 #define CAN_F1R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
\r
2380 #define CAN_F1R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
\r
2381 #define CAN_F1R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
\r
2382 #define CAN_F1R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
\r
2383 #define CAN_F1R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
\r
2384 #define CAN_F1R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
\r
2385 #define CAN_F1R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
\r
2386 #define CAN_F1R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
\r
2387 #define CAN_F1R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
\r
2388 #define CAN_F1R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
\r
2389 #define CAN_F1R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
\r
2390 #define CAN_F1R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
\r
2391 #define CAN_F1R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
\r
2392 #define CAN_F1R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
\r
2393 #define CAN_F1R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
\r
2394 #define CAN_F1R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
\r
2395 #define CAN_F1R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
\r
2396 #define CAN_F1R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
\r
2397 #define CAN_F1R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
\r
2398 #define CAN_F1R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
\r
2399 #define CAN_F1R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
\r
2400 #define CAN_F1R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
\r
2402 /******************* Bit definition for CAN_F2R2 register *******************/
\r
2403 #define CAN_F2R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
\r
2404 #define CAN_F2R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
\r
2405 #define CAN_F2R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
\r
2406 #define CAN_F2R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
\r
2407 #define CAN_F2R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
\r
2408 #define CAN_F2R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
\r
2409 #define CAN_F2R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
\r
2410 #define CAN_F2R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
\r
2411 #define CAN_F2R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
\r
2412 #define CAN_F2R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
\r
2413 #define CAN_F2R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
\r
2414 #define CAN_F2R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
\r
2415 #define CAN_F2R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
\r
2416 #define CAN_F2R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
\r
2417 #define CAN_F2R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
\r
2418 #define CAN_F2R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
\r
2419 #define CAN_F2R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
\r
2420 #define CAN_F2R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
\r
2421 #define CAN_F2R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
\r
2422 #define CAN_F2R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
\r
2423 #define CAN_F2R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
\r
2424 #define CAN_F2R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
\r
2425 #define CAN_F2R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
\r
2426 #define CAN_F2R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
\r
2427 #define CAN_F2R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
\r
2428 #define CAN_F2R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
\r
2429 #define CAN_F2R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
\r
2430 #define CAN_F2R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
\r
2431 #define CAN_F2R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
\r
2432 #define CAN_F2R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
\r
2433 #define CAN_F2R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
\r
2434 #define CAN_F2R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
\r
2436 /******************* Bit definition for CAN_F3R2 register *******************/
\r
2437 #define CAN_F3R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
\r
2438 #define CAN_F3R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
\r
2439 #define CAN_F3R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
\r
2440 #define CAN_F3R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
\r
2441 #define CAN_F3R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
\r
2442 #define CAN_F3R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
\r
2443 #define CAN_F3R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
\r
2444 #define CAN_F3R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
\r
2445 #define CAN_F3R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
\r
2446 #define CAN_F3R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
\r
2447 #define CAN_F3R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
\r
2448 #define CAN_F3R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
\r
2449 #define CAN_F3R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
\r
2450 #define CAN_F3R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
\r
2451 #define CAN_F3R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
\r
2452 #define CAN_F3R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
\r
2453 #define CAN_F3R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
\r
2454 #define CAN_F3R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
\r
2455 #define CAN_F3R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
\r
2456 #define CAN_F3R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
\r
2457 #define CAN_F3R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
\r
2458 #define CAN_F3R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
\r
2459 #define CAN_F3R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
\r
2460 #define CAN_F3R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
\r
2461 #define CAN_F3R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
\r
2462 #define CAN_F3R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
\r
2463 #define CAN_F3R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
\r
2464 #define CAN_F3R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
\r
2465 #define CAN_F3R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
\r
2466 #define CAN_F3R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
\r
2467 #define CAN_F3R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
\r
2468 #define CAN_F3R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
\r
2470 /******************* Bit definition for CAN_F4R2 register *******************/
\r
2471 #define CAN_F4R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
\r
2472 #define CAN_F4R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
\r
2473 #define CAN_F4R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
\r
2474 #define CAN_F4R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
\r
2475 #define CAN_F4R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
\r
2476 #define CAN_F4R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
\r
2477 #define CAN_F4R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
\r
2478 #define CAN_F4R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
\r
2479 #define CAN_F4R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
\r
2480 #define CAN_F4R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
\r
2481 #define CAN_F4R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
\r
2482 #define CAN_F4R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
\r
2483 #define CAN_F4R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
\r
2484 #define CAN_F4R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
\r
2485 #define CAN_F4R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
\r
2486 #define CAN_F4R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
\r
2487 #define CAN_F4R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
\r
2488 #define CAN_F4R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
\r
2489 #define CAN_F4R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
\r
2490 #define CAN_F4R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
\r
2491 #define CAN_F4R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
\r
2492 #define CAN_F4R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
\r
2493 #define CAN_F4R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
\r
2494 #define CAN_F4R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
\r
2495 #define CAN_F4R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
\r
2496 #define CAN_F4R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
\r
2497 #define CAN_F4R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
\r
2498 #define CAN_F4R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
\r
2499 #define CAN_F4R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
\r
2500 #define CAN_F4R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
\r
2501 #define CAN_F4R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
\r
2502 #define CAN_F4R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
\r
2504 /******************* Bit definition for CAN_F5R2 register *******************/
\r
2505 #define CAN_F5R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
\r
2506 #define CAN_F5R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
\r
2507 #define CAN_F5R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
\r
2508 #define CAN_F5R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
\r
2509 #define CAN_F5R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
\r
2510 #define CAN_F5R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
\r
2511 #define CAN_F5R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
\r
2512 #define CAN_F5R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
\r
2513 #define CAN_F5R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
\r
2514 #define CAN_F5R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
\r
2515 #define CAN_F5R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
\r
2516 #define CAN_F5R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
\r
2517 #define CAN_F5R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
\r
2518 #define CAN_F5R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
\r
2519 #define CAN_F5R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
\r
2520 #define CAN_F5R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
\r
2521 #define CAN_F5R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
\r
2522 #define CAN_F5R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
\r
2523 #define CAN_F5R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
\r
2524 #define CAN_F5R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
\r
2525 #define CAN_F5R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
\r
2526 #define CAN_F5R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
\r
2527 #define CAN_F5R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
\r
2528 #define CAN_F5R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
\r
2529 #define CAN_F5R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
\r
2530 #define CAN_F5R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
\r
2531 #define CAN_F5R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
\r
2532 #define CAN_F5R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
\r
2533 #define CAN_F5R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
\r
2534 #define CAN_F5R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
\r
2535 #define CAN_F5R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
\r
2536 #define CAN_F5R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
\r
2538 /******************* Bit definition for CAN_F6R2 register *******************/
\r
2539 #define CAN_F6R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
\r
2540 #define CAN_F6R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
\r
2541 #define CAN_F6R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
\r
2542 #define CAN_F6R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
\r
2543 #define CAN_F6R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
\r
2544 #define CAN_F6R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
\r
2545 #define CAN_F6R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
\r
2546 #define CAN_F6R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
\r
2547 #define CAN_F6R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
\r
2548 #define CAN_F6R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
\r
2549 #define CAN_F6R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
\r
2550 #define CAN_F6R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
\r
2551 #define CAN_F6R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
\r
2552 #define CAN_F6R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
\r
2553 #define CAN_F6R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
\r
2554 #define CAN_F6R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
\r
2555 #define CAN_F6R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
\r
2556 #define CAN_F6R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
\r
2557 #define CAN_F6R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
\r
2558 #define CAN_F6R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
\r
2559 #define CAN_F6R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
\r
2560 #define CAN_F6R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
\r
2561 #define CAN_F6R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
\r
2562 #define CAN_F6R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
\r
2563 #define CAN_F6R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
\r
2564 #define CAN_F6R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
\r
2565 #define CAN_F6R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
\r
2566 #define CAN_F6R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
\r
2567 #define CAN_F6R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
\r
2568 #define CAN_F6R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
\r
2569 #define CAN_F6R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
\r
2570 #define CAN_F6R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
\r
2572 /******************* Bit definition for CAN_F7R2 register *******************/
\r
2573 #define CAN_F7R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
\r
2574 #define CAN_F7R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
\r
2575 #define CAN_F7R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
\r
2576 #define CAN_F7R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
\r
2577 #define CAN_F7R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
\r
2578 #define CAN_F7R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
\r
2579 #define CAN_F7R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
\r
2580 #define CAN_F7R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
\r
2581 #define CAN_F7R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
\r
2582 #define CAN_F7R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
\r
2583 #define CAN_F7R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
\r
2584 #define CAN_F7R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
\r
2585 #define CAN_F7R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
\r
2586 #define CAN_F7R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
\r
2587 #define CAN_F7R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
\r
2588 #define CAN_F7R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
\r
2589 #define CAN_F7R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
\r
2590 #define CAN_F7R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
\r
2591 #define CAN_F7R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
\r
2592 #define CAN_F7R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
\r
2593 #define CAN_F7R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
\r
2594 #define CAN_F7R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
\r
2595 #define CAN_F7R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
\r
2596 #define CAN_F7R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
\r
2597 #define CAN_F7R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
\r
2598 #define CAN_F7R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
\r
2599 #define CAN_F7R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
\r
2600 #define CAN_F7R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
\r
2601 #define CAN_F7R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
\r
2602 #define CAN_F7R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
\r
2603 #define CAN_F7R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
\r
2604 #define CAN_F7R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
\r
2606 /******************* Bit definition for CAN_F8R2 register *******************/
\r
2607 #define CAN_F8R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
\r
2608 #define CAN_F8R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
\r
2609 #define CAN_F8R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
\r
2610 #define CAN_F8R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
\r
2611 #define CAN_F8R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
\r
2612 #define CAN_F8R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
\r
2613 #define CAN_F8R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
\r
2614 #define CAN_F8R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
\r
2615 #define CAN_F8R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
\r
2616 #define CAN_F8R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
\r
2617 #define CAN_F8R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
\r
2618 #define CAN_F8R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
\r
2619 #define CAN_F8R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
\r
2620 #define CAN_F8R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
\r
2621 #define CAN_F8R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
\r
2622 #define CAN_F8R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
\r
2623 #define CAN_F8R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
\r
2624 #define CAN_F8R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
\r
2625 #define CAN_F8R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
\r
2626 #define CAN_F8R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
\r
2627 #define CAN_F8R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
\r
2628 #define CAN_F8R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
\r
2629 #define CAN_F8R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
\r
2630 #define CAN_F8R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
\r
2631 #define CAN_F8R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
\r
2632 #define CAN_F8R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
\r
2633 #define CAN_F8R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
\r
2634 #define CAN_F8R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
\r
2635 #define CAN_F8R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
\r
2636 #define CAN_F8R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
\r
2637 #define CAN_F8R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
\r
2638 #define CAN_F8R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
\r
2640 /******************* Bit definition for CAN_F9R2 register *******************/
\r
2641 #define CAN_F9R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
\r
2642 #define CAN_F9R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
\r
2643 #define CAN_F9R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
\r
2644 #define CAN_F9R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
\r
2645 #define CAN_F9R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
\r
2646 #define CAN_F9R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
\r
2647 #define CAN_F9R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
\r
2648 #define CAN_F9R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
\r
2649 #define CAN_F9R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
\r
2650 #define CAN_F9R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
\r
2651 #define CAN_F9R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
\r
2652 #define CAN_F9R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
\r
2653 #define CAN_F9R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
\r
2654 #define CAN_F9R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
\r
2655 #define CAN_F9R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
\r
2656 #define CAN_F9R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
\r
2657 #define CAN_F9R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
\r
2658 #define CAN_F9R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
\r
2659 #define CAN_F9R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
\r
2660 #define CAN_F9R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
\r
2661 #define CAN_F9R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
\r
2662 #define CAN_F9R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
\r
2663 #define CAN_F9R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
\r
2664 #define CAN_F9R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
\r
2665 #define CAN_F9R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
\r
2666 #define CAN_F9R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
\r
2667 #define CAN_F9R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
\r
2668 #define CAN_F9R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
\r
2669 #define CAN_F9R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
\r
2670 #define CAN_F9R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
\r
2671 #define CAN_F9R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
\r
2672 #define CAN_F9R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
\r
2674 /******************* Bit definition for CAN_F10R2 register ******************/
\r
2675 #define CAN_F10R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
\r
2676 #define CAN_F10R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
\r
2677 #define CAN_F10R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
\r
2678 #define CAN_F10R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
\r
2679 #define CAN_F10R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
\r
2680 #define CAN_F10R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
\r
2681 #define CAN_F10R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
\r
2682 #define CAN_F10R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
\r
2683 #define CAN_F10R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
\r
2684 #define CAN_F10R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
\r
2685 #define CAN_F10R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
\r
2686 #define CAN_F10R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
\r
2687 #define CAN_F10R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
\r
2688 #define CAN_F10R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
\r
2689 #define CAN_F10R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
\r
2690 #define CAN_F10R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
\r
2691 #define CAN_F10R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
\r
2692 #define CAN_F10R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
\r
2693 #define CAN_F10R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
\r
2694 #define CAN_F10R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
\r
2695 #define CAN_F10R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
\r
2696 #define CAN_F10R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
\r
2697 #define CAN_F10R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
\r
2698 #define CAN_F10R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
\r
2699 #define CAN_F10R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
\r
2700 #define CAN_F10R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
\r
2701 #define CAN_F10R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
\r
2702 #define CAN_F10R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
\r
2703 #define CAN_F10R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
\r
2704 #define CAN_F10R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
\r
2705 #define CAN_F10R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
\r
2706 #define CAN_F10R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
\r
2708 /******************* Bit definition for CAN_F11R2 register ******************/
\r
2709 #define CAN_F11R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
\r
2710 #define CAN_F11R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
\r
2711 #define CAN_F11R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
\r
2712 #define CAN_F11R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
\r
2713 #define CAN_F11R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
\r
2714 #define CAN_F11R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
\r
2715 #define CAN_F11R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
\r
2716 #define CAN_F11R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
\r
2717 #define CAN_F11R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
\r
2718 #define CAN_F11R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
\r
2719 #define CAN_F11R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
\r
2720 #define CAN_F11R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
\r
2721 #define CAN_F11R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
\r
2722 #define CAN_F11R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
\r
2723 #define CAN_F11R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
\r
2724 #define CAN_F11R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
\r
2725 #define CAN_F11R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
\r
2726 #define CAN_F11R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
\r
2727 #define CAN_F11R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
\r
2728 #define CAN_F11R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
\r
2729 #define CAN_F11R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
\r
2730 #define CAN_F11R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
\r
2731 #define CAN_F11R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
\r
2732 #define CAN_F11R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
\r
2733 #define CAN_F11R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
\r
2734 #define CAN_F11R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
\r
2735 #define CAN_F11R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
\r
2736 #define CAN_F11R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
\r
2737 #define CAN_F11R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
\r
2738 #define CAN_F11R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
\r
2739 #define CAN_F11R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
\r
2740 #define CAN_F11R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
\r
2742 /******************* Bit definition for CAN_F12R2 register ******************/
\r
2743 #define CAN_F12R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
\r
2744 #define CAN_F12R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
\r
2745 #define CAN_F12R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
\r
2746 #define CAN_F12R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
\r
2747 #define CAN_F12R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
\r
2748 #define CAN_F12R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
\r
2749 #define CAN_F12R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
\r
2750 #define CAN_F12R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
\r
2751 #define CAN_F12R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
\r
2752 #define CAN_F12R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
\r
2753 #define CAN_F12R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
\r
2754 #define CAN_F12R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
\r
2755 #define CAN_F12R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
\r
2756 #define CAN_F12R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
\r
2757 #define CAN_F12R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
\r
2758 #define CAN_F12R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
\r
2759 #define CAN_F12R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
\r
2760 #define CAN_F12R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
\r
2761 #define CAN_F12R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
\r
2762 #define CAN_F12R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
\r
2763 #define CAN_F12R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
\r
2764 #define CAN_F12R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
\r
2765 #define CAN_F12R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
\r
2766 #define CAN_F12R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
\r
2767 #define CAN_F12R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
\r
2768 #define CAN_F12R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
\r
2769 #define CAN_F12R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
\r
2770 #define CAN_F12R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
\r
2771 #define CAN_F12R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
\r
2772 #define CAN_F12R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
\r
2773 #define CAN_F12R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
\r
2774 #define CAN_F12R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
\r
2776 /******************* Bit definition for CAN_F13R2 register ******************/
\r
2777 #define CAN_F13R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
\r
2778 #define CAN_F13R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
\r
2779 #define CAN_F13R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
\r
2780 #define CAN_F13R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
\r
2781 #define CAN_F13R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
\r
2782 #define CAN_F13R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
\r
2783 #define CAN_F13R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
\r
2784 #define CAN_F13R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
\r
2785 #define CAN_F13R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
\r
2786 #define CAN_F13R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
\r
2787 #define CAN_F13R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
\r
2788 #define CAN_F13R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
\r
2789 #define CAN_F13R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
\r
2790 #define CAN_F13R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
\r
2791 #define CAN_F13R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
\r
2792 #define CAN_F13R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
\r
2793 #define CAN_F13R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
\r
2794 #define CAN_F13R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
\r
2795 #define CAN_F13R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
\r
2796 #define CAN_F13R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
\r
2797 #define CAN_F13R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
\r
2798 #define CAN_F13R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
\r
2799 #define CAN_F13R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
\r
2800 #define CAN_F13R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
\r
2801 #define CAN_F13R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
\r
2802 #define CAN_F13R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
\r
2803 #define CAN_F13R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
\r
2804 #define CAN_F13R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
\r
2805 #define CAN_F13R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
\r
2806 #define CAN_F13R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
\r
2807 #define CAN_F13R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
\r
2808 #define CAN_F13R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
\r
2810 /******************************************************************************/
\r
2812 /* CRC calculation unit */
\r
2814 /******************************************************************************/
\r
2815 /******************* Bit definition for CRC_DR register *********************/
\r
2816 #define CRC_DR_DR ((uint32_t)0xFFFFFFFF) /*!< Data register bits */
\r
2819 /******************* Bit definition for CRC_IDR register ********************/
\r
2820 #define CRC_IDR_IDR ((uint32_t)0xFF) /*!< General-purpose 8-bit data register bits */
\r
2823 /******************** Bit definition for CRC_CR register ********************/
\r
2824 #define CRC_CR_RESET ((uint32_t)0x01) /*!< RESET bit */
\r
2827 /******************************************************************************/
\r
2829 /* Digital to Analog Converter */
\r
2831 /******************************************************************************/
\r
2832 /******************** Bit definition for DAC_CR register ********************/
\r
2833 #define DAC_CR_EN1 ((uint32_t)0x00000001) /*!<DAC channel1 enable */
\r
2834 #define DAC_CR_BOFF1 ((uint32_t)0x00000002) /*!<DAC channel1 output buffer disable */
\r
2835 #define DAC_CR_TEN1 ((uint32_t)0x00000004) /*!<DAC channel1 Trigger enable */
\r
2837 #define DAC_CR_TSEL1 ((uint32_t)0x00000038) /*!<TSEL1[2:0] (DAC channel1 Trigger selection) */
\r
2838 #define DAC_CR_TSEL1_0 ((uint32_t)0x00000008) /*!<Bit 0 */
\r
2839 #define DAC_CR_TSEL1_1 ((uint32_t)0x00000010) /*!<Bit 1 */
\r
2840 #define DAC_CR_TSEL1_2 ((uint32_t)0x00000020) /*!<Bit 2 */
\r
2842 #define DAC_CR_WAVE1 ((uint32_t)0x000000C0) /*!<WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */
\r
2843 #define DAC_CR_WAVE1_0 ((uint32_t)0x00000040) /*!<Bit 0 */
\r
2844 #define DAC_CR_WAVE1_1 ((uint32_t)0x00000080) /*!<Bit 1 */
\r
2846 #define DAC_CR_MAMP1 ((uint32_t)0x00000F00) /*!<MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */
\r
2847 #define DAC_CR_MAMP1_0 ((uint32_t)0x00000100) /*!<Bit 0 */
\r
2848 #define DAC_CR_MAMP1_1 ((uint32_t)0x00000200) /*!<Bit 1 */
\r
2849 #define DAC_CR_MAMP1_2 ((uint32_t)0x00000400) /*!<Bit 2 */
\r
2850 #define DAC_CR_MAMP1_3 ((uint32_t)0x00000800) /*!<Bit 3 */
\r
2852 #define DAC_CR_DMAEN1 ((uint32_t)0x00001000) /*!<DAC channel1 DMA enable */
\r
2853 #define DAC_CR_EN2 ((uint32_t)0x00010000) /*!<DAC channel2 enable */
\r
2854 #define DAC_CR_BOFF2 ((uint32_t)0x00020000) /*!<DAC channel2 output buffer disable */
\r
2855 #define DAC_CR_TEN2 ((uint32_t)0x00040000) /*!<DAC channel2 Trigger enable */
\r
2857 #define DAC_CR_TSEL2 ((uint32_t)0x00380000) /*!<TSEL2[2:0] (DAC channel2 Trigger selection) */
\r
2858 #define DAC_CR_TSEL2_0 ((uint32_t)0x00080000) /*!<Bit 0 */
\r
2859 #define DAC_CR_TSEL2_1 ((uint32_t)0x00100000) /*!<Bit 1 */
\r
2860 #define DAC_CR_TSEL2_2 ((uint32_t)0x00200000) /*!<Bit 2 */
\r
2862 #define DAC_CR_WAVE2 ((uint32_t)0x00C00000) /*!<WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */
\r
2863 #define DAC_CR_WAVE2_0 ((uint32_t)0x00400000) /*!<Bit 0 */
\r
2864 #define DAC_CR_WAVE2_1 ((uint32_t)0x00800000) /*!<Bit 1 */
\r
2866 #define DAC_CR_MAMP2 ((uint32_t)0x0F000000) /*!<MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */
\r
2867 #define DAC_CR_MAMP2_0 ((uint32_t)0x01000000) /*!<Bit 0 */
\r
2868 #define DAC_CR_MAMP2_1 ((uint32_t)0x02000000) /*!<Bit 1 */
\r
2869 #define DAC_CR_MAMP2_2 ((uint32_t)0x04000000) /*!<Bit 2 */
\r
2870 #define DAC_CR_MAMP2_3 ((uint32_t)0x08000000) /*!<Bit 3 */
\r
2872 #define DAC_CR_DMAEN2 ((uint32_t)0x10000000) /*!<DAC channel2 DMA enabled */
\r
2874 /***************** Bit definition for DAC_SWTRIGR register ******************/
\r
2875 #define DAC_SWTRIGR_SWTRIG1 ((uint32_t)0x01) /*!<DAC channel1 software trigger */
\r
2876 #define DAC_SWTRIGR_SWTRIG2 ((uint32_t)0x02) /*!<DAC channel2 software trigger */
\r
2878 /***************** Bit definition for DAC_DHR12R1 register ******************/
\r
2879 #define DAC_DHR12R1_DACC1DHR ((uint32_t)0x0FFF) /*!<DAC channel1 12-bit Right aligned data */
\r
2881 /***************** Bit definition for DAC_DHR12L1 register ******************/
\r
2882 #define DAC_DHR12L1_DACC1DHR ((uint32_t)0xFFF0) /*!<DAC channel1 12-bit Left aligned data */
\r
2884 /****************** Bit definition for DAC_DHR8R1 register ******************/
\r
2885 #define DAC_DHR8R1_DACC1DHR ((uint32_t)0xFF) /*!<DAC channel1 8-bit Right aligned data */
\r
2887 /***************** Bit definition for DAC_DHR12R2 register ******************/
\r
2888 #define DAC_DHR12R2_DACC2DHR ((uint32_t)0x0FFF) /*!<DAC channel2 12-bit Right aligned data */
\r
2890 /***************** Bit definition for DAC_DHR12L2 register ******************/
\r
2891 #define DAC_DHR12L2_DACC2DHR ((uint32_t)0xFFF0) /*!<DAC channel2 12-bit Left aligned data */
\r
2893 /****************** Bit definition for DAC_DHR8R2 register ******************/
\r
2894 #define DAC_DHR8R2_DACC2DHR ((uint32_t)0xFF) /*!<DAC channel2 8-bit Right aligned data */
\r
2896 /***************** Bit definition for DAC_DHR12RD register ******************/
\r
2897 #define DAC_DHR12RD_DACC1DHR ((uint32_t)0x00000FFF) /*!<DAC channel1 12-bit Right aligned data */
\r
2898 #define DAC_DHR12RD_DACC2DHR ((uint32_t)0x0FFF0000) /*!<DAC channel2 12-bit Right aligned data */
\r
2900 /***************** Bit definition for DAC_DHR12LD register ******************/
\r
2901 #define DAC_DHR12LD_DACC1DHR ((uint32_t)0x0000FFF0) /*!<DAC channel1 12-bit Left aligned data */
\r
2902 #define DAC_DHR12LD_DACC2DHR ((uint32_t)0xFFF00000) /*!<DAC channel2 12-bit Left aligned data */
\r
2904 /****************** Bit definition for DAC_DHR8RD register ******************/
\r
2905 #define DAC_DHR8RD_DACC1DHR ((uint32_t)0x00FF) /*!<DAC channel1 8-bit Right aligned data */
\r
2906 #define DAC_DHR8RD_DACC2DHR ((uint32_t)0xFF00) /*!<DAC channel2 8-bit Right aligned data */
\r
2908 /******************* Bit definition for DAC_DOR1 register *******************/
\r
2909 #define DAC_DOR1_DACC1DOR ((uint32_t)0x0FFF) /*!<DAC channel1 data output */
\r
2911 /******************* Bit definition for DAC_DOR2 register *******************/
\r
2912 #define DAC_DOR2_DACC2DOR ((uint32_t)0x0FFF) /*!<DAC channel2 data output */
\r
2914 /******************** Bit definition for DAC_SR register ********************/
\r
2915 #define DAC_SR_DMAUDR1 ((uint32_t)0x00002000) /*!<DAC channel1 DMA underrun flag */
\r
2916 #define DAC_SR_DMAUDR2 ((uint32_t)0x20000000) /*!<DAC channel2 DMA underrun flag */
\r
2918 /******************************************************************************/
\r
2922 /******************************************************************************/
\r
2924 /******************************************************************************/
\r
2928 /******************************************************************************/
\r
2929 /******************** Bits definition for DCMI_CR register ******************/
\r
2930 #define DCMI_CR_CAPTURE ((uint32_t)0x00000001)
\r
2931 #define DCMI_CR_CM ((uint32_t)0x00000002)
\r
2932 #define DCMI_CR_CROP ((uint32_t)0x00000004)
\r
2933 #define DCMI_CR_JPEG ((uint32_t)0x00000008)
\r
2934 #define DCMI_CR_ESS ((uint32_t)0x00000010)
\r
2935 #define DCMI_CR_PCKPOL ((uint32_t)0x00000020)
\r
2936 #define DCMI_CR_HSPOL ((uint32_t)0x00000040)
\r
2937 #define DCMI_CR_VSPOL ((uint32_t)0x00000080)
\r
2938 #define DCMI_CR_FCRC_0 ((uint32_t)0x00000100)
\r
2939 #define DCMI_CR_FCRC_1 ((uint32_t)0x00000200)
\r
2940 #define DCMI_CR_EDM_0 ((uint32_t)0x00000400)
\r
2941 #define DCMI_CR_EDM_1 ((uint32_t)0x00000800)
\r
2942 #define DCMI_CR_CRE ((uint32_t)0x00001000)
\r
2943 #define DCMI_CR_ENABLE ((uint32_t)0x00004000)
\r
2945 /******************** Bits definition for DCMI_SR register ******************/
\r
2946 #define DCMI_SR_HSYNC ((uint32_t)0x00000001)
\r
2947 #define DCMI_SR_VSYNC ((uint32_t)0x00000002)
\r
2948 #define DCMI_SR_FNE ((uint32_t)0x00000004)
\r
2950 /******************** Bits definition for DCMI_RISR register ****************/
\r
2951 #define DCMI_RISR_FRAME_RIS ((uint32_t)0x00000001)
\r
2952 #define DCMI_RISR_OVF_RIS ((uint32_t)0x00000002)
\r
2953 #define DCMI_RISR_ERR_RIS ((uint32_t)0x00000004)
\r
2954 #define DCMI_RISR_VSYNC_RIS ((uint32_t)0x00000008)
\r
2955 #define DCMI_RISR_LINE_RIS ((uint32_t)0x00000010)
\r
2957 /******************** Bits definition for DCMI_IER register *****************/
\r
2958 #define DCMI_IER_FRAME_IE ((uint32_t)0x00000001)
\r
2959 #define DCMI_IER_OVF_IE ((uint32_t)0x00000002)
\r
2960 #define DCMI_IER_ERR_IE ((uint32_t)0x00000004)
\r
2961 #define DCMI_IER_VSYNC_IE ((uint32_t)0x00000008)
\r
2962 #define DCMI_IER_LINE_IE ((uint32_t)0x00000010)
\r
2964 /******************** Bits definition for DCMI_MISR register ****************/
\r
2965 #define DCMI_MISR_FRAME_MIS ((uint32_t)0x00000001)
\r
2966 #define DCMI_MISR_OVF_MIS ((uint32_t)0x00000002)
\r
2967 #define DCMI_MISR_ERR_MIS ((uint32_t)0x00000004)
\r
2968 #define DCMI_MISR_VSYNC_MIS ((uint32_t)0x00000008)
\r
2969 #define DCMI_MISR_LINE_MIS ((uint32_t)0x00000010)
\r
2971 /******************** Bits definition for DCMI_ICR register *****************/
\r
2972 #define DCMI_ICR_FRAME_ISC ((uint32_t)0x00000001)
\r
2973 #define DCMI_ICR_OVF_ISC ((uint32_t)0x00000002)
\r
2974 #define DCMI_ICR_ERR_ISC ((uint32_t)0x00000004)
\r
2975 #define DCMI_ICR_VSYNC_ISC ((uint32_t)0x00000008)
\r
2976 #define DCMI_ICR_LINE_ISC ((uint32_t)0x00000010)
\r
2978 /******************************************************************************/
\r
2980 /* DMA Controller */
\r
2982 /******************************************************************************/
\r
2983 /******************** Bits definition for DMA_SxCR register *****************/
\r
2984 #define DMA_SxCR_CHSEL ((uint32_t)0x0E000000)
\r
2985 #define DMA_SxCR_CHSEL_0 ((uint32_t)0x02000000)
\r
2986 #define DMA_SxCR_CHSEL_1 ((uint32_t)0x04000000)
\r
2987 #define DMA_SxCR_CHSEL_2 ((uint32_t)0x08000000)
\r
2988 #define DMA_SxCR_MBURST ((uint32_t)0x01800000)
\r
2989 #define DMA_SxCR_MBURST_0 ((uint32_t)0x00800000)
\r
2990 #define DMA_SxCR_MBURST_1 ((uint32_t)0x01000000)
\r
2991 #define DMA_SxCR_PBURST ((uint32_t)0x00600000)
\r
2992 #define DMA_SxCR_PBURST_0 ((uint32_t)0x00200000)
\r
2993 #define DMA_SxCR_PBURST_1 ((uint32_t)0x00400000)
\r
2994 #define DMA_SxCR_ACK ((uint32_t)0x00100000)
\r
2995 #define DMA_SxCR_CT ((uint32_t)0x00080000)
\r
2996 #define DMA_SxCR_DBM ((uint32_t)0x00040000)
\r
2997 #define DMA_SxCR_PL ((uint32_t)0x00030000)
\r
2998 #define DMA_SxCR_PL_0 ((uint32_t)0x00010000)
\r
2999 #define DMA_SxCR_PL_1 ((uint32_t)0x00020000)
\r
3000 #define DMA_SxCR_PINCOS ((uint32_t)0x00008000)
\r
3001 #define DMA_SxCR_MSIZE ((uint32_t)0x00006000)
\r
3002 #define DMA_SxCR_MSIZE_0 ((uint32_t)0x00002000)
\r
3003 #define DMA_SxCR_MSIZE_1 ((uint32_t)0x00004000)
\r
3004 #define DMA_SxCR_PSIZE ((uint32_t)0x00001800)
\r
3005 #define DMA_SxCR_PSIZE_0 ((uint32_t)0x00000800)
\r
3006 #define DMA_SxCR_PSIZE_1 ((uint32_t)0x00001000)
\r
3007 #define DMA_SxCR_MINC ((uint32_t)0x00000400)
\r
3008 #define DMA_SxCR_PINC ((uint32_t)0x00000200)
\r
3009 #define DMA_SxCR_CIRC ((uint32_t)0x00000100)
\r
3010 #define DMA_SxCR_DIR ((uint32_t)0x000000C0)
\r
3011 #define DMA_SxCR_DIR_0 ((uint32_t)0x00000040)
\r
3012 #define DMA_SxCR_DIR_1 ((uint32_t)0x00000080)
\r
3013 #define DMA_SxCR_PFCTRL ((uint32_t)0x00000020)
\r
3014 #define DMA_SxCR_TCIE ((uint32_t)0x00000010)
\r
3015 #define DMA_SxCR_HTIE ((uint32_t)0x00000008)
\r
3016 #define DMA_SxCR_TEIE ((uint32_t)0x00000004)
\r
3017 #define DMA_SxCR_DMEIE ((uint32_t)0x00000002)
\r
3018 #define DMA_SxCR_EN ((uint32_t)0x00000001)
\r
3020 /******************** Bits definition for DMA_SxCNDTR register **************/
\r
3021 #define DMA_SxNDT ((uint32_t)0x0000FFFF)
\r
3022 #define DMA_SxNDT_0 ((uint32_t)0x00000001)
\r
3023 #define DMA_SxNDT_1 ((uint32_t)0x00000002)
\r
3024 #define DMA_SxNDT_2 ((uint32_t)0x00000004)
\r
3025 #define DMA_SxNDT_3 ((uint32_t)0x00000008)
\r
3026 #define DMA_SxNDT_4 ((uint32_t)0x00000010)
\r
3027 #define DMA_SxNDT_5 ((uint32_t)0x00000020)
\r
3028 #define DMA_SxNDT_6 ((uint32_t)0x00000040)
\r
3029 #define DMA_SxNDT_7 ((uint32_t)0x00000080)
\r
3030 #define DMA_SxNDT_8 ((uint32_t)0x00000100)
\r
3031 #define DMA_SxNDT_9 ((uint32_t)0x00000200)
\r
3032 #define DMA_SxNDT_10 ((uint32_t)0x00000400)
\r
3033 #define DMA_SxNDT_11 ((uint32_t)0x00000800)
\r
3034 #define DMA_SxNDT_12 ((uint32_t)0x00001000)
\r
3035 #define DMA_SxNDT_13 ((uint32_t)0x00002000)
\r
3036 #define DMA_SxNDT_14 ((uint32_t)0x00004000)
\r
3037 #define DMA_SxNDT_15 ((uint32_t)0x00008000)
\r
3039 /******************** Bits definition for DMA_SxFCR register ****************/
\r
3040 #define DMA_SxFCR_FEIE ((uint32_t)0x00000080)
\r
3041 #define DMA_SxFCR_FS ((uint32_t)0x00000038)
\r
3042 #define DMA_SxFCR_FS_0 ((uint32_t)0x00000008)
\r
3043 #define DMA_SxFCR_FS_1 ((uint32_t)0x00000010)
\r
3044 #define DMA_SxFCR_FS_2 ((uint32_t)0x00000020)
\r
3045 #define DMA_SxFCR_DMDIS ((uint32_t)0x00000004)
\r
3046 #define DMA_SxFCR_FTH ((uint32_t)0x00000003)
\r
3047 #define DMA_SxFCR_FTH_0 ((uint32_t)0x00000001)
\r
3048 #define DMA_SxFCR_FTH_1 ((uint32_t)0x00000002)
\r
3050 /******************** Bits definition for DMA_LISR register *****************/
\r
3051 #define DMA_LISR_TCIF3 ((uint32_t)0x08000000)
\r
3052 #define DMA_LISR_HTIF3 ((uint32_t)0x04000000)
\r
3053 #define DMA_LISR_TEIF3 ((uint32_t)0x02000000)
\r
3054 #define DMA_LISR_DMEIF3 ((uint32_t)0x01000000)
\r
3055 #define DMA_LISR_FEIF3 ((uint32_t)0x00400000)
\r
3056 #define DMA_LISR_TCIF2 ((uint32_t)0x00200000)
\r
3057 #define DMA_LISR_HTIF2 ((uint32_t)0x00100000)
\r
3058 #define DMA_LISR_TEIF2 ((uint32_t)0x00080000)
\r
3059 #define DMA_LISR_DMEIF2 ((uint32_t)0x00040000)
\r
3060 #define DMA_LISR_FEIF2 ((uint32_t)0x00010000)
\r
3061 #define DMA_LISR_TCIF1 ((uint32_t)0x00000800)
\r
3062 #define DMA_LISR_HTIF1 ((uint32_t)0x00000400)
\r
3063 #define DMA_LISR_TEIF1 ((uint32_t)0x00000200)
\r
3064 #define DMA_LISR_DMEIF1 ((uint32_t)0x00000100)
\r
3065 #define DMA_LISR_FEIF1 ((uint32_t)0x00000040)
\r
3066 #define DMA_LISR_TCIF0 ((uint32_t)0x00000020)
\r
3067 #define DMA_LISR_HTIF0 ((uint32_t)0x00000010)
\r
3068 #define DMA_LISR_TEIF0 ((uint32_t)0x00000008)
\r
3069 #define DMA_LISR_DMEIF0 ((uint32_t)0x00000004)
\r
3070 #define DMA_LISR_FEIF0 ((uint32_t)0x00000001)
\r
3072 /******************** Bits definition for DMA_HISR register *****************/
\r
3073 #define DMA_HISR_TCIF7 ((uint32_t)0x08000000)
\r
3074 #define DMA_HISR_HTIF7 ((uint32_t)0x04000000)
\r
3075 #define DMA_HISR_TEIF7 ((uint32_t)0x02000000)
\r
3076 #define DMA_HISR_DMEIF7 ((uint32_t)0x01000000)
\r
3077 #define DMA_HISR_FEIF7 ((uint32_t)0x00400000)
\r
3078 #define DMA_HISR_TCIF6 ((uint32_t)0x00200000)
\r
3079 #define DMA_HISR_HTIF6 ((uint32_t)0x00100000)
\r
3080 #define DMA_HISR_TEIF6 ((uint32_t)0x00080000)
\r
3081 #define DMA_HISR_DMEIF6 ((uint32_t)0x00040000)
\r
3082 #define DMA_HISR_FEIF6 ((uint32_t)0x00010000)
\r
3083 #define DMA_HISR_TCIF5 ((uint32_t)0x00000800)
\r
3084 #define DMA_HISR_HTIF5 ((uint32_t)0x00000400)
\r
3085 #define DMA_HISR_TEIF5 ((uint32_t)0x00000200)
\r
3086 #define DMA_HISR_DMEIF5 ((uint32_t)0x00000100)
\r
3087 #define DMA_HISR_FEIF5 ((uint32_t)0x00000040)
\r
3088 #define DMA_HISR_TCIF4 ((uint32_t)0x00000020)
\r
3089 #define DMA_HISR_HTIF4 ((uint32_t)0x00000010)
\r
3090 #define DMA_HISR_TEIF4 ((uint32_t)0x00000008)
\r
3091 #define DMA_HISR_DMEIF4 ((uint32_t)0x00000004)
\r
3092 #define DMA_HISR_FEIF4 ((uint32_t)0x00000001)
\r
3094 /******************** Bits definition for DMA_LIFCR register ****************/
\r
3095 #define DMA_LIFCR_CTCIF3 ((uint32_t)0x08000000)
\r
3096 #define DMA_LIFCR_CHTIF3 ((uint32_t)0x04000000)
\r
3097 #define DMA_LIFCR_CTEIF3 ((uint32_t)0x02000000)
\r
3098 #define DMA_LIFCR_CDMEIF3 ((uint32_t)0x01000000)
\r
3099 #define DMA_LIFCR_CFEIF3 ((uint32_t)0x00400000)
\r
3100 #define DMA_LIFCR_CTCIF2 ((uint32_t)0x00200000)
\r
3101 #define DMA_LIFCR_CHTIF2 ((uint32_t)0x00100000)
\r
3102 #define DMA_LIFCR_CTEIF2 ((uint32_t)0x00080000)
\r
3103 #define DMA_LIFCR_CDMEIF2 ((uint32_t)0x00040000)
\r
3104 #define DMA_LIFCR_CFEIF2 ((uint32_t)0x00010000)
\r
3105 #define DMA_LIFCR_CTCIF1 ((uint32_t)0x00000800)
\r
3106 #define DMA_LIFCR_CHTIF1 ((uint32_t)0x00000400)
\r
3107 #define DMA_LIFCR_CTEIF1 ((uint32_t)0x00000200)
\r
3108 #define DMA_LIFCR_CDMEIF1 ((uint32_t)0x00000100)
\r
3109 #define DMA_LIFCR_CFEIF1 ((uint32_t)0x00000040)
\r
3110 #define DMA_LIFCR_CTCIF0 ((uint32_t)0x00000020)
\r
3111 #define DMA_LIFCR_CHTIF0 ((uint32_t)0x00000010)
\r
3112 #define DMA_LIFCR_CTEIF0 ((uint32_t)0x00000008)
\r
3113 #define DMA_LIFCR_CDMEIF0 ((uint32_t)0x00000004)
\r
3114 #define DMA_LIFCR_CFEIF0 ((uint32_t)0x00000001)
\r
3116 /******************** Bits definition for DMA_HIFCR register ****************/
\r
3117 #define DMA_HIFCR_CTCIF7 ((uint32_t)0x08000000)
\r
3118 #define DMA_HIFCR_CHTIF7 ((uint32_t)0x04000000)
\r
3119 #define DMA_HIFCR_CTEIF7 ((uint32_t)0x02000000)
\r
3120 #define DMA_HIFCR_CDMEIF7 ((uint32_t)0x01000000)
\r
3121 #define DMA_HIFCR_CFEIF7 ((uint32_t)0x00400000)
\r
3122 #define DMA_HIFCR_CTCIF6 ((uint32_t)0x00200000)
\r
3123 #define DMA_HIFCR_CHTIF6 ((uint32_t)0x00100000)
\r
3124 #define DMA_HIFCR_CTEIF6 ((uint32_t)0x00080000)
\r
3125 #define DMA_HIFCR_CDMEIF6 ((uint32_t)0x00040000)
\r
3126 #define DMA_HIFCR_CFEIF6 ((uint32_t)0x00010000)
\r
3127 #define DMA_HIFCR_CTCIF5 ((uint32_t)0x00000800)
\r
3128 #define DMA_HIFCR_CHTIF5 ((uint32_t)0x00000400)
\r
3129 #define DMA_HIFCR_CTEIF5 ((uint32_t)0x00000200)
\r
3130 #define DMA_HIFCR_CDMEIF5 ((uint32_t)0x00000100)
\r
3131 #define DMA_HIFCR_CFEIF5 ((uint32_t)0x00000040)
\r
3132 #define DMA_HIFCR_CTCIF4 ((uint32_t)0x00000020)
\r
3133 #define DMA_HIFCR_CHTIF4 ((uint32_t)0x00000010)
\r
3134 #define DMA_HIFCR_CTEIF4 ((uint32_t)0x00000008)
\r
3135 #define DMA_HIFCR_CDMEIF4 ((uint32_t)0x00000004)
\r
3136 #define DMA_HIFCR_CFEIF4 ((uint32_t)0x00000001)
\r
3139 /******************************************************************************/
\r
3141 /* External Interrupt/Event Controller */
\r
3143 /******************************************************************************/
\r
3144 /******************* Bit definition for EXTI_IMR register *******************/
\r
3145 #define EXTI_IMR_MR0 ((uint32_t)0x00000001) /*!< Interrupt Mask on line 0 */
\r
3146 #define EXTI_IMR_MR1 ((uint32_t)0x00000002) /*!< Interrupt Mask on line 1 */
\r
3147 #define EXTI_IMR_MR2 ((uint32_t)0x00000004) /*!< Interrupt Mask on line 2 */
\r
3148 #define EXTI_IMR_MR3 ((uint32_t)0x00000008) /*!< Interrupt Mask on line 3 */
\r
3149 #define EXTI_IMR_MR4 ((uint32_t)0x00000010) /*!< Interrupt Mask on line 4 */
\r
3150 #define EXTI_IMR_MR5 ((uint32_t)0x00000020) /*!< Interrupt Mask on line 5 */
\r
3151 #define EXTI_IMR_MR6 ((uint32_t)0x00000040) /*!< Interrupt Mask on line 6 */
\r
3152 #define EXTI_IMR_MR7 ((uint32_t)0x00000080) /*!< Interrupt Mask on line 7 */
\r
3153 #define EXTI_IMR_MR8 ((uint32_t)0x00000100) /*!< Interrupt Mask on line 8 */
\r
3154 #define EXTI_IMR_MR9 ((uint32_t)0x00000200) /*!< Interrupt Mask on line 9 */
\r
3155 #define EXTI_IMR_MR10 ((uint32_t)0x00000400) /*!< Interrupt Mask on line 10 */
\r
3156 #define EXTI_IMR_MR11 ((uint32_t)0x00000800) /*!< Interrupt Mask on line 11 */
\r
3157 #define EXTI_IMR_MR12 ((uint32_t)0x00001000) /*!< Interrupt Mask on line 12 */
\r
3158 #define EXTI_IMR_MR13 ((uint32_t)0x00002000) /*!< Interrupt Mask on line 13 */
\r
3159 #define EXTI_IMR_MR14 ((uint32_t)0x00004000) /*!< Interrupt Mask on line 14 */
\r
3160 #define EXTI_IMR_MR15 ((uint32_t)0x00008000) /*!< Interrupt Mask on line 15 */
\r
3161 #define EXTI_IMR_MR16 ((uint32_t)0x00010000) /*!< Interrupt Mask on line 16 */
\r
3162 #define EXTI_IMR_MR17 ((uint32_t)0x00020000) /*!< Interrupt Mask on line 17 */
\r
3163 #define EXTI_IMR_MR18 ((uint32_t)0x00040000) /*!< Interrupt Mask on line 18 */
\r
3164 #define EXTI_IMR_MR19 ((uint32_t)0x00080000) /*!< Interrupt Mask on line 19 */
\r
3166 /******************* Bit definition for EXTI_EMR register *******************/
\r
3167 #define EXTI_EMR_MR0 ((uint32_t)0x00000001) /*!< Event Mask on line 0 */
\r
3168 #define EXTI_EMR_MR1 ((uint32_t)0x00000002) /*!< Event Mask on line 1 */
\r
3169 #define EXTI_EMR_MR2 ((uint32_t)0x00000004) /*!< Event Mask on line 2 */
\r
3170 #define EXTI_EMR_MR3 ((uint32_t)0x00000008) /*!< Event Mask on line 3 */
\r
3171 #define EXTI_EMR_MR4 ((uint32_t)0x00000010) /*!< Event Mask on line 4 */
\r
3172 #define EXTI_EMR_MR5 ((uint32_t)0x00000020) /*!< Event Mask on line 5 */
\r
3173 #define EXTI_EMR_MR6 ((uint32_t)0x00000040) /*!< Event Mask on line 6 */
\r
3174 #define EXTI_EMR_MR7 ((uint32_t)0x00000080) /*!< Event Mask on line 7 */
\r
3175 #define EXTI_EMR_MR8 ((uint32_t)0x00000100) /*!< Event Mask on line 8 */
\r
3176 #define EXTI_EMR_MR9 ((uint32_t)0x00000200) /*!< Event Mask on line 9 */
\r
3177 #define EXTI_EMR_MR10 ((uint32_t)0x00000400) /*!< Event Mask on line 10 */
\r
3178 #define EXTI_EMR_MR11 ((uint32_t)0x00000800) /*!< Event Mask on line 11 */
\r
3179 #define EXTI_EMR_MR12 ((uint32_t)0x00001000) /*!< Event Mask on line 12 */
\r
3180 #define EXTI_EMR_MR13 ((uint32_t)0x00002000) /*!< Event Mask on line 13 */
\r
3181 #define EXTI_EMR_MR14 ((uint32_t)0x00004000) /*!< Event Mask on line 14 */
\r
3182 #define EXTI_EMR_MR15 ((uint32_t)0x00008000) /*!< Event Mask on line 15 */
\r
3183 #define EXTI_EMR_MR16 ((uint32_t)0x00010000) /*!< Event Mask on line 16 */
\r
3184 #define EXTI_EMR_MR17 ((uint32_t)0x00020000) /*!< Event Mask on line 17 */
\r
3185 #define EXTI_EMR_MR18 ((uint32_t)0x00040000) /*!< Event Mask on line 18 */
\r
3186 #define EXTI_EMR_MR19 ((uint32_t)0x00080000) /*!< Event Mask on line 19 */
\r
3188 /****************** Bit definition for EXTI_RTSR register *******************/
\r
3189 #define EXTI_RTSR_TR0 ((uint32_t)0x00000001) /*!< Rising trigger event configuration bit of line 0 */
\r
3190 #define EXTI_RTSR_TR1 ((uint32_t)0x00000002) /*!< Rising trigger event configuration bit of line 1 */
\r
3191 #define EXTI_RTSR_TR2 ((uint32_t)0x00000004) /*!< Rising trigger event configuration bit of line 2 */
\r
3192 #define EXTI_RTSR_TR3 ((uint32_t)0x00000008) /*!< Rising trigger event configuration bit of line 3 */
\r
3193 #define EXTI_RTSR_TR4 ((uint32_t)0x00000010) /*!< Rising trigger event configuration bit of line 4 */
\r
3194 #define EXTI_RTSR_TR5 ((uint32_t)0x00000020) /*!< Rising trigger event configuration bit of line 5 */
\r
3195 #define EXTI_RTSR_TR6 ((uint32_t)0x00000040) /*!< Rising trigger event configuration bit of line 6 */
\r
3196 #define EXTI_RTSR_TR7 ((uint32_t)0x00000080) /*!< Rising trigger event configuration bit of line 7 */
\r
3197 #define EXTI_RTSR_TR8 ((uint32_t)0x00000100) /*!< Rising trigger event configuration bit of line 8 */
\r
3198 #define EXTI_RTSR_TR9 ((uint32_t)0x00000200) /*!< Rising trigger event configuration bit of line 9 */
\r
3199 #define EXTI_RTSR_TR10 ((uint32_t)0x00000400) /*!< Rising trigger event configuration bit of line 10 */
\r
3200 #define EXTI_RTSR_TR11 ((uint32_t)0x00000800) /*!< Rising trigger event configuration bit of line 11 */
\r
3201 #define EXTI_RTSR_TR12 ((uint32_t)0x00001000) /*!< Rising trigger event configuration bit of line 12 */
\r
3202 #define EXTI_RTSR_TR13 ((uint32_t)0x00002000) /*!< Rising trigger event configuration bit of line 13 */
\r
3203 #define EXTI_RTSR_TR14 ((uint32_t)0x00004000) /*!< Rising trigger event configuration bit of line 14 */
\r
3204 #define EXTI_RTSR_TR15 ((uint32_t)0x00008000) /*!< Rising trigger event configuration bit of line 15 */
\r
3205 #define EXTI_RTSR_TR16 ((uint32_t)0x00010000) /*!< Rising trigger event configuration bit of line 16 */
\r
3206 #define EXTI_RTSR_TR17 ((uint32_t)0x00020000) /*!< Rising trigger event configuration bit of line 17 */
\r
3207 #define EXTI_RTSR_TR18 ((uint32_t)0x00040000) /*!< Rising trigger event configuration bit of line 18 */
\r
3208 #define EXTI_RTSR_TR19 ((uint32_t)0x00080000) /*!< Rising trigger event configuration bit of line 19 */
\r
3210 /****************** Bit definition for EXTI_FTSR register *******************/
\r
3211 #define EXTI_FTSR_TR0 ((uint32_t)0x00000001) /*!< Falling trigger event configuration bit of line 0 */
\r
3212 #define EXTI_FTSR_TR1 ((uint32_t)0x00000002) /*!< Falling trigger event configuration bit of line 1 */
\r
3213 #define EXTI_FTSR_TR2 ((uint32_t)0x00000004) /*!< Falling trigger event configuration bit of line 2 */
\r
3214 #define EXTI_FTSR_TR3 ((uint32_t)0x00000008) /*!< Falling trigger event configuration bit of line 3 */
\r
3215 #define EXTI_FTSR_TR4 ((uint32_t)0x00000010) /*!< Falling trigger event configuration bit of line 4 */
\r
3216 #define EXTI_FTSR_TR5 ((uint32_t)0x00000020) /*!< Falling trigger event configuration bit of line 5 */
\r
3217 #define EXTI_FTSR_TR6 ((uint32_t)0x00000040) /*!< Falling trigger event configuration bit of line 6 */
\r
3218 #define EXTI_FTSR_TR7 ((uint32_t)0x00000080) /*!< Falling trigger event configuration bit of line 7 */
\r
3219 #define EXTI_FTSR_TR8 ((uint32_t)0x00000100) /*!< Falling trigger event configuration bit of line 8 */
\r
3220 #define EXTI_FTSR_TR9 ((uint32_t)0x00000200) /*!< Falling trigger event configuration bit of line 9 */
\r
3221 #define EXTI_FTSR_TR10 ((uint32_t)0x00000400) /*!< Falling trigger event configuration bit of line 10 */
\r
3222 #define EXTI_FTSR_TR11 ((uint32_t)0x00000800) /*!< Falling trigger event configuration bit of line 11 */
\r
3223 #define EXTI_FTSR_TR12 ((uint32_t)0x00001000) /*!< Falling trigger event configuration bit of line 12 */
\r
3224 #define EXTI_FTSR_TR13 ((uint32_t)0x00002000) /*!< Falling trigger event configuration bit of line 13 */
\r
3225 #define EXTI_FTSR_TR14 ((uint32_t)0x00004000) /*!< Falling trigger event configuration bit of line 14 */
\r
3226 #define EXTI_FTSR_TR15 ((uint32_t)0x00008000) /*!< Falling trigger event configuration bit of line 15 */
\r
3227 #define EXTI_FTSR_TR16 ((uint32_t)0x00010000) /*!< Falling trigger event configuration bit of line 16 */
\r
3228 #define EXTI_FTSR_TR17 ((uint32_t)0x00020000) /*!< Falling trigger event configuration bit of line 17 */
\r
3229 #define EXTI_FTSR_TR18 ((uint32_t)0x00040000) /*!< Falling trigger event configuration bit of line 18 */
\r
3230 #define EXTI_FTSR_TR19 ((uint32_t)0x00080000) /*!< Falling trigger event configuration bit of line 19 */
\r
3232 /****************** Bit definition for EXTI_SWIER register ******************/
\r
3233 #define EXTI_SWIER_SWIER0 ((uint32_t)0x00000001) /*!< Software Interrupt on line 0 */
\r
3234 #define EXTI_SWIER_SWIER1 ((uint32_t)0x00000002) /*!< Software Interrupt on line 1 */
\r
3235 #define EXTI_SWIER_SWIER2 ((uint32_t)0x00000004) /*!< Software Interrupt on line 2 */
\r
3236 #define EXTI_SWIER_SWIER3 ((uint32_t)0x00000008) /*!< Software Interrupt on line 3 */
\r
3237 #define EXTI_SWIER_SWIER4 ((uint32_t)0x00000010) /*!< Software Interrupt on line 4 */
\r
3238 #define EXTI_SWIER_SWIER5 ((uint32_t)0x00000020) /*!< Software Interrupt on line 5 */
\r
3239 #define EXTI_SWIER_SWIER6 ((uint32_t)0x00000040) /*!< Software Interrupt on line 6 */
\r
3240 #define EXTI_SWIER_SWIER7 ((uint32_t)0x00000080) /*!< Software Interrupt on line 7 */
\r
3241 #define EXTI_SWIER_SWIER8 ((uint32_t)0x00000100) /*!< Software Interrupt on line 8 */
\r
3242 #define EXTI_SWIER_SWIER9 ((uint32_t)0x00000200) /*!< Software Interrupt on line 9 */
\r
3243 #define EXTI_SWIER_SWIER10 ((uint32_t)0x00000400) /*!< Software Interrupt on line 10 */
\r
3244 #define EXTI_SWIER_SWIER11 ((uint32_t)0x00000800) /*!< Software Interrupt on line 11 */
\r
3245 #define EXTI_SWIER_SWIER12 ((uint32_t)0x00001000) /*!< Software Interrupt on line 12 */
\r
3246 #define EXTI_SWIER_SWIER13 ((uint32_t)0x00002000) /*!< Software Interrupt on line 13 */
\r
3247 #define EXTI_SWIER_SWIER14 ((uint32_t)0x00004000) /*!< Software Interrupt on line 14 */
\r
3248 #define EXTI_SWIER_SWIER15 ((uint32_t)0x00008000) /*!< Software Interrupt on line 15 */
\r
3249 #define EXTI_SWIER_SWIER16 ((uint32_t)0x00010000) /*!< Software Interrupt on line 16 */
\r
3250 #define EXTI_SWIER_SWIER17 ((uint32_t)0x00020000) /*!< Software Interrupt on line 17 */
\r
3251 #define EXTI_SWIER_SWIER18 ((uint32_t)0x00040000) /*!< Software Interrupt on line 18 */
\r
3252 #define EXTI_SWIER_SWIER19 ((uint32_t)0x00080000) /*!< Software Interrupt on line 19 */
\r
3254 /******************* Bit definition for EXTI_PR register ********************/
\r
3255 #define EXTI_PR_PR0 ((uint32_t)0x00000001) /*!< Pending bit for line 0 */
\r
3256 #define EXTI_PR_PR1 ((uint32_t)0x00000002) /*!< Pending bit for line 1 */
\r
3257 #define EXTI_PR_PR2 ((uint32_t)0x00000004) /*!< Pending bit for line 2 */
\r
3258 #define EXTI_PR_PR3 ((uint32_t)0x00000008) /*!< Pending bit for line 3 */
\r
3259 #define EXTI_PR_PR4 ((uint32_t)0x00000010) /*!< Pending bit for line 4 */
\r
3260 #define EXTI_PR_PR5 ((uint32_t)0x00000020) /*!< Pending bit for line 5 */
\r
3261 #define EXTI_PR_PR6 ((uint32_t)0x00000040) /*!< Pending bit for line 6 */
\r
3262 #define EXTI_PR_PR7 ((uint32_t)0x00000080) /*!< Pending bit for line 7 */
\r
3263 #define EXTI_PR_PR8 ((uint32_t)0x00000100) /*!< Pending bit for line 8 */
\r
3264 #define EXTI_PR_PR9 ((uint32_t)0x00000200) /*!< Pending bit for line 9 */
\r
3265 #define EXTI_PR_PR10 ((uint32_t)0x00000400) /*!< Pending bit for line 10 */
\r
3266 #define EXTI_PR_PR11 ((uint32_t)0x00000800) /*!< Pending bit for line 11 */
\r
3267 #define EXTI_PR_PR12 ((uint32_t)0x00001000) /*!< Pending bit for line 12 */
\r
3268 #define EXTI_PR_PR13 ((uint32_t)0x00002000) /*!< Pending bit for line 13 */
\r
3269 #define EXTI_PR_PR14 ((uint32_t)0x00004000) /*!< Pending bit for line 14 */
\r
3270 #define EXTI_PR_PR15 ((uint32_t)0x00008000) /*!< Pending bit for line 15 */
\r
3271 #define EXTI_PR_PR16 ((uint32_t)0x00010000) /*!< Pending bit for line 16 */
\r
3272 #define EXTI_PR_PR17 ((uint32_t)0x00020000) /*!< Pending bit for line 17 */
\r
3273 #define EXTI_PR_PR18 ((uint32_t)0x00040000) /*!< Pending bit for line 18 */
\r
3274 #define EXTI_PR_PR19 ((uint32_t)0x00080000) /*!< Pending bit for line 19 */
\r
3276 /******************************************************************************/
\r
3280 /******************************************************************************/
\r
3281 /******************* Bits definition for FLASH_ACR register *****************/
\r
3282 #define FLASH_ACR_LATENCY ((uint32_t)0x0000000F)
\r
3283 #define FLASH_ACR_LATENCY_0WS ((uint32_t)0x00000000)
\r
3284 #define FLASH_ACR_LATENCY_1WS ((uint32_t)0x00000001)
\r
3285 #define FLASH_ACR_LATENCY_2WS ((uint32_t)0x00000002)
\r
3286 #define FLASH_ACR_LATENCY_3WS ((uint32_t)0x00000003)
\r
3287 #define FLASH_ACR_LATENCY_4WS ((uint32_t)0x00000004)
\r
3288 #define FLASH_ACR_LATENCY_5WS ((uint32_t)0x00000005)
\r
3289 #define FLASH_ACR_LATENCY_6WS ((uint32_t)0x00000006)
\r
3290 #define FLASH_ACR_LATENCY_7WS ((uint32_t)0x00000007)
\r
3292 #define FLASH_ACR_PRFTEN ((uint32_t)0x00000100)
\r
3293 #define FLASH_ACR_ICEN ((uint32_t)0x00000200)
\r
3294 #define FLASH_ACR_DCEN ((uint32_t)0x00000400)
\r
3295 #define FLASH_ACR_ICRST ((uint32_t)0x00000800)
\r
3296 #define FLASH_ACR_DCRST ((uint32_t)0x00001000)
\r
3297 #define FLASH_ACR_BYTE0_ADDRESS ((uint32_t)0x40023C00)
\r
3298 #define FLASH_ACR_BYTE2_ADDRESS ((uint32_t)0x40023C03)
\r
3300 /******************* Bits definition for FLASH_SR register ******************/
\r
3301 #define FLASH_SR_EOP ((uint32_t)0x00000001)
\r
3302 #define FLASH_SR_SOP ((uint32_t)0x00000002)
\r
3303 #define FLASH_SR_WRPERR ((uint32_t)0x00000010)
\r
3304 #define FLASH_SR_PGAERR ((uint32_t)0x00000020)
\r
3305 #define FLASH_SR_PGPERR ((uint32_t)0x00000040)
\r
3306 #define FLASH_SR_PGSERR ((uint32_t)0x00000080)
\r
3307 #define FLASH_SR_BSY ((uint32_t)0x00010000)
\r
3309 /******************* Bits definition for FLASH_CR register ******************/
\r
3310 #define FLASH_CR_PG ((uint32_t)0x00000001)
\r
3311 #define FLASH_CR_SER ((uint32_t)0x00000002)
\r
3312 #define FLASH_CR_MER ((uint32_t)0x00000004)
\r
3313 #define FLASH_CR_SNB ((uint32_t)0x000000F8)
\r
3314 #define FLASH_CR_SNB_0 ((uint32_t)0x00000008)
\r
3315 #define FLASH_CR_SNB_1 ((uint32_t)0x00000010)
\r
3316 #define FLASH_CR_SNB_2 ((uint32_t)0x00000020)
\r
3317 #define FLASH_CR_SNB_3 ((uint32_t)0x00000040)
\r
3318 #define FLASH_CR_SNB_4 ((uint32_t)0x00000080)
\r
3319 #define FLASH_CR_PSIZE ((uint32_t)0x00000300)
\r
3320 #define FLASH_CR_PSIZE_0 ((uint32_t)0x00000100)
\r
3321 #define FLASH_CR_PSIZE_1 ((uint32_t)0x00000200)
\r
3322 #define FLASH_CR_STRT ((uint32_t)0x00010000)
\r
3323 #define FLASH_CR_EOPIE ((uint32_t)0x01000000)
\r
3324 #define FLASH_CR_LOCK ((uint32_t)0x80000000)
\r
3326 /******************* Bits definition for FLASH_OPTCR register ***************/
\r
3327 #define FLASH_OPTCR_OPTLOCK ((uint32_t)0x00000001)
\r
3328 #define FLASH_OPTCR_OPTSTRT ((uint32_t)0x00000002)
\r
3329 #define FLASH_OPTCR_BOR_LEV_0 ((uint32_t)0x00000004)
\r
3330 #define FLASH_OPTCR_BOR_LEV_1 ((uint32_t)0x00000008)
\r
3331 #define FLASH_OPTCR_BOR_LEV ((uint32_t)0x0000000C)
\r
3333 #define FLASH_OPTCR_WDG_SW ((uint32_t)0x00000020)
\r
3334 #define FLASH_OPTCR_nRST_STOP ((uint32_t)0x00000040)
\r
3335 #define FLASH_OPTCR_nRST_STDBY ((uint32_t)0x00000080)
\r
3336 #define FLASH_OPTCR_RDP ((uint32_t)0x0000FF00)
\r
3337 #define FLASH_OPTCR_RDP_0 ((uint32_t)0x00000100)
\r
3338 #define FLASH_OPTCR_RDP_1 ((uint32_t)0x00000200)
\r
3339 #define FLASH_OPTCR_RDP_2 ((uint32_t)0x00000400)
\r
3340 #define FLASH_OPTCR_RDP_3 ((uint32_t)0x00000800)
\r
3341 #define FLASH_OPTCR_RDP_4 ((uint32_t)0x00001000)
\r
3342 #define FLASH_OPTCR_RDP_5 ((uint32_t)0x00002000)
\r
3343 #define FLASH_OPTCR_RDP_6 ((uint32_t)0x00004000)
\r
3344 #define FLASH_OPTCR_RDP_7 ((uint32_t)0x00008000)
\r
3345 #define FLASH_OPTCR_nWRP ((uint32_t)0x0FFF0000)
\r
3346 #define FLASH_OPTCR_nWRP_0 ((uint32_t)0x00010000)
\r
3347 #define FLASH_OPTCR_nWRP_1 ((uint32_t)0x00020000)
\r
3348 #define FLASH_OPTCR_nWRP_2 ((uint32_t)0x00040000)
\r
3349 #define FLASH_OPTCR_nWRP_3 ((uint32_t)0x00080000)
\r
3350 #define FLASH_OPTCR_nWRP_4 ((uint32_t)0x00100000)
\r
3351 #define FLASH_OPTCR_nWRP_5 ((uint32_t)0x00200000)
\r
3352 #define FLASH_OPTCR_nWRP_6 ((uint32_t)0x00400000)
\r
3353 #define FLASH_OPTCR_nWRP_7 ((uint32_t)0x00800000)
\r
3354 #define FLASH_OPTCR_nWRP_8 ((uint32_t)0x01000000)
\r
3355 #define FLASH_OPTCR_nWRP_9 ((uint32_t)0x02000000)
\r
3356 #define FLASH_OPTCR_nWRP_10 ((uint32_t)0x04000000)
\r
3357 #define FLASH_OPTCR_nWRP_11 ((uint32_t)0x08000000)
\r
3359 /****************** Bits definition for FLASH_OPTCR1 register ***************/
\r
3360 #define FLASH_OPTCR1_nWRP ((uint32_t)0x0FFF0000)
\r
3361 #define FLASH_OPTCR1_nWRP_0 ((uint32_t)0x00010000)
\r
3362 #define FLASH_OPTCR1_nWRP_1 ((uint32_t)0x00020000)
\r
3363 #define FLASH_OPTCR1_nWRP_2 ((uint32_t)0x00040000)
\r
3364 #define FLASH_OPTCR1_nWRP_3 ((uint32_t)0x00080000)
\r
3365 #define FLASH_OPTCR1_nWRP_4 ((uint32_t)0x00100000)
\r
3366 #define FLASH_OPTCR1_nWRP_5 ((uint32_t)0x00200000)
\r
3367 #define FLASH_OPTCR1_nWRP_6 ((uint32_t)0x00400000)
\r
3368 #define FLASH_OPTCR1_nWRP_7 ((uint32_t)0x00800000)
\r
3369 #define FLASH_OPTCR1_nWRP_8 ((uint32_t)0x01000000)
\r
3370 #define FLASH_OPTCR1_nWRP_9 ((uint32_t)0x02000000)
\r
3371 #define FLASH_OPTCR1_nWRP_10 ((uint32_t)0x04000000)
\r
3372 #define FLASH_OPTCR1_nWRP_11 ((uint32_t)0x08000000)
\r
3374 /******************************************************************************/
\r
3376 /* Flexible Static Memory Controller */
\r
3378 /******************************************************************************/
\r
3379 /****************** Bit definition for FSMC_BCR1 register *******************/
\r
3380 #define FSMC_BCR1_MBKEN ((uint32_t)0x00000001) /*!<Memory bank enable bit */
\r
3381 #define FSMC_BCR1_MUXEN ((uint32_t)0x00000002) /*!<Address/data multiplexing enable bit */
\r
3383 #define FSMC_BCR1_MTYP ((uint32_t)0x0000000C) /*!<MTYP[1:0] bits (Memory type) */
\r
3384 #define FSMC_BCR1_MTYP_0 ((uint32_t)0x00000004) /*!<Bit 0 */
\r
3385 #define FSMC_BCR1_MTYP_1 ((uint32_t)0x00000008) /*!<Bit 1 */
\r
3387 #define FSMC_BCR1_MWID ((uint32_t)0x00000030) /*!<MWID[1:0] bits (Memory data bus width) */
\r
3388 #define FSMC_BCR1_MWID_0 ((uint32_t)0x00000010) /*!<Bit 0 */
\r
3389 #define FSMC_BCR1_MWID_1 ((uint32_t)0x00000020) /*!<Bit 1 */
\r
3391 #define FSMC_BCR1_FACCEN ((uint32_t)0x00000040) /*!<Flash access enable */
\r
3392 #define FSMC_BCR1_BURSTEN ((uint32_t)0x00000100) /*!<Burst enable bit */
\r
3393 #define FSMC_BCR1_WAITPOL ((uint32_t)0x00000200) /*!<Wait signal polarity bit */
\r
3394 #define FSMC_BCR1_WRAPMOD ((uint32_t)0x00000400) /*!<Wrapped burst mode support */
\r
3395 #define FSMC_BCR1_WAITCFG ((uint32_t)0x00000800) /*!<Wait timing configuration */
\r
3396 #define FSMC_BCR1_WREN ((uint32_t)0x00001000) /*!<Write enable bit */
\r
3397 #define FSMC_BCR1_WAITEN ((uint32_t)0x00002000) /*!<Wait enable bit */
\r
3398 #define FSMC_BCR1_EXTMOD ((uint32_t)0x00004000) /*!<Extended mode enable */
\r
3399 #define FSMC_BCR1_ASYNCWAIT ((uint32_t)0x00008000) /*!<Asynchronous wait */
\r
3400 #define FSMC_BCR1_CBURSTRW ((uint32_t)0x00080000) /*!<Write burst enable */
\r
3402 /****************** Bit definition for FSMC_BCR2 register *******************/
\r
3403 #define FSMC_BCR2_MBKEN ((uint32_t)0x00000001) /*!<Memory bank enable bit */
\r
3404 #define FSMC_BCR2_MUXEN ((uint32_t)0x00000002) /*!<Address/data multiplexing enable bit */
\r
3406 #define FSMC_BCR2_MTYP ((uint32_t)0x0000000C) /*!<MTYP[1:0] bits (Memory type) */
\r
3407 #define FSMC_BCR2_MTYP_0 ((uint32_t)0x00000004) /*!<Bit 0 */
\r
3408 #define FSMC_BCR2_MTYP_1 ((uint32_t)0x00000008) /*!<Bit 1 */
\r
3410 #define FSMC_BCR2_MWID ((uint32_t)0x00000030) /*!<MWID[1:0] bits (Memory data bus width) */
\r
3411 #define FSMC_BCR2_MWID_0 ((uint32_t)0x00000010) /*!<Bit 0 */
\r
3412 #define FSMC_BCR2_MWID_1 ((uint32_t)0x00000020) /*!<Bit 1 */
\r
3414 #define FSMC_BCR2_FACCEN ((uint32_t)0x00000040) /*!<Flash access enable */
\r
3415 #define FSMC_BCR2_BURSTEN ((uint32_t)0x00000100) /*!<Burst enable bit */
\r
3416 #define FSMC_BCR2_WAITPOL ((uint32_t)0x00000200) /*!<Wait signal polarity bit */
\r
3417 #define FSMC_BCR2_WRAPMOD ((uint32_t)0x00000400) /*!<Wrapped burst mode support */
\r
3418 #define FSMC_BCR2_WAITCFG ((uint32_t)0x00000800) /*!<Wait timing configuration */
\r
3419 #define FSMC_BCR2_WREN ((uint32_t)0x00001000) /*!<Write enable bit */
\r
3420 #define FSMC_BCR2_WAITEN ((uint32_t)0x00002000) /*!<Wait enable bit */
\r
3421 #define FSMC_BCR2_EXTMOD ((uint32_t)0x00004000) /*!<Extended mode enable */
\r
3422 #define FSMC_BCR2_ASYNCWAIT ((uint32_t)0x00008000) /*!<Asynchronous wait */
\r
3423 #define FSMC_BCR2_CBURSTRW ((uint32_t)0x00080000) /*!<Write burst enable */
\r
3425 /****************** Bit definition for FSMC_BCR3 register *******************/
\r
3426 #define FSMC_BCR3_MBKEN ((uint32_t)0x00000001) /*!<Memory bank enable bit */
\r
3427 #define FSMC_BCR3_MUXEN ((uint32_t)0x00000002) /*!<Address/data multiplexing enable bit */
\r
3429 #define FSMC_BCR3_MTYP ((uint32_t)0x0000000C) /*!<MTYP[1:0] bits (Memory type) */
\r
3430 #define FSMC_BCR3_MTYP_0 ((uint32_t)0x00000004) /*!<Bit 0 */
\r
3431 #define FSMC_BCR3_MTYP_1 ((uint32_t)0x00000008) /*!<Bit 1 */
\r
3433 #define FSMC_BCR3_MWID ((uint32_t)0x00000030) /*!<MWID[1:0] bits (Memory data bus width) */
\r
3434 #define FSMC_BCR3_MWID_0 ((uint32_t)0x00000010) /*!<Bit 0 */
\r
3435 #define FSMC_BCR3_MWID_1 ((uint32_t)0x00000020) /*!<Bit 1 */
\r
3437 #define FSMC_BCR3_FACCEN ((uint32_t)0x00000040) /*!<Flash access enable */
\r
3438 #define FSMC_BCR3_BURSTEN ((uint32_t)0x00000100) /*!<Burst enable bit */
\r
3439 #define FSMC_BCR3_WAITPOL ((uint32_t)0x00000200) /*!<Wait signal polarity bit */
\r
3440 #define FSMC_BCR3_WRAPMOD ((uint32_t)0x00000400) /*!<Wrapped burst mode support */
\r
3441 #define FSMC_BCR3_WAITCFG ((uint32_t)0x00000800) /*!<Wait timing configuration */
\r
3442 #define FSMC_BCR3_WREN ((uint32_t)0x00001000) /*!<Write enable bit */
\r
3443 #define FSMC_BCR3_WAITEN ((uint32_t)0x00002000) /*!<Wait enable bit */
\r
3444 #define FSMC_BCR3_EXTMOD ((uint32_t)0x00004000) /*!<Extended mode enable */
\r
3445 #define FSMC_BCR3_ASYNCWAIT ((uint32_t)0x00008000) /*!<Asynchronous wait */
\r
3446 #define FSMC_BCR3_CBURSTRW ((uint32_t)0x00080000) /*!<Write burst enable */
\r
3448 /****************** Bit definition for FSMC_BCR4 register *******************/
\r
3449 #define FSMC_BCR4_MBKEN ((uint32_t)0x00000001) /*!<Memory bank enable bit */
\r
3450 #define FSMC_BCR4_MUXEN ((uint32_t)0x00000002) /*!<Address/data multiplexing enable bit */
\r
3452 #define FSMC_BCR4_MTYP ((uint32_t)0x0000000C) /*!<MTYP[1:0] bits (Memory type) */
\r
3453 #define FSMC_BCR4_MTYP_0 ((uint32_t)0x00000004) /*!<Bit 0 */
\r
3454 #define FSMC_BCR4_MTYP_1 ((uint32_t)0x00000008) /*!<Bit 1 */
\r
3456 #define FSMC_BCR4_MWID ((uint32_t)0x00000030) /*!<MWID[1:0] bits (Memory data bus width) */
\r
3457 #define FSMC_BCR4_MWID_0 ((uint32_t)0x00000010) /*!<Bit 0 */
\r
3458 #define FSMC_BCR4_MWID_1 ((uint32_t)0x00000020) /*!<Bit 1 */
\r
3460 #define FSMC_BCR4_FACCEN ((uint32_t)0x00000040) /*!<Flash access enable */
\r
3461 #define FSMC_BCR4_BURSTEN ((uint32_t)0x00000100) /*!<Burst enable bit */
\r
3462 #define FSMC_BCR4_WAITPOL ((uint32_t)0x00000200) /*!<Wait signal polarity bit */
\r
3463 #define FSMC_BCR4_WRAPMOD ((uint32_t)0x00000400) /*!<Wrapped burst mode support */
\r
3464 #define FSMC_BCR4_WAITCFG ((uint32_t)0x00000800) /*!<Wait timing configuration */
\r
3465 #define FSMC_BCR4_WREN ((uint32_t)0x00001000) /*!<Write enable bit */
\r
3466 #define FSMC_BCR4_WAITEN ((uint32_t)0x00002000) /*!<Wait enable bit */
\r
3467 #define FSMC_BCR4_EXTMOD ((uint32_t)0x00004000) /*!<Extended mode enable */
\r
3468 #define FSMC_BCR4_ASYNCWAIT ((uint32_t)0x00008000) /*!<Asynchronous wait */
\r
3469 #define FSMC_BCR4_CBURSTRW ((uint32_t)0x00080000) /*!<Write burst enable */
\r
3471 /****************** Bit definition for FSMC_BTR1 register ******************/
\r
3472 #define FSMC_BTR1_ADDSET ((uint32_t)0x0000000F) /*!<ADDSET[3:0] bits (Address setup phase duration) */
\r
3473 #define FSMC_BTR1_ADDSET_0 ((uint32_t)0x00000001) /*!<Bit 0 */
\r
3474 #define FSMC_BTR1_ADDSET_1 ((uint32_t)0x00000002) /*!<Bit 1 */
\r
3475 #define FSMC_BTR1_ADDSET_2 ((uint32_t)0x00000004) /*!<Bit 2 */
\r
3476 #define FSMC_BTR1_ADDSET_3 ((uint32_t)0x00000008) /*!<Bit 3 */
\r
3478 #define FSMC_BTR1_ADDHLD ((uint32_t)0x000000F0) /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
\r
3479 #define FSMC_BTR1_ADDHLD_0 ((uint32_t)0x00000010) /*!<Bit 0 */
\r
3480 #define FSMC_BTR1_ADDHLD_1 ((uint32_t)0x00000020) /*!<Bit 1 */
\r
3481 #define FSMC_BTR1_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */
\r
3482 #define FSMC_BTR1_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */
\r
3484 #define FSMC_BTR1_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */
\r
3485 #define FSMC_BTR1_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */
\r
3486 #define FSMC_BTR1_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */
\r
3487 #define FSMC_BTR1_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */
\r
3488 #define FSMC_BTR1_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */
\r
3490 #define FSMC_BTR1_BUSTURN ((uint32_t)0x000F0000) /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
\r
3491 #define FSMC_BTR1_BUSTURN_0 ((uint32_t)0x00010000) /*!<Bit 0 */
\r
3492 #define FSMC_BTR1_BUSTURN_1 ((uint32_t)0x00020000) /*!<Bit 1 */
\r
3493 #define FSMC_BTR1_BUSTURN_2 ((uint32_t)0x00040000) /*!<Bit 2 */
\r
3494 #define FSMC_BTR1_BUSTURN_3 ((uint32_t)0x00080000) /*!<Bit 3 */
\r
3496 #define FSMC_BTR1_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */
\r
3497 #define FSMC_BTR1_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */
\r
3498 #define FSMC_BTR1_CLKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1 */
\r
3499 #define FSMC_BTR1_CLKDIV_2 ((uint32_t)0x00400000) /*!<Bit 2 */
\r
3500 #define FSMC_BTR1_CLKDIV_3 ((uint32_t)0x00800000) /*!<Bit 3 */
\r
3502 #define FSMC_BTR1_DATLAT ((uint32_t)0x0F000000) /*!<DATLA[3:0] bits (Data latency) */
\r
3503 #define FSMC_BTR1_DATLAT_0 ((uint32_t)0x01000000) /*!<Bit 0 */
\r
3504 #define FSMC_BTR1_DATLAT_1 ((uint32_t)0x02000000) /*!<Bit 1 */
\r
3505 #define FSMC_BTR1_DATLAT_2 ((uint32_t)0x04000000) /*!<Bit 2 */
\r
3506 #define FSMC_BTR1_DATLAT_3 ((uint32_t)0x08000000) /*!<Bit 3 */
\r
3508 #define FSMC_BTR1_ACCMOD ((uint32_t)0x30000000) /*!<ACCMOD[1:0] bits (Access mode) */
\r
3509 #define FSMC_BTR1_ACCMOD_0 ((uint32_t)0x10000000) /*!<Bit 0 */
\r
3510 #define FSMC_BTR1_ACCMOD_1 ((uint32_t)0x20000000) /*!<Bit 1 */
\r
3512 /****************** Bit definition for FSMC_BTR2 register *******************/
\r
3513 #define FSMC_BTR2_ADDSET ((uint32_t)0x0000000F) /*!<ADDSET[3:0] bits (Address setup phase duration) */
\r
3514 #define FSMC_BTR2_ADDSET_0 ((uint32_t)0x00000001) /*!<Bit 0 */
\r
3515 #define FSMC_BTR2_ADDSET_1 ((uint32_t)0x00000002) /*!<Bit 1 */
\r
3516 #define FSMC_BTR2_ADDSET_2 ((uint32_t)0x00000004) /*!<Bit 2 */
\r
3517 #define FSMC_BTR2_ADDSET_3 ((uint32_t)0x00000008) /*!<Bit 3 */
\r
3519 #define FSMC_BTR2_ADDHLD ((uint32_t)0x000000F0) /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
\r
3520 #define FSMC_BTR2_ADDHLD_0 ((uint32_t)0x00000010) /*!<Bit 0 */
\r
3521 #define FSMC_BTR2_ADDHLD_1 ((uint32_t)0x00000020) /*!<Bit 1 */
\r
3522 #define FSMC_BTR2_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */
\r
3523 #define FSMC_BTR2_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */
\r
3525 #define FSMC_BTR2_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */
\r
3526 #define FSMC_BTR2_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */
\r
3527 #define FSMC_BTR2_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */
\r
3528 #define FSMC_BTR2_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */
\r
3529 #define FSMC_BTR2_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */
\r
3531 #define FSMC_BTR2_BUSTURN ((uint32_t)0x000F0000) /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
\r
3532 #define FSMC_BTR2_BUSTURN_0 ((uint32_t)0x00010000) /*!<Bit 0 */
\r
3533 #define FSMC_BTR2_BUSTURN_1 ((uint32_t)0x00020000) /*!<Bit 1 */
\r
3534 #define FSMC_BTR2_BUSTURN_2 ((uint32_t)0x00040000) /*!<Bit 2 */
\r
3535 #define FSMC_BTR2_BUSTURN_3 ((uint32_t)0x00080000) /*!<Bit 3 */
\r
3537 #define FSMC_BTR2_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */
\r
3538 #define FSMC_BTR2_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */
\r
3539 #define FSMC_BTR2_CLKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1 */
\r
3540 #define FSMC_BTR2_CLKDIV_2 ((uint32_t)0x00400000) /*!<Bit 2 */
\r
3541 #define FSMC_BTR2_CLKDIV_3 ((uint32_t)0x00800000) /*!<Bit 3 */
\r
3543 #define FSMC_BTR2_DATLAT ((uint32_t)0x0F000000) /*!<DATLA[3:0] bits (Data latency) */
\r
3544 #define FSMC_BTR2_DATLAT_0 ((uint32_t)0x01000000) /*!<Bit 0 */
\r
3545 #define FSMC_BTR2_DATLAT_1 ((uint32_t)0x02000000) /*!<Bit 1 */
\r
3546 #define FSMC_BTR2_DATLAT_2 ((uint32_t)0x04000000) /*!<Bit 2 */
\r
3547 #define FSMC_BTR2_DATLAT_3 ((uint32_t)0x08000000) /*!<Bit 3 */
\r
3549 #define FSMC_BTR2_ACCMOD ((uint32_t)0x30000000) /*!<ACCMOD[1:0] bits (Access mode) */
\r
3550 #define FSMC_BTR2_ACCMOD_0 ((uint32_t)0x10000000) /*!<Bit 0 */
\r
3551 #define FSMC_BTR2_ACCMOD_1 ((uint32_t)0x20000000) /*!<Bit 1 */
\r
3553 /******************* Bit definition for FSMC_BTR3 register *******************/
\r
3554 #define FSMC_BTR3_ADDSET ((uint32_t)0x0000000F) /*!<ADDSET[3:0] bits (Address setup phase duration) */
\r
3555 #define FSMC_BTR3_ADDSET_0 ((uint32_t)0x00000001) /*!<Bit 0 */
\r
3556 #define FSMC_BTR3_ADDSET_1 ((uint32_t)0x00000002) /*!<Bit 1 */
\r
3557 #define FSMC_BTR3_ADDSET_2 ((uint32_t)0x00000004) /*!<Bit 2 */
\r
3558 #define FSMC_BTR3_ADDSET_3 ((uint32_t)0x00000008) /*!<Bit 3 */
\r
3560 #define FSMC_BTR3_ADDHLD ((uint32_t)0x000000F0) /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
\r
3561 #define FSMC_BTR3_ADDHLD_0 ((uint32_t)0x00000010) /*!<Bit 0 */
\r
3562 #define FSMC_BTR3_ADDHLD_1 ((uint32_t)0x00000020) /*!<Bit 1 */
\r
3563 #define FSMC_BTR3_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */
\r
3564 #define FSMC_BTR3_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */
\r
3566 #define FSMC_BTR3_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */
\r
3567 #define FSMC_BTR3_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */
\r
3568 #define FSMC_BTR3_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */
\r
3569 #define FSMC_BTR3_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */
\r
3570 #define FSMC_BTR3_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */
\r
3572 #define FSMC_BTR3_BUSTURN ((uint32_t)0x000F0000) /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
\r
3573 #define FSMC_BTR3_BUSTURN_0 ((uint32_t)0x00010000) /*!<Bit 0 */
\r
3574 #define FSMC_BTR3_BUSTURN_1 ((uint32_t)0x00020000) /*!<Bit 1 */
\r
3575 #define FSMC_BTR3_BUSTURN_2 ((uint32_t)0x00040000) /*!<Bit 2 */
\r
3576 #define FSMC_BTR3_BUSTURN_3 ((uint32_t)0x00080000) /*!<Bit 3 */
\r
3578 #define FSMC_BTR3_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */
\r
3579 #define FSMC_BTR3_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */
\r
3580 #define FSMC_BTR3_CLKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1 */
\r
3581 #define FSMC_BTR3_CLKDIV_2 ((uint32_t)0x00400000) /*!<Bit 2 */
\r
3582 #define FSMC_BTR3_CLKDIV_3 ((uint32_t)0x00800000) /*!<Bit 3 */
\r
3584 #define FSMC_BTR3_DATLAT ((uint32_t)0x0F000000) /*!<DATLA[3:0] bits (Data latency) */
\r
3585 #define FSMC_BTR3_DATLAT_0 ((uint32_t)0x01000000) /*!<Bit 0 */
\r
3586 #define FSMC_BTR3_DATLAT_1 ((uint32_t)0x02000000) /*!<Bit 1 */
\r
3587 #define FSMC_BTR3_DATLAT_2 ((uint32_t)0x04000000) /*!<Bit 2 */
\r
3588 #define FSMC_BTR3_DATLAT_3 ((uint32_t)0x08000000) /*!<Bit 3 */
\r
3590 #define FSMC_BTR3_ACCMOD ((uint32_t)0x30000000) /*!<ACCMOD[1:0] bits (Access mode) */
\r
3591 #define FSMC_BTR3_ACCMOD_0 ((uint32_t)0x10000000) /*!<Bit 0 */
\r
3592 #define FSMC_BTR3_ACCMOD_1 ((uint32_t)0x20000000) /*!<Bit 1 */
\r
3594 /****************** Bit definition for FSMC_BTR4 register *******************/
\r
3595 #define FSMC_BTR4_ADDSET ((uint32_t)0x0000000F) /*!<ADDSET[3:0] bits (Address setup phase duration) */
\r
3596 #define FSMC_BTR4_ADDSET_0 ((uint32_t)0x00000001) /*!<Bit 0 */
\r
3597 #define FSMC_BTR4_ADDSET_1 ((uint32_t)0x00000002) /*!<Bit 1 */
\r
3598 #define FSMC_BTR4_ADDSET_2 ((uint32_t)0x00000004) /*!<Bit 2 */
\r
3599 #define FSMC_BTR4_ADDSET_3 ((uint32_t)0x00000008) /*!<Bit 3 */
\r
3601 #define FSMC_BTR4_ADDHLD ((uint32_t)0x000000F0) /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
\r
3602 #define FSMC_BTR4_ADDHLD_0 ((uint32_t)0x00000010) /*!<Bit 0 */
\r
3603 #define FSMC_BTR4_ADDHLD_1 ((uint32_t)0x00000020) /*!<Bit 1 */
\r
3604 #define FSMC_BTR4_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */
\r
3605 #define FSMC_BTR4_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */
\r
3607 #define FSMC_BTR4_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */
\r
3608 #define FSMC_BTR4_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */
\r
3609 #define FSMC_BTR4_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */
\r
3610 #define FSMC_BTR4_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */
\r
3611 #define FSMC_BTR4_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */
\r
3613 #define FSMC_BTR4_BUSTURN ((uint32_t)0x000F0000) /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
\r
3614 #define FSMC_BTR4_BUSTURN_0 ((uint32_t)0x00010000) /*!<Bit 0 */
\r
3615 #define FSMC_BTR4_BUSTURN_1 ((uint32_t)0x00020000) /*!<Bit 1 */
\r
3616 #define FSMC_BTR4_BUSTURN_2 ((uint32_t)0x00040000) /*!<Bit 2 */
\r
3617 #define FSMC_BTR4_BUSTURN_3 ((uint32_t)0x00080000) /*!<Bit 3 */
\r
3619 #define FSMC_BTR4_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */
\r
3620 #define FSMC_BTR4_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */
\r
3621 #define FSMC_BTR4_CLKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1 */
\r
3622 #define FSMC_BTR4_CLKDIV_2 ((uint32_t)0x00400000) /*!<Bit 2 */
\r
3623 #define FSMC_BTR4_CLKDIV_3 ((uint32_t)0x00800000) /*!<Bit 3 */
\r
3625 #define FSMC_BTR4_DATLAT ((uint32_t)0x0F000000) /*!<DATLA[3:0] bits (Data latency) */
\r
3626 #define FSMC_BTR4_DATLAT_0 ((uint32_t)0x01000000) /*!<Bit 0 */
\r
3627 #define FSMC_BTR4_DATLAT_1 ((uint32_t)0x02000000) /*!<Bit 1 */
\r
3628 #define FSMC_BTR4_DATLAT_2 ((uint32_t)0x04000000) /*!<Bit 2 */
\r
3629 #define FSMC_BTR4_DATLAT_3 ((uint32_t)0x08000000) /*!<Bit 3 */
\r
3631 #define FSMC_BTR4_ACCMOD ((uint32_t)0x30000000) /*!<ACCMOD[1:0] bits (Access mode) */
\r
3632 #define FSMC_BTR4_ACCMOD_0 ((uint32_t)0x10000000) /*!<Bit 0 */
\r
3633 #define FSMC_BTR4_ACCMOD_1 ((uint32_t)0x20000000) /*!<Bit 1 */
\r
3635 /****************** Bit definition for FSMC_BWTR1 register ******************/
\r
3636 #define FSMC_BWTR1_ADDSET ((uint32_t)0x0000000F) /*!<ADDSET[3:0] bits (Address setup phase duration) */
\r
3637 #define FSMC_BWTR1_ADDSET_0 ((uint32_t)0x00000001) /*!<Bit 0 */
\r
3638 #define FSMC_BWTR1_ADDSET_1 ((uint32_t)0x00000002) /*!<Bit 1 */
\r
3639 #define FSMC_BWTR1_ADDSET_2 ((uint32_t)0x00000004) /*!<Bit 2 */
\r
3640 #define FSMC_BWTR1_ADDSET_3 ((uint32_t)0x00000008) /*!<Bit 3 */
\r
3642 #define FSMC_BWTR1_ADDHLD ((uint32_t)0x000000F0) /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
\r
3643 #define FSMC_BWTR1_ADDHLD_0 ((uint32_t)0x00000010) /*!<Bit 0 */
\r
3644 #define FSMC_BWTR1_ADDHLD_1 ((uint32_t)0x00000020) /*!<Bit 1 */
\r
3645 #define FSMC_BWTR1_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */
\r
3646 #define FSMC_BWTR1_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */
\r
3648 #define FSMC_BWTR1_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */
\r
3649 #define FSMC_BWTR1_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */
\r
3650 #define FSMC_BWTR1_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */
\r
3651 #define FSMC_BWTR1_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */
\r
3652 #define FSMC_BWTR1_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */
\r
3654 #define FSMC_BWTR1_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */
\r
3655 #define FSMC_BWTR1_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */
\r
3656 #define FSMC_BWTR1_CLKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1 */
\r
3657 #define FSMC_BWTR1_CLKDIV_2 ((uint32_t)0x00400000) /*!<Bit 2 */
\r
3658 #define FSMC_BWTR1_CLKDIV_3 ((uint32_t)0x00800000) /*!<Bit 3 */
\r
3660 #define FSMC_BWTR1_DATLAT ((uint32_t)0x0F000000) /*!<DATLA[3:0] bits (Data latency) */
\r
3661 #define FSMC_BWTR1_DATLAT_0 ((uint32_t)0x01000000) /*!<Bit 0 */
\r
3662 #define FSMC_BWTR1_DATLAT_1 ((uint32_t)0x02000000) /*!<Bit 1 */
\r
3663 #define FSMC_BWTR1_DATLAT_2 ((uint32_t)0x04000000) /*!<Bit 2 */
\r
3664 #define FSMC_BWTR1_DATLAT_3 ((uint32_t)0x08000000) /*!<Bit 3 */
\r
3666 #define FSMC_BWTR1_ACCMOD ((uint32_t)0x30000000) /*!<ACCMOD[1:0] bits (Access mode) */
\r
3667 #define FSMC_BWTR1_ACCMOD_0 ((uint32_t)0x10000000) /*!<Bit 0 */
\r
3668 #define FSMC_BWTR1_ACCMOD_1 ((uint32_t)0x20000000) /*!<Bit 1 */
\r
3670 /****************** Bit definition for FSMC_BWTR2 register ******************/
\r
3671 #define FSMC_BWTR2_ADDSET ((uint32_t)0x0000000F) /*!<ADDSET[3:0] bits (Address setup phase duration) */
\r
3672 #define FSMC_BWTR2_ADDSET_0 ((uint32_t)0x00000001) /*!<Bit 0 */
\r
3673 #define FSMC_BWTR2_ADDSET_1 ((uint32_t)0x00000002) /*!<Bit 1 */
\r
3674 #define FSMC_BWTR2_ADDSET_2 ((uint32_t)0x00000004) /*!<Bit 2 */
\r
3675 #define FSMC_BWTR2_ADDSET_3 ((uint32_t)0x00000008) /*!<Bit 3 */
\r
3677 #define FSMC_BWTR2_ADDHLD ((uint32_t)0x000000F0) /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
\r
3678 #define FSMC_BWTR2_ADDHLD_0 ((uint32_t)0x00000010) /*!<Bit 0 */
\r
3679 #define FSMC_BWTR2_ADDHLD_1 ((uint32_t)0x00000020) /*!<Bit 1 */
\r
3680 #define FSMC_BWTR2_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */
\r
3681 #define FSMC_BWTR2_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */
\r
3683 #define FSMC_BWTR2_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */
\r
3684 #define FSMC_BWTR2_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */
\r
3685 #define FSMC_BWTR2_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */
\r
3686 #define FSMC_BWTR2_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */
\r
3687 #define FSMC_BWTR2_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */
\r
3689 #define FSMC_BWTR2_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */
\r
3690 #define FSMC_BWTR2_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */
\r
3691 #define FSMC_BWTR2_CLKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1*/
\r
3692 #define FSMC_BWTR2_CLKDIV_2 ((uint32_t)0x00400000) /*!<Bit 2 */
\r
3693 #define FSMC_BWTR2_CLKDIV_3 ((uint32_t)0x00800000) /*!<Bit 3 */
\r
3695 #define FSMC_BWTR2_DATLAT ((uint32_t)0x0F000000) /*!<DATLA[3:0] bits (Data latency) */
\r
3696 #define FSMC_BWTR2_DATLAT_0 ((uint32_t)0x01000000) /*!<Bit 0 */
\r
3697 #define FSMC_BWTR2_DATLAT_1 ((uint32_t)0x02000000) /*!<Bit 1 */
\r
3698 #define FSMC_BWTR2_DATLAT_2 ((uint32_t)0x04000000) /*!<Bit 2 */
\r
3699 #define FSMC_BWTR2_DATLAT_3 ((uint32_t)0x08000000) /*!<Bit 3 */
\r
3701 #define FSMC_BWTR2_ACCMOD ((uint32_t)0x30000000) /*!<ACCMOD[1:0] bits (Access mode) */
\r
3702 #define FSMC_BWTR2_ACCMOD_0 ((uint32_t)0x10000000) /*!<Bit 0 */
\r
3703 #define FSMC_BWTR2_ACCMOD_1 ((uint32_t)0x20000000) /*!<Bit 1 */
\r
3705 /****************** Bit definition for FSMC_BWTR3 register ******************/
\r
3706 #define FSMC_BWTR3_ADDSET ((uint32_t)0x0000000F) /*!<ADDSET[3:0] bits (Address setup phase duration) */
\r
3707 #define FSMC_BWTR3_ADDSET_0 ((uint32_t)0x00000001) /*!<Bit 0 */
\r
3708 #define FSMC_BWTR3_ADDSET_1 ((uint32_t)0x00000002) /*!<Bit 1 */
\r
3709 #define FSMC_BWTR3_ADDSET_2 ((uint32_t)0x00000004) /*!<Bit 2 */
\r
3710 #define FSMC_BWTR3_ADDSET_3 ((uint32_t)0x00000008) /*!<Bit 3 */
\r
3712 #define FSMC_BWTR3_ADDHLD ((uint32_t)0x000000F0) /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
\r
3713 #define FSMC_BWTR3_ADDHLD_0 ((uint32_t)0x00000010) /*!<Bit 0 */
\r
3714 #define FSMC_BWTR3_ADDHLD_1 ((uint32_t)0x00000020) /*!<Bit 1 */
\r
3715 #define FSMC_BWTR3_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */
\r
3716 #define FSMC_BWTR3_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */
\r
3718 #define FSMC_BWTR3_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */
\r
3719 #define FSMC_BWTR3_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */
\r
3720 #define FSMC_BWTR3_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */
\r
3721 #define FSMC_BWTR3_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */
\r
3722 #define FSMC_BWTR3_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */
\r
3724 #define FSMC_BWTR3_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */
\r
3725 #define FSMC_BWTR3_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */
\r
3726 #define FSMC_BWTR3_CLKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1 */
\r
3727 #define FSMC_BWTR3_CLKDIV_2 ((uint32_t)0x00400000) /*!<Bit 2 */
\r
3728 #define FSMC_BWTR3_CLKDIV_3 ((uint32_t)0x00800000) /*!<Bit 3 */
\r
3730 #define FSMC_BWTR3_DATLAT ((uint32_t)0x0F000000) /*!<DATLA[3:0] bits (Data latency) */
\r
3731 #define FSMC_BWTR3_DATLAT_0 ((uint32_t)0x01000000) /*!<Bit 0 */
\r
3732 #define FSMC_BWTR3_DATLAT_1 ((uint32_t)0x02000000) /*!<Bit 1 */
\r
3733 #define FSMC_BWTR3_DATLAT_2 ((uint32_t)0x04000000) /*!<Bit 2 */
\r
3734 #define FSMC_BWTR3_DATLAT_3 ((uint32_t)0x08000000) /*!<Bit 3 */
\r
3736 #define FSMC_BWTR3_ACCMOD ((uint32_t)0x30000000) /*!<ACCMOD[1:0] bits (Access mode) */
\r
3737 #define FSMC_BWTR3_ACCMOD_0 ((uint32_t)0x10000000) /*!<Bit 0 */
\r
3738 #define FSMC_BWTR3_ACCMOD_1 ((uint32_t)0x20000000) /*!<Bit 1 */
\r
3740 /****************** Bit definition for FSMC_BWTR4 register ******************/
\r
3741 #define FSMC_BWTR4_ADDSET ((uint32_t)0x0000000F) /*!<ADDSET[3:0] bits (Address setup phase duration) */
\r
3742 #define FSMC_BWTR4_ADDSET_0 ((uint32_t)0x00000001) /*!<Bit 0 */
\r
3743 #define FSMC_BWTR4_ADDSET_1 ((uint32_t)0x00000002) /*!<Bit 1 */
\r
3744 #define FSMC_BWTR4_ADDSET_2 ((uint32_t)0x00000004) /*!<Bit 2 */
\r
3745 #define FSMC_BWTR4_ADDSET_3 ((uint32_t)0x00000008) /*!<Bit 3 */
\r
3747 #define FSMC_BWTR4_ADDHLD ((uint32_t)0x000000F0) /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
\r
3748 #define FSMC_BWTR4_ADDHLD_0 ((uint32_t)0x00000010) /*!<Bit 0 */
\r
3749 #define FSMC_BWTR4_ADDHLD_1 ((uint32_t)0x00000020) /*!<Bit 1 */
\r
3750 #define FSMC_BWTR4_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */
\r
3751 #define FSMC_BWTR4_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */
\r
3753 #define FSMC_BWTR4_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */
\r
3754 #define FSMC_BWTR4_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */
\r
3755 #define FSMC_BWTR4_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */
\r
3756 #define FSMC_BWTR4_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */
\r
3757 #define FSMC_BWTR4_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */
\r
3759 #define FSMC_BWTR4_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */
\r
3760 #define FSMC_BWTR4_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */
\r
3761 #define FSMC_BWTR4_CLKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1 */
\r
3762 #define FSMC_BWTR4_CLKDIV_2 ((uint32_t)0x00400000) /*!<Bit 2 */
\r
3763 #define FSMC_BWTR4_CLKDIV_3 ((uint32_t)0x00800000) /*!<Bit 3 */
\r
3765 #define FSMC_BWTR4_DATLAT ((uint32_t)0x0F000000) /*!<DATLA[3:0] bits (Data latency) */
\r
3766 #define FSMC_BWTR4_DATLAT_0 ((uint32_t)0x01000000) /*!<Bit 0 */
\r
3767 #define FSMC_BWTR4_DATLAT_1 ((uint32_t)0x02000000) /*!<Bit 1 */
\r
3768 #define FSMC_BWTR4_DATLAT_2 ((uint32_t)0x04000000) /*!<Bit 2 */
\r
3769 #define FSMC_BWTR4_DATLAT_3 ((uint32_t)0x08000000) /*!<Bit 3 */
\r
3771 #define FSMC_BWTR4_ACCMOD ((uint32_t)0x30000000) /*!<ACCMOD[1:0] bits (Access mode) */
\r
3772 #define FSMC_BWTR4_ACCMOD_0 ((uint32_t)0x10000000) /*!<Bit 0 */
\r
3773 #define FSMC_BWTR4_ACCMOD_1 ((uint32_t)0x20000000) /*!<Bit 1 */
\r
3775 /****************** Bit definition for FSMC_PCR2 register *******************/
\r
3776 #define FSMC_PCR2_PWAITEN ((uint32_t)0x00000002) /*!<Wait feature enable bit */
\r
3777 #define FSMC_PCR2_PBKEN ((uint32_t)0x00000004) /*!<PC Card/NAND Flash memory bank enable bit */
\r
3778 #define FSMC_PCR2_PTYP ((uint32_t)0x00000008) /*!<Memory type */
\r
3780 #define FSMC_PCR2_PWID ((uint32_t)0x00000030) /*!<PWID[1:0] bits (NAND Flash databus width) */
\r
3781 #define FSMC_PCR2_PWID_0 ((uint32_t)0x00000010) /*!<Bit 0 */
\r
3782 #define FSMC_PCR2_PWID_1 ((uint32_t)0x00000020) /*!<Bit 1 */
\r
3784 #define FSMC_PCR2_ECCEN ((uint32_t)0x00000040) /*!<ECC computation logic enable bit */
\r
3786 #define FSMC_PCR2_TCLR ((uint32_t)0x00001E00) /*!<TCLR[3:0] bits (CLE to RE delay) */
\r
3787 #define FSMC_PCR2_TCLR_0 ((uint32_t)0x00000200) /*!<Bit 0 */
\r
3788 #define FSMC_PCR2_TCLR_1 ((uint32_t)0x00000400) /*!<Bit 1 */
\r
3789 #define FSMC_PCR2_TCLR_2 ((uint32_t)0x00000800) /*!<Bit 2 */
\r
3790 #define FSMC_PCR2_TCLR_3 ((uint32_t)0x00001000) /*!<Bit 3 */
\r
3792 #define FSMC_PCR2_TAR ((uint32_t)0x0001E000) /*!<TAR[3:0] bits (ALE to RE delay) */
\r
3793 #define FSMC_PCR2_TAR_0 ((uint32_t)0x00002000) /*!<Bit 0 */
\r
3794 #define FSMC_PCR2_TAR_1 ((uint32_t)0x00004000) /*!<Bit 1 */
\r
3795 #define FSMC_PCR2_TAR_2 ((uint32_t)0x00008000) /*!<Bit 2 */
\r
3796 #define FSMC_PCR2_TAR_3 ((uint32_t)0x00010000) /*!<Bit 3 */
\r
3798 #define FSMC_PCR2_ECCPS ((uint32_t)0x000E0000) /*!<ECCPS[1:0] bits (ECC page size) */
\r
3799 #define FSMC_PCR2_ECCPS_0 ((uint32_t)0x00020000) /*!<Bit 0 */
\r
3800 #define FSMC_PCR2_ECCPS_1 ((uint32_t)0x00040000) /*!<Bit 1 */
\r
3801 #define FSMC_PCR2_ECCPS_2 ((uint32_t)0x00080000) /*!<Bit 2 */
\r
3803 /****************** Bit definition for FSMC_PCR3 register *******************/
\r
3804 #define FSMC_PCR3_PWAITEN ((uint32_t)0x00000002) /*!<Wait feature enable bit */
\r
3805 #define FSMC_PCR3_PBKEN ((uint32_t)0x00000004) /*!<PC Card/NAND Flash memory bank enable bit */
\r
3806 #define FSMC_PCR3_PTYP ((uint32_t)0x00000008) /*!<Memory type */
\r
3808 #define FSMC_PCR3_PWID ((uint32_t)0x00000030) /*!<PWID[1:0] bits (NAND Flash databus width) */
\r
3809 #define FSMC_PCR3_PWID_0 ((uint32_t)0x00000010) /*!<Bit 0 */
\r
3810 #define FSMC_PCR3_PWID_1 ((uint32_t)0x00000020) /*!<Bit 1 */
\r
3812 #define FSMC_PCR3_ECCEN ((uint32_t)0x00000040) /*!<ECC computation logic enable bit */
\r
3814 #define FSMC_PCR3_TCLR ((uint32_t)0x00001E00) /*!<TCLR[3:0] bits (CLE to RE delay) */
\r
3815 #define FSMC_PCR3_TCLR_0 ((uint32_t)0x00000200) /*!<Bit 0 */
\r
3816 #define FSMC_PCR3_TCLR_1 ((uint32_t)0x00000400) /*!<Bit 1 */
\r
3817 #define FSMC_PCR3_TCLR_2 ((uint32_t)0x00000800) /*!<Bit 2 */
\r
3818 #define FSMC_PCR3_TCLR_3 ((uint32_t)0x00001000) /*!<Bit 3 */
\r
3820 #define FSMC_PCR3_TAR ((uint32_t)0x0001E000) /*!<TAR[3:0] bits (ALE to RE delay) */
\r
3821 #define FSMC_PCR3_TAR_0 ((uint32_t)0x00002000) /*!<Bit 0 */
\r
3822 #define FSMC_PCR3_TAR_1 ((uint32_t)0x00004000) /*!<Bit 1 */
\r
3823 #define FSMC_PCR3_TAR_2 ((uint32_t)0x00008000) /*!<Bit 2 */
\r
3824 #define FSMC_PCR3_TAR_3 ((uint32_t)0x00010000) /*!<Bit 3 */
\r
3826 #define FSMC_PCR3_ECCPS ((uint32_t)0x000E0000) /*!<ECCPS[2:0] bits (ECC page size) */
\r
3827 #define FSMC_PCR3_ECCPS_0 ((uint32_t)0x00020000) /*!<Bit 0 */
\r
3828 #define FSMC_PCR3_ECCPS_1 ((uint32_t)0x00040000) /*!<Bit 1 */
\r
3829 #define FSMC_PCR3_ECCPS_2 ((uint32_t)0x00080000) /*!<Bit 2 */
\r
3831 /****************** Bit definition for FSMC_PCR4 register *******************/
\r
3832 #define FSMC_PCR4_PWAITEN ((uint32_t)0x00000002) /*!<Wait feature enable bit */
\r
3833 #define FSMC_PCR4_PBKEN ((uint32_t)0x00000004) /*!<PC Card/NAND Flash memory bank enable bit */
\r
3834 #define FSMC_PCR4_PTYP ((uint32_t)0x00000008) /*!<Memory type */
\r
3836 #define FSMC_PCR4_PWID ((uint32_t)0x00000030) /*!<PWID[1:0] bits (NAND Flash databus width) */
\r
3837 #define FSMC_PCR4_PWID_0 ((uint32_t)0x00000010) /*!<Bit 0 */
\r
3838 #define FSMC_PCR4_PWID_1 ((uint32_t)0x00000020) /*!<Bit 1 */
\r
3840 #define FSMC_PCR4_ECCEN ((uint32_t)0x00000040) /*!<ECC computation logic enable bit */
\r
3842 #define FSMC_PCR4_TCLR ((uint32_t)0x00001E00) /*!<TCLR[3:0] bits (CLE to RE delay) */
\r
3843 #define FSMC_PCR4_TCLR_0 ((uint32_t)0x00000200) /*!<Bit 0 */
\r
3844 #define FSMC_PCR4_TCLR_1 ((uint32_t)0x00000400) /*!<Bit 1 */
\r
3845 #define FSMC_PCR4_TCLR_2 ((uint32_t)0x00000800) /*!<Bit 2 */
\r
3846 #define FSMC_PCR4_TCLR_3 ((uint32_t)0x00001000) /*!<Bit 3 */
\r
3848 #define FSMC_PCR4_TAR ((uint32_t)0x0001E000) /*!<TAR[3:0] bits (ALE to RE delay) */
\r
3849 #define FSMC_PCR4_TAR_0 ((uint32_t)0x00002000) /*!<Bit 0 */
\r
3850 #define FSMC_PCR4_TAR_1 ((uint32_t)0x00004000) /*!<Bit 1 */
\r
3851 #define FSMC_PCR4_TAR_2 ((uint32_t)0x00008000) /*!<Bit 2 */
\r
3852 #define FSMC_PCR4_TAR_3 ((uint32_t)0x00010000) /*!<Bit 3 */
\r
3854 #define FSMC_PCR4_ECCPS ((uint32_t)0x000E0000) /*!<ECCPS[2:0] bits (ECC page size) */
\r
3855 #define FSMC_PCR4_ECCPS_0 ((uint32_t)0x00020000) /*!<Bit 0 */
\r
3856 #define FSMC_PCR4_ECCPS_1 ((uint32_t)0x00040000) /*!<Bit 1 */
\r
3857 #define FSMC_PCR4_ECCPS_2 ((uint32_t)0x00080000) /*!<Bit 2 */
\r
3859 /******************* Bit definition for FSMC_SR2 register *******************/
\r
3860 #define FSMC_SR2_IRS ((uint32_t)0x01) /*!<Interrupt Rising Edge status */
\r
3861 #define FSMC_SR2_ILS ((uint32_t)0x02) /*!<Interrupt Level status */
\r
3862 #define FSMC_SR2_IFS ((uint32_t)0x04) /*!<Interrupt Falling Edge status */
\r
3863 #define FSMC_SR2_IREN ((uint32_t)0x08) /*!<Interrupt Rising Edge detection Enable bit */
\r
3864 #define FSMC_SR2_ILEN ((uint32_t)0x10) /*!<Interrupt Level detection Enable bit */
\r
3865 #define FSMC_SR2_IFEN ((uint32_t)0x20) /*!<Interrupt Falling Edge detection Enable bit */
\r
3866 #define FSMC_SR2_FEMPT ((uint32_t)0x40) /*!<FIFO empty */
\r
3868 /******************* Bit definition for FSMC_SR3 register *******************/
\r
3869 #define FSMC_SR3_IRS ((uint32_t)0x01) /*!<Interrupt Rising Edge status */
\r
3870 #define FSMC_SR3_ILS ((uint32_t)0x02) /*!<Interrupt Level status */
\r
3871 #define FSMC_SR3_IFS ((uint32_t)0x04) /*!<Interrupt Falling Edge status */
\r
3872 #define FSMC_SR3_IREN ((uint32_t)0x08) /*!<Interrupt Rising Edge detection Enable bit */
\r
3873 #define FSMC_SR3_ILEN ((uint32_t)0x10) /*!<Interrupt Level detection Enable bit */
\r
3874 #define FSMC_SR3_IFEN ((uint32_t)0x20) /*!<Interrupt Falling Edge detection Enable bit */
\r
3875 #define FSMC_SR3_FEMPT ((uint32_t)0x40) /*!<FIFO empty */
\r
3877 /******************* Bit definition for FSMC_SR4 register *******************/
\r
3878 #define FSMC_SR4_IRS ((uint32_t)0x01) /*!<Interrupt Rising Edge status */
\r
3879 #define FSMC_SR4_ILS ((uint32_t)0x02) /*!<Interrupt Level status */
\r
3880 #define FSMC_SR4_IFS ((uint32_t)0x04) /*!<Interrupt Falling Edge status */
\r
3881 #define FSMC_SR4_IREN ((uint32_t)0x08) /*!<Interrupt Rising Edge detection Enable bit */
\r
3882 #define FSMC_SR4_ILEN ((uint32_t)0x10) /*!<Interrupt Level detection Enable bit */
\r
3883 #define FSMC_SR4_IFEN ((uint32_t)0x20) /*!<Interrupt Falling Edge detection Enable bit */
\r
3884 #define FSMC_SR4_FEMPT ((uint32_t)0x40) /*!<FIFO empty */
\r
3886 /****************** Bit definition for FSMC_PMEM2 register ******************/
\r
3887 #define FSMC_PMEM2_MEMSET2 ((uint32_t)0x000000FF) /*!<MEMSET2[7:0] bits (Common memory 2 setup time) */
\r
3888 #define FSMC_PMEM2_MEMSET2_0 ((uint32_t)0x00000001) /*!<Bit 0 */
\r
3889 #define FSMC_PMEM2_MEMSET2_1 ((uint32_t)0x00000002) /*!<Bit 1 */
\r
3890 #define FSMC_PMEM2_MEMSET2_2 ((uint32_t)0x00000004) /*!<Bit 2 */
\r
3891 #define FSMC_PMEM2_MEMSET2_3 ((uint32_t)0x00000008) /*!<Bit 3 */
\r
3892 #define FSMC_PMEM2_MEMSET2_4 ((uint32_t)0x00000010) /*!<Bit 4 */
\r
3893 #define FSMC_PMEM2_MEMSET2_5 ((uint32_t)0x00000020) /*!<Bit 5 */
\r
3894 #define FSMC_PMEM2_MEMSET2_6 ((uint32_t)0x00000040) /*!<Bit 6 */
\r
3895 #define FSMC_PMEM2_MEMSET2_7 ((uint32_t)0x00000080) /*!<Bit 7 */
\r
3897 #define FSMC_PMEM2_MEMWAIT2 ((uint32_t)0x0000FF00) /*!<MEMWAIT2[7:0] bits (Common memory 2 wait time) */
\r
3898 #define FSMC_PMEM2_MEMWAIT2_0 ((uint32_t)0x00000100) /*!<Bit 0 */
\r
3899 #define FSMC_PMEM2_MEMWAIT2_1 ((uint32_t)0x00000200) /*!<Bit 1 */
\r
3900 #define FSMC_PMEM2_MEMWAIT2_2 ((uint32_t)0x00000400) /*!<Bit 2 */
\r
3901 #define FSMC_PMEM2_MEMWAIT2_3 ((uint32_t)0x00000800) /*!<Bit 3 */
\r
3902 #define FSMC_PMEM2_MEMWAIT2_4 ((uint32_t)0x00001000) /*!<Bit 4 */
\r
3903 #define FSMC_PMEM2_MEMWAIT2_5 ((uint32_t)0x00002000) /*!<Bit 5 */
\r
3904 #define FSMC_PMEM2_MEMWAIT2_6 ((uint32_t)0x00004000) /*!<Bit 6 */
\r
3905 #define FSMC_PMEM2_MEMWAIT2_7 ((uint32_t)0x00008000) /*!<Bit 7 */
\r
3907 #define FSMC_PMEM2_MEMHOLD2 ((uint32_t)0x00FF0000) /*!<MEMHOLD2[7:0] bits (Common memory 2 hold time) */
\r
3908 #define FSMC_PMEM2_MEMHOLD2_0 ((uint32_t)0x00010000) /*!<Bit 0 */
\r
3909 #define FSMC_PMEM2_MEMHOLD2_1 ((uint32_t)0x00020000) /*!<Bit 1 */
\r
3910 #define FSMC_PMEM2_MEMHOLD2_2 ((uint32_t)0x00040000) /*!<Bit 2 */
\r
3911 #define FSMC_PMEM2_MEMHOLD2_3 ((uint32_t)0x00080000) /*!<Bit 3 */
\r
3912 #define FSMC_PMEM2_MEMHOLD2_4 ((uint32_t)0x00100000) /*!<Bit 4 */
\r
3913 #define FSMC_PMEM2_MEMHOLD2_5 ((uint32_t)0x00200000) /*!<Bit 5 */
\r
3914 #define FSMC_PMEM2_MEMHOLD2_6 ((uint32_t)0x00400000) /*!<Bit 6 */
\r
3915 #define FSMC_PMEM2_MEMHOLD2_7 ((uint32_t)0x00800000) /*!<Bit 7 */
\r
3917 #define FSMC_PMEM2_MEMHIZ2 ((uint32_t)0xFF000000) /*!<MEMHIZ2[7:0] bits (Common memory 2 databus HiZ time) */
\r
3918 #define FSMC_PMEM2_MEMHIZ2_0 ((uint32_t)0x01000000) /*!<Bit 0 */
\r
3919 #define FSMC_PMEM2_MEMHIZ2_1 ((uint32_t)0x02000000) /*!<Bit 1 */
\r
3920 #define FSMC_PMEM2_MEMHIZ2_2 ((uint32_t)0x04000000) /*!<Bit 2 */
\r
3921 #define FSMC_PMEM2_MEMHIZ2_3 ((uint32_t)0x08000000) /*!<Bit 3 */
\r
3922 #define FSMC_PMEM2_MEMHIZ2_4 ((uint32_t)0x10000000) /*!<Bit 4 */
\r
3923 #define FSMC_PMEM2_MEMHIZ2_5 ((uint32_t)0x20000000) /*!<Bit 5 */
\r
3924 #define FSMC_PMEM2_MEMHIZ2_6 ((uint32_t)0x40000000) /*!<Bit 6 */
\r
3925 #define FSMC_PMEM2_MEMHIZ2_7 ((uint32_t)0x80000000) /*!<Bit 7 */
\r
3927 /****************** Bit definition for FSMC_PMEM3 register ******************/
\r
3928 #define FSMC_PMEM3_MEMSET3 ((uint32_t)0x000000FF) /*!<MEMSET3[7:0] bits (Common memory 3 setup time) */
\r
3929 #define FSMC_PMEM3_MEMSET3_0 ((uint32_t)0x00000001) /*!<Bit 0 */
\r
3930 #define FSMC_PMEM3_MEMSET3_1 ((uint32_t)0x00000002) /*!<Bit 1 */
\r
3931 #define FSMC_PMEM3_MEMSET3_2 ((uint32_t)0x00000004) /*!<Bit 2 */
\r
3932 #define FSMC_PMEM3_MEMSET3_3 ((uint32_t)0x00000008) /*!<Bit 3 */
\r
3933 #define FSMC_PMEM3_MEMSET3_4 ((uint32_t)0x00000010) /*!<Bit 4 */
\r
3934 #define FSMC_PMEM3_MEMSET3_5 ((uint32_t)0x00000020) /*!<Bit 5 */
\r
3935 #define FSMC_PMEM3_MEMSET3_6 ((uint32_t)0x00000040) /*!<Bit 6 */
\r
3936 #define FSMC_PMEM3_MEMSET3_7 ((uint32_t)0x00000080) /*!<Bit 7 */
\r
3938 #define FSMC_PMEM3_MEMWAIT3 ((uint32_t)0x0000FF00) /*!<MEMWAIT3[7:0] bits (Common memory 3 wait time) */
\r
3939 #define FSMC_PMEM3_MEMWAIT3_0 ((uint32_t)0x00000100) /*!<Bit 0 */
\r
3940 #define FSMC_PMEM3_MEMWAIT3_1 ((uint32_t)0x00000200) /*!<Bit 1 */
\r
3941 #define FSMC_PMEM3_MEMWAIT3_2 ((uint32_t)0x00000400) /*!<Bit 2 */
\r
3942 #define FSMC_PMEM3_MEMWAIT3_3 ((uint32_t)0x00000800) /*!<Bit 3 */
\r
3943 #define FSMC_PMEM3_MEMWAIT3_4 ((uint32_t)0x00001000) /*!<Bit 4 */
\r
3944 #define FSMC_PMEM3_MEMWAIT3_5 ((uint32_t)0x00002000) /*!<Bit 5 */
\r
3945 #define FSMC_PMEM3_MEMWAIT3_6 ((uint32_t)0x00004000) /*!<Bit 6 */
\r
3946 #define FSMC_PMEM3_MEMWAIT3_7 ((uint32_t)0x00008000) /*!<Bit 7 */
\r
3948 #define FSMC_PMEM3_MEMHOLD3 ((uint32_t)0x00FF0000) /*!<MEMHOLD3[7:0] bits (Common memory 3 hold time) */
\r
3949 #define FSMC_PMEM3_MEMHOLD3_0 ((uint32_t)0x00010000) /*!<Bit 0 */
\r
3950 #define FSMC_PMEM3_MEMHOLD3_1 ((uint32_t)0x00020000) /*!<Bit 1 */
\r
3951 #define FSMC_PMEM3_MEMHOLD3_2 ((uint32_t)0x00040000) /*!<Bit 2 */
\r
3952 #define FSMC_PMEM3_MEMHOLD3_3 ((uint32_t)0x00080000) /*!<Bit 3 */
\r
3953 #define FSMC_PMEM3_MEMHOLD3_4 ((uint32_t)0x00100000) /*!<Bit 4 */
\r
3954 #define FSMC_PMEM3_MEMHOLD3_5 ((uint32_t)0x00200000) /*!<Bit 5 */
\r
3955 #define FSMC_PMEM3_MEMHOLD3_6 ((uint32_t)0x00400000) /*!<Bit 6 */
\r
3956 #define FSMC_PMEM3_MEMHOLD3_7 ((uint32_t)0x00800000) /*!<Bit 7 */
\r
3958 #define FSMC_PMEM3_MEMHIZ3 ((uint32_t)0xFF000000) /*!<MEMHIZ3[7:0] bits (Common memory 3 databus HiZ time) */
\r
3959 #define FSMC_PMEM3_MEMHIZ3_0 ((uint32_t)0x01000000) /*!<Bit 0 */
\r
3960 #define FSMC_PMEM3_MEMHIZ3_1 ((uint32_t)0x02000000) /*!<Bit 1 */
\r
3961 #define FSMC_PMEM3_MEMHIZ3_2 ((uint32_t)0x04000000) /*!<Bit 2 */
\r
3962 #define FSMC_PMEM3_MEMHIZ3_3 ((uint32_t)0x08000000) /*!<Bit 3 */
\r
3963 #define FSMC_PMEM3_MEMHIZ3_4 ((uint32_t)0x10000000) /*!<Bit 4 */
\r
3964 #define FSMC_PMEM3_MEMHIZ3_5 ((uint32_t)0x20000000) /*!<Bit 5 */
\r
3965 #define FSMC_PMEM3_MEMHIZ3_6 ((uint32_t)0x40000000) /*!<Bit 6 */
\r
3966 #define FSMC_PMEM3_MEMHIZ3_7 ((uint32_t)0x80000000) /*!<Bit 7 */
\r
3968 /****************** Bit definition for FSMC_PMEM4 register ******************/
\r
3969 #define FSMC_PMEM4_MEMSET4 ((uint32_t)0x000000FF) /*!<MEMSET4[7:0] bits (Common memory 4 setup time) */
\r
3970 #define FSMC_PMEM4_MEMSET4_0 ((uint32_t)0x00000001) /*!<Bit 0 */
\r
3971 #define FSMC_PMEM4_MEMSET4_1 ((uint32_t)0x00000002) /*!<Bit 1 */
\r
3972 #define FSMC_PMEM4_MEMSET4_2 ((uint32_t)0x00000004) /*!<Bit 2 */
\r
3973 #define FSMC_PMEM4_MEMSET4_3 ((uint32_t)0x00000008) /*!<Bit 3 */
\r
3974 #define FSMC_PMEM4_MEMSET4_4 ((uint32_t)0x00000010) /*!<Bit 4 */
\r
3975 #define FSMC_PMEM4_MEMSET4_5 ((uint32_t)0x00000020) /*!<Bit 5 */
\r
3976 #define FSMC_PMEM4_MEMSET4_6 ((uint32_t)0x00000040) /*!<Bit 6 */
\r
3977 #define FSMC_PMEM4_MEMSET4_7 ((uint32_t)0x00000080) /*!<Bit 7 */
\r
3979 #define FSMC_PMEM4_MEMWAIT4 ((uint32_t)0x0000FF00) /*!<MEMWAIT4[7:0] bits (Common memory 4 wait time) */
\r
3980 #define FSMC_PMEM4_MEMWAIT4_0 ((uint32_t)0x00000100) /*!<Bit 0 */
\r
3981 #define FSMC_PMEM4_MEMWAIT4_1 ((uint32_t)0x00000200) /*!<Bit 1 */
\r
3982 #define FSMC_PMEM4_MEMWAIT4_2 ((uint32_t)0x00000400) /*!<Bit 2 */
\r
3983 #define FSMC_PMEM4_MEMWAIT4_3 ((uint32_t)0x00000800) /*!<Bit 3 */
\r
3984 #define FSMC_PMEM4_MEMWAIT4_4 ((uint32_t)0x00001000) /*!<Bit 4 */
\r
3985 #define FSMC_PMEM4_MEMWAIT4_5 ((uint32_t)0x00002000) /*!<Bit 5 */
\r
3986 #define FSMC_PMEM4_MEMWAIT4_6 ((uint32_t)0x00004000) /*!<Bit 6 */
\r
3987 #define FSMC_PMEM4_MEMWAIT4_7 ((uint32_t)0x00008000) /*!<Bit 7 */
\r
3989 #define FSMC_PMEM4_MEMHOLD4 ((uint32_t)0x00FF0000) /*!<MEMHOLD4[7:0] bits (Common memory 4 hold time) */
\r
3990 #define FSMC_PMEM4_MEMHOLD4_0 ((uint32_t)0x00010000) /*!<Bit 0 */
\r
3991 #define FSMC_PMEM4_MEMHOLD4_1 ((uint32_t)0x00020000) /*!<Bit 1 */
\r
3992 #define FSMC_PMEM4_MEMHOLD4_2 ((uint32_t)0x00040000) /*!<Bit 2 */
\r
3993 #define FSMC_PMEM4_MEMHOLD4_3 ((uint32_t)0x00080000) /*!<Bit 3 */
\r
3994 #define FSMC_PMEM4_MEMHOLD4_4 ((uint32_t)0x00100000) /*!<Bit 4 */
\r
3995 #define FSMC_PMEM4_MEMHOLD4_5 ((uint32_t)0x00200000) /*!<Bit 5 */
\r
3996 #define FSMC_PMEM4_MEMHOLD4_6 ((uint32_t)0x00400000) /*!<Bit 6 */
\r
3997 #define FSMC_PMEM4_MEMHOLD4_7 ((uint32_t)0x00800000) /*!<Bit 7 */
\r
3999 #define FSMC_PMEM4_MEMHIZ4 ((uint32_t)0xFF000000) /*!<MEMHIZ4[7:0] bits (Common memory 4 databus HiZ time) */
\r
4000 #define FSMC_PMEM4_MEMHIZ4_0 ((uint32_t)0x01000000) /*!<Bit 0 */
\r
4001 #define FSMC_PMEM4_MEMHIZ4_1 ((uint32_t)0x02000000) /*!<Bit 1 */
\r
4002 #define FSMC_PMEM4_MEMHIZ4_2 ((uint32_t)0x04000000) /*!<Bit 2 */
\r
4003 #define FSMC_PMEM4_MEMHIZ4_3 ((uint32_t)0x08000000) /*!<Bit 3 */
\r
4004 #define FSMC_PMEM4_MEMHIZ4_4 ((uint32_t)0x10000000) /*!<Bit 4 */
\r
4005 #define FSMC_PMEM4_MEMHIZ4_5 ((uint32_t)0x20000000) /*!<Bit 5 */
\r
4006 #define FSMC_PMEM4_MEMHIZ4_6 ((uint32_t)0x40000000) /*!<Bit 6 */
\r
4007 #define FSMC_PMEM4_MEMHIZ4_7 ((uint32_t)0x80000000) /*!<Bit 7 */
\r
4009 /****************** Bit definition for FSMC_PATT2 register ******************/
\r
4010 #define FSMC_PATT2_ATTSET2 ((uint32_t)0x000000FF) /*!<ATTSET2[7:0] bits (Attribute memory 2 setup time) */
\r
4011 #define FSMC_PATT2_ATTSET2_0 ((uint32_t)0x00000001) /*!<Bit 0 */
\r
4012 #define FSMC_PATT2_ATTSET2_1 ((uint32_t)0x00000002) /*!<Bit 1 */
\r
4013 #define FSMC_PATT2_ATTSET2_2 ((uint32_t)0x00000004) /*!<Bit 2 */
\r
4014 #define FSMC_PATT2_ATTSET2_3 ((uint32_t)0x00000008) /*!<Bit 3 */
\r
4015 #define FSMC_PATT2_ATTSET2_4 ((uint32_t)0x00000010) /*!<Bit 4 */
\r
4016 #define FSMC_PATT2_ATTSET2_5 ((uint32_t)0x00000020) /*!<Bit 5 */
\r
4017 #define FSMC_PATT2_ATTSET2_6 ((uint32_t)0x00000040) /*!<Bit 6 */
\r
4018 #define FSMC_PATT2_ATTSET2_7 ((uint32_t)0x00000080) /*!<Bit 7 */
\r
4020 #define FSMC_PATT2_ATTWAIT2 ((uint32_t)0x0000FF00) /*!<ATTWAIT2[7:0] bits (Attribute memory 2 wait time) */
\r
4021 #define FSMC_PATT2_ATTWAIT2_0 ((uint32_t)0x00000100) /*!<Bit 0 */
\r
4022 #define FSMC_PATT2_ATTWAIT2_1 ((uint32_t)0x00000200) /*!<Bit 1 */
\r
4023 #define FSMC_PATT2_ATTWAIT2_2 ((uint32_t)0x00000400) /*!<Bit 2 */
\r
4024 #define FSMC_PATT2_ATTWAIT2_3 ((uint32_t)0x00000800) /*!<Bit 3 */
\r
4025 #define FSMC_PATT2_ATTWAIT2_4 ((uint32_t)0x00001000) /*!<Bit 4 */
\r
4026 #define FSMC_PATT2_ATTWAIT2_5 ((uint32_t)0x00002000) /*!<Bit 5 */
\r
4027 #define FSMC_PATT2_ATTWAIT2_6 ((uint32_t)0x00004000) /*!<Bit 6 */
\r
4028 #define FSMC_PATT2_ATTWAIT2_7 ((uint32_t)0x00008000) /*!<Bit 7 */
\r
4030 #define FSMC_PATT2_ATTHOLD2 ((uint32_t)0x00FF0000) /*!<ATTHOLD2[7:0] bits (Attribute memory 2 hold time) */
\r
4031 #define FSMC_PATT2_ATTHOLD2_0 ((uint32_t)0x00010000) /*!<Bit 0 */
\r
4032 #define FSMC_PATT2_ATTHOLD2_1 ((uint32_t)0x00020000) /*!<Bit 1 */
\r
4033 #define FSMC_PATT2_ATTHOLD2_2 ((uint32_t)0x00040000) /*!<Bit 2 */
\r
4034 #define FSMC_PATT2_ATTHOLD2_3 ((uint32_t)0x00080000) /*!<Bit 3 */
\r
4035 #define FSMC_PATT2_ATTHOLD2_4 ((uint32_t)0x00100000) /*!<Bit 4 */
\r
4036 #define FSMC_PATT2_ATTHOLD2_5 ((uint32_t)0x00200000) /*!<Bit 5 */
\r
4037 #define FSMC_PATT2_ATTHOLD2_6 ((uint32_t)0x00400000) /*!<Bit 6 */
\r
4038 #define FSMC_PATT2_ATTHOLD2_7 ((uint32_t)0x00800000) /*!<Bit 7 */
\r
4040 #define FSMC_PATT2_ATTHIZ2 ((uint32_t)0xFF000000) /*!<ATTHIZ2[7:0] bits (Attribute memory 2 databus HiZ time) */
\r
4041 #define FSMC_PATT2_ATTHIZ2_0 ((uint32_t)0x01000000) /*!<Bit 0 */
\r
4042 #define FSMC_PATT2_ATTHIZ2_1 ((uint32_t)0x02000000) /*!<Bit 1 */
\r
4043 #define FSMC_PATT2_ATTHIZ2_2 ((uint32_t)0x04000000) /*!<Bit 2 */
\r
4044 #define FSMC_PATT2_ATTHIZ2_3 ((uint32_t)0x08000000) /*!<Bit 3 */
\r
4045 #define FSMC_PATT2_ATTHIZ2_4 ((uint32_t)0x10000000) /*!<Bit 4 */
\r
4046 #define FSMC_PATT2_ATTHIZ2_5 ((uint32_t)0x20000000) /*!<Bit 5 */
\r
4047 #define FSMC_PATT2_ATTHIZ2_6 ((uint32_t)0x40000000) /*!<Bit 6 */
\r
4048 #define FSMC_PATT2_ATTHIZ2_7 ((uint32_t)0x80000000) /*!<Bit 7 */
\r
4050 /****************** Bit definition for FSMC_PATT3 register ******************/
\r
4051 #define FSMC_PATT3_ATTSET3 ((uint32_t)0x000000FF) /*!<ATTSET3[7:0] bits (Attribute memory 3 setup time) */
\r
4052 #define FSMC_PATT3_ATTSET3_0 ((uint32_t)0x00000001) /*!<Bit 0 */
\r
4053 #define FSMC_PATT3_ATTSET3_1 ((uint32_t)0x00000002) /*!<Bit 1 */
\r
4054 #define FSMC_PATT3_ATTSET3_2 ((uint32_t)0x00000004) /*!<Bit 2 */
\r
4055 #define FSMC_PATT3_ATTSET3_3 ((uint32_t)0x00000008) /*!<Bit 3 */
\r
4056 #define FSMC_PATT3_ATTSET3_4 ((uint32_t)0x00000010) /*!<Bit 4 */
\r
4057 #define FSMC_PATT3_ATTSET3_5 ((uint32_t)0x00000020) /*!<Bit 5 */
\r
4058 #define FSMC_PATT3_ATTSET3_6 ((uint32_t)0x00000040) /*!<Bit 6 */
\r
4059 #define FSMC_PATT3_ATTSET3_7 ((uint32_t)0x00000080) /*!<Bit 7 */
\r
4061 #define FSMC_PATT3_ATTWAIT3 ((uint32_t)0x0000FF00) /*!<ATTWAIT3[7:0] bits (Attribute memory 3 wait time) */
\r
4062 #define FSMC_PATT3_ATTWAIT3_0 ((uint32_t)0x00000100) /*!<Bit 0 */
\r
4063 #define FSMC_PATT3_ATTWAIT3_1 ((uint32_t)0x00000200) /*!<Bit 1 */
\r
4064 #define FSMC_PATT3_ATTWAIT3_2 ((uint32_t)0x00000400) /*!<Bit 2 */
\r
4065 #define FSMC_PATT3_ATTWAIT3_3 ((uint32_t)0x00000800) /*!<Bit 3 */
\r
4066 #define FSMC_PATT3_ATTWAIT3_4 ((uint32_t)0x00001000) /*!<Bit 4 */
\r
4067 #define FSMC_PATT3_ATTWAIT3_5 ((uint32_t)0x00002000) /*!<Bit 5 */
\r
4068 #define FSMC_PATT3_ATTWAIT3_6 ((uint32_t)0x00004000) /*!<Bit 6 */
\r
4069 #define FSMC_PATT3_ATTWAIT3_7 ((uint32_t)0x00008000) /*!<Bit 7 */
\r
4071 #define FSMC_PATT3_ATTHOLD3 ((uint32_t)0x00FF0000) /*!<ATTHOLD3[7:0] bits (Attribute memory 3 hold time) */
\r
4072 #define FSMC_PATT3_ATTHOLD3_0 ((uint32_t)0x00010000) /*!<Bit 0 */
\r
4073 #define FSMC_PATT3_ATTHOLD3_1 ((uint32_t)0x00020000) /*!<Bit 1 */
\r
4074 #define FSMC_PATT3_ATTHOLD3_2 ((uint32_t)0x00040000) /*!<Bit 2 */
\r
4075 #define FSMC_PATT3_ATTHOLD3_3 ((uint32_t)0x00080000) /*!<Bit 3 */
\r
4076 #define FSMC_PATT3_ATTHOLD3_4 ((uint32_t)0x00100000) /*!<Bit 4 */
\r
4077 #define FSMC_PATT3_ATTHOLD3_5 ((uint32_t)0x00200000) /*!<Bit 5 */
\r
4078 #define FSMC_PATT3_ATTHOLD3_6 ((uint32_t)0x00400000) /*!<Bit 6 */
\r
4079 #define FSMC_PATT3_ATTHOLD3_7 ((uint32_t)0x00800000) /*!<Bit 7 */
\r
4081 #define FSMC_PATT3_ATTHIZ3 ((uint32_t)0xFF000000) /*!<ATTHIZ3[7:0] bits (Attribute memory 3 databus HiZ time) */
\r
4082 #define FSMC_PATT3_ATTHIZ3_0 ((uint32_t)0x01000000) /*!<Bit 0 */
\r
4083 #define FSMC_PATT3_ATTHIZ3_1 ((uint32_t)0x02000000) /*!<Bit 1 */
\r
4084 #define FSMC_PATT3_ATTHIZ3_2 ((uint32_t)0x04000000) /*!<Bit 2 */
\r
4085 #define FSMC_PATT3_ATTHIZ3_3 ((uint32_t)0x08000000) /*!<Bit 3 */
\r
4086 #define FSMC_PATT3_ATTHIZ3_4 ((uint32_t)0x10000000) /*!<Bit 4 */
\r
4087 #define FSMC_PATT3_ATTHIZ3_5 ((uint32_t)0x20000000) /*!<Bit 5 */
\r
4088 #define FSMC_PATT3_ATTHIZ3_6 ((uint32_t)0x40000000) /*!<Bit 6 */
\r
4089 #define FSMC_PATT3_ATTHIZ3_7 ((uint32_t)0x80000000) /*!<Bit 7 */
\r
4091 /****************** Bit definition for FSMC_PATT4 register ******************/
\r
4092 #define FSMC_PATT4_ATTSET4 ((uint32_t)0x000000FF) /*!<ATTSET4[7:0] bits (Attribute memory 4 setup time) */
\r
4093 #define FSMC_PATT4_ATTSET4_0 ((uint32_t)0x00000001) /*!<Bit 0 */
\r
4094 #define FSMC_PATT4_ATTSET4_1 ((uint32_t)0x00000002) /*!<Bit 1 */
\r
4095 #define FSMC_PATT4_ATTSET4_2 ((uint32_t)0x00000004) /*!<Bit 2 */
\r
4096 #define FSMC_PATT4_ATTSET4_3 ((uint32_t)0x00000008) /*!<Bit 3 */
\r
4097 #define FSMC_PATT4_ATTSET4_4 ((uint32_t)0x00000010) /*!<Bit 4 */
\r
4098 #define FSMC_PATT4_ATTSET4_5 ((uint32_t)0x00000020) /*!<Bit 5 */
\r
4099 #define FSMC_PATT4_ATTSET4_6 ((uint32_t)0x00000040) /*!<Bit 6 */
\r
4100 #define FSMC_PATT4_ATTSET4_7 ((uint32_t)0x00000080) /*!<Bit 7 */
\r
4102 #define FSMC_PATT4_ATTWAIT4 ((uint32_t)0x0000FF00) /*!<ATTWAIT4[7:0] bits (Attribute memory 4 wait time) */
\r
4103 #define FSMC_PATT4_ATTWAIT4_0 ((uint32_t)0x00000100) /*!<Bit 0 */
\r
4104 #define FSMC_PATT4_ATTWAIT4_1 ((uint32_t)0x00000200) /*!<Bit 1 */
\r
4105 #define FSMC_PATT4_ATTWAIT4_2 ((uint32_t)0x00000400) /*!<Bit 2 */
\r
4106 #define FSMC_PATT4_ATTWAIT4_3 ((uint32_t)0x00000800) /*!<Bit 3 */
\r
4107 #define FSMC_PATT4_ATTWAIT4_4 ((uint32_t)0x00001000) /*!<Bit 4 */
\r
4108 #define FSMC_PATT4_ATTWAIT4_5 ((uint32_t)0x00002000) /*!<Bit 5 */
\r
4109 #define FSMC_PATT4_ATTWAIT4_6 ((uint32_t)0x00004000) /*!<Bit 6 */
\r
4110 #define FSMC_PATT4_ATTWAIT4_7 ((uint32_t)0x00008000) /*!<Bit 7 */
\r
4112 #define FSMC_PATT4_ATTHOLD4 ((uint32_t)0x00FF0000) /*!<ATTHOLD4[7:0] bits (Attribute memory 4 hold time) */
\r
4113 #define FSMC_PATT4_ATTHOLD4_0 ((uint32_t)0x00010000) /*!<Bit 0 */
\r
4114 #define FSMC_PATT4_ATTHOLD4_1 ((uint32_t)0x00020000) /*!<Bit 1 */
\r
4115 #define FSMC_PATT4_ATTHOLD4_2 ((uint32_t)0x00040000) /*!<Bit 2 */
\r
4116 #define FSMC_PATT4_ATTHOLD4_3 ((uint32_t)0x00080000) /*!<Bit 3 */
\r
4117 #define FSMC_PATT4_ATTHOLD4_4 ((uint32_t)0x00100000) /*!<Bit 4 */
\r
4118 #define FSMC_PATT4_ATTHOLD4_5 ((uint32_t)0x00200000) /*!<Bit 5 */
\r
4119 #define FSMC_PATT4_ATTHOLD4_6 ((uint32_t)0x00400000) /*!<Bit 6 */
\r
4120 #define FSMC_PATT4_ATTHOLD4_7 ((uint32_t)0x00800000) /*!<Bit 7 */
\r
4122 #define FSMC_PATT4_ATTHIZ4 ((uint32_t)0xFF000000) /*!<ATTHIZ4[7:0] bits (Attribute memory 4 databus HiZ time) */
\r
4123 #define FSMC_PATT4_ATTHIZ4_0 ((uint32_t)0x01000000) /*!<Bit 0 */
\r
4124 #define FSMC_PATT4_ATTHIZ4_1 ((uint32_t)0x02000000) /*!<Bit 1 */
\r
4125 #define FSMC_PATT4_ATTHIZ4_2 ((uint32_t)0x04000000) /*!<Bit 2 */
\r
4126 #define FSMC_PATT4_ATTHIZ4_3 ((uint32_t)0x08000000) /*!<Bit 3 */
\r
4127 #define FSMC_PATT4_ATTHIZ4_4 ((uint32_t)0x10000000) /*!<Bit 4 */
\r
4128 #define FSMC_PATT4_ATTHIZ4_5 ((uint32_t)0x20000000) /*!<Bit 5 */
\r
4129 #define FSMC_PATT4_ATTHIZ4_6 ((uint32_t)0x40000000) /*!<Bit 6 */
\r
4130 #define FSMC_PATT4_ATTHIZ4_7 ((uint32_t)0x80000000) /*!<Bit 7 */
\r
4132 /****************** Bit definition for FSMC_PIO4 register *******************/
\r
4133 #define FSMC_PIO4_IOSET4 ((uint32_t)0x000000FF) /*!<IOSET4[7:0] bits (I/O 4 setup time) */
\r
4134 #define FSMC_PIO4_IOSET4_0 ((uint32_t)0x00000001) /*!<Bit 0 */
\r
4135 #define FSMC_PIO4_IOSET4_1 ((uint32_t)0x00000002) /*!<Bit 1 */
\r
4136 #define FSMC_PIO4_IOSET4_2 ((uint32_t)0x00000004) /*!<Bit 2 */
\r
4137 #define FSMC_PIO4_IOSET4_3 ((uint32_t)0x00000008) /*!<Bit 3 */
\r
4138 #define FSMC_PIO4_IOSET4_4 ((uint32_t)0x00000010) /*!<Bit 4 */
\r
4139 #define FSMC_PIO4_IOSET4_5 ((uint32_t)0x00000020) /*!<Bit 5 */
\r
4140 #define FSMC_PIO4_IOSET4_6 ((uint32_t)0x00000040) /*!<Bit 6 */
\r
4141 #define FSMC_PIO4_IOSET4_7 ((uint32_t)0x00000080) /*!<Bit 7 */
\r
4143 #define FSMC_PIO4_IOWAIT4 ((uint32_t)0x0000FF00) /*!<IOWAIT4[7:0] bits (I/O 4 wait time) */
\r
4144 #define FSMC_PIO4_IOWAIT4_0 ((uint32_t)0x00000100) /*!<Bit 0 */
\r
4145 #define FSMC_PIO4_IOWAIT4_1 ((uint32_t)0x00000200) /*!<Bit 1 */
\r
4146 #define FSMC_PIO4_IOWAIT4_2 ((uint32_t)0x00000400) /*!<Bit 2 */
\r
4147 #define FSMC_PIO4_IOWAIT4_3 ((uint32_t)0x00000800) /*!<Bit 3 */
\r
4148 #define FSMC_PIO4_IOWAIT4_4 ((uint32_t)0x00001000) /*!<Bit 4 */
\r
4149 #define FSMC_PIO4_IOWAIT4_5 ((uint32_t)0x00002000) /*!<Bit 5 */
\r
4150 #define FSMC_PIO4_IOWAIT4_6 ((uint32_t)0x00004000) /*!<Bit 6 */
\r
4151 #define FSMC_PIO4_IOWAIT4_7 ((uint32_t)0x00008000) /*!<Bit 7 */
\r
4153 #define FSMC_PIO4_IOHOLD4 ((uint32_t)0x00FF0000) /*!<IOHOLD4[7:0] bits (I/O 4 hold time) */
\r
4154 #define FSMC_PIO4_IOHOLD4_0 ((uint32_t)0x00010000) /*!<Bit 0 */
\r
4155 #define FSMC_PIO4_IOHOLD4_1 ((uint32_t)0x00020000) /*!<Bit 1 */
\r
4156 #define FSMC_PIO4_IOHOLD4_2 ((uint32_t)0x00040000) /*!<Bit 2 */
\r
4157 #define FSMC_PIO4_IOHOLD4_3 ((uint32_t)0x00080000) /*!<Bit 3 */
\r
4158 #define FSMC_PIO4_IOHOLD4_4 ((uint32_t)0x00100000) /*!<Bit 4 */
\r
4159 #define FSMC_PIO4_IOHOLD4_5 ((uint32_t)0x00200000) /*!<Bit 5 */
\r
4160 #define FSMC_PIO4_IOHOLD4_6 ((uint32_t)0x00400000) /*!<Bit 6 */
\r
4161 #define FSMC_PIO4_IOHOLD4_7 ((uint32_t)0x00800000) /*!<Bit 7 */
\r
4163 #define FSMC_PIO4_IOHIZ4 ((uint32_t)0xFF000000) /*!<IOHIZ4[7:0] bits (I/O 4 databus HiZ time) */
\r
4164 #define FSMC_PIO4_IOHIZ4_0 ((uint32_t)0x01000000) /*!<Bit 0 */
\r
4165 #define FSMC_PIO4_IOHIZ4_1 ((uint32_t)0x02000000) /*!<Bit 1 */
\r
4166 #define FSMC_PIO4_IOHIZ4_2 ((uint32_t)0x04000000) /*!<Bit 2 */
\r
4167 #define FSMC_PIO4_IOHIZ4_3 ((uint32_t)0x08000000) /*!<Bit 3 */
\r
4168 #define FSMC_PIO4_IOHIZ4_4 ((uint32_t)0x10000000) /*!<Bit 4 */
\r
4169 #define FSMC_PIO4_IOHIZ4_5 ((uint32_t)0x20000000) /*!<Bit 5 */
\r
4170 #define FSMC_PIO4_IOHIZ4_6 ((uint32_t)0x40000000) /*!<Bit 6 */
\r
4171 #define FSMC_PIO4_IOHIZ4_7 ((uint32_t)0x80000000) /*!<Bit 7 */
\r
4173 /****************** Bit definition for FSMC_ECCR2 register ******************/
\r
4174 #define FSMC_ECCR2_ECC2 ((uint32_t)0xFFFFFFFF) /*!<ECC result */
\r
4176 /****************** Bit definition for FSMC_ECCR3 register ******************/
\r
4177 #define FSMC_ECCR3_ECC3 ((uint32_t)0xFFFFFFFF) /*!<ECC result */
\r
4179 /******************************************************************************/
\r
4181 /* General Purpose I/O */
\r
4183 /******************************************************************************/
\r
4184 /****************** Bits definition for GPIO_MODER register *****************/
\r
4185 #define GPIO_MODER_MODER0 ((uint32_t)0x00000003)
\r
4186 #define GPIO_MODER_MODER0_0 ((uint32_t)0x00000001)
\r
4187 #define GPIO_MODER_MODER0_1 ((uint32_t)0x00000002)
\r
4189 #define GPIO_MODER_MODER1 ((uint32_t)0x0000000C)
\r
4190 #define GPIO_MODER_MODER1_0 ((uint32_t)0x00000004)
\r
4191 #define GPIO_MODER_MODER1_1 ((uint32_t)0x00000008)
\r
4193 #define GPIO_MODER_MODER2 ((uint32_t)0x00000030)
\r
4194 #define GPIO_MODER_MODER2_0 ((uint32_t)0x00000010)
\r
4195 #define GPIO_MODER_MODER2_1 ((uint32_t)0x00000020)
\r
4197 #define GPIO_MODER_MODER3 ((uint32_t)0x000000C0)
\r
4198 #define GPIO_MODER_MODER3_0 ((uint32_t)0x00000040)
\r
4199 #define GPIO_MODER_MODER3_1 ((uint32_t)0x00000080)
\r
4201 #define GPIO_MODER_MODER4 ((uint32_t)0x00000300)
\r
4202 #define GPIO_MODER_MODER4_0 ((uint32_t)0x00000100)
\r
4203 #define GPIO_MODER_MODER4_1 ((uint32_t)0x00000200)
\r
4205 #define GPIO_MODER_MODER5 ((uint32_t)0x00000C00)
\r
4206 #define GPIO_MODER_MODER5_0 ((uint32_t)0x00000400)
\r
4207 #define GPIO_MODER_MODER5_1 ((uint32_t)0x00000800)
\r
4209 #define GPIO_MODER_MODER6 ((uint32_t)0x00003000)
\r
4210 #define GPIO_MODER_MODER6_0 ((uint32_t)0x00001000)
\r
4211 #define GPIO_MODER_MODER6_1 ((uint32_t)0x00002000)
\r
4213 #define GPIO_MODER_MODER7 ((uint32_t)0x0000C000)
\r
4214 #define GPIO_MODER_MODER7_0 ((uint32_t)0x00004000)
\r
4215 #define GPIO_MODER_MODER7_1 ((uint32_t)0x00008000)
\r
4217 #define GPIO_MODER_MODER8 ((uint32_t)0x00030000)
\r
4218 #define GPIO_MODER_MODER8_0 ((uint32_t)0x00010000)
\r
4219 #define GPIO_MODER_MODER8_1 ((uint32_t)0x00020000)
\r
4221 #define GPIO_MODER_MODER9 ((uint32_t)0x000C0000)
\r
4222 #define GPIO_MODER_MODER9_0 ((uint32_t)0x00040000)
\r
4223 #define GPIO_MODER_MODER9_1 ((uint32_t)0x00080000)
\r
4225 #define GPIO_MODER_MODER10 ((uint32_t)0x00300000)
\r
4226 #define GPIO_MODER_MODER10_0 ((uint32_t)0x00100000)
\r
4227 #define GPIO_MODER_MODER10_1 ((uint32_t)0x00200000)
\r
4229 #define GPIO_MODER_MODER11 ((uint32_t)0x00C00000)
\r
4230 #define GPIO_MODER_MODER11_0 ((uint32_t)0x00400000)
\r
4231 #define GPIO_MODER_MODER11_1 ((uint32_t)0x00800000)
\r
4233 #define GPIO_MODER_MODER12 ((uint32_t)0x03000000)
\r
4234 #define GPIO_MODER_MODER12_0 ((uint32_t)0x01000000)
\r
4235 #define GPIO_MODER_MODER12_1 ((uint32_t)0x02000000)
\r
4237 #define GPIO_MODER_MODER13 ((uint32_t)0x0C000000)
\r
4238 #define GPIO_MODER_MODER13_0 ((uint32_t)0x04000000)
\r
4239 #define GPIO_MODER_MODER13_1 ((uint32_t)0x08000000)
\r
4241 #define GPIO_MODER_MODER14 ((uint32_t)0x30000000)
\r
4242 #define GPIO_MODER_MODER14_0 ((uint32_t)0x10000000)
\r
4243 #define GPIO_MODER_MODER14_1 ((uint32_t)0x20000000)
\r
4245 #define GPIO_MODER_MODER15 ((uint32_t)0xC0000000)
\r
4246 #define GPIO_MODER_MODER15_0 ((uint32_t)0x40000000)
\r
4247 #define GPIO_MODER_MODER15_1 ((uint32_t)0x80000000)
\r
4249 /****************** Bits definition for GPIO_OTYPER register ****************/
\r
4250 #define GPIO_OTYPER_OT_0 ((uint32_t)0x00000001)
\r
4251 #define GPIO_OTYPER_OT_1 ((uint32_t)0x00000002)
\r
4252 #define GPIO_OTYPER_OT_2 ((uint32_t)0x00000004)
\r
4253 #define GPIO_OTYPER_OT_3 ((uint32_t)0x00000008)
\r
4254 #define GPIO_OTYPER_OT_4 ((uint32_t)0x00000010)
\r
4255 #define GPIO_OTYPER_OT_5 ((uint32_t)0x00000020)
\r
4256 #define GPIO_OTYPER_OT_6 ((uint32_t)0x00000040)
\r
4257 #define GPIO_OTYPER_OT_7 ((uint32_t)0x00000080)
\r
4258 #define GPIO_OTYPER_OT_8 ((uint32_t)0x00000100)
\r
4259 #define GPIO_OTYPER_OT_9 ((uint32_t)0x00000200)
\r
4260 #define GPIO_OTYPER_OT_10 ((uint32_t)0x00000400)
\r
4261 #define GPIO_OTYPER_OT_11 ((uint32_t)0x00000800)
\r
4262 #define GPIO_OTYPER_OT_12 ((uint32_t)0x00001000)
\r
4263 #define GPIO_OTYPER_OT_13 ((uint32_t)0x00002000)
\r
4264 #define GPIO_OTYPER_OT_14 ((uint32_t)0x00004000)
\r
4265 #define GPIO_OTYPER_OT_15 ((uint32_t)0x00008000)
\r
4267 /****************** Bits definition for GPIO_OSPEEDR register ***************/
\r
4268 #define GPIO_OSPEEDER_OSPEEDR0 ((uint32_t)0x00000003)
\r
4269 #define GPIO_OSPEEDER_OSPEEDR0_0 ((uint32_t)0x00000001)
\r
4270 #define GPIO_OSPEEDER_OSPEEDR0_1 ((uint32_t)0x00000002)
\r
4272 #define GPIO_OSPEEDER_OSPEEDR1 ((uint32_t)0x0000000C)
\r
4273 #define GPIO_OSPEEDER_OSPEEDR1_0 ((uint32_t)0x00000004)
\r
4274 #define GPIO_OSPEEDER_OSPEEDR1_1 ((uint32_t)0x00000008)
\r
4276 #define GPIO_OSPEEDER_OSPEEDR2 ((uint32_t)0x00000030)
\r
4277 #define GPIO_OSPEEDER_OSPEEDR2_0 ((uint32_t)0x00000010)
\r
4278 #define GPIO_OSPEEDER_OSPEEDR2_1 ((uint32_t)0x00000020)
\r
4280 #define GPIO_OSPEEDER_OSPEEDR3 ((uint32_t)0x000000C0)
\r
4281 #define GPIO_OSPEEDER_OSPEEDR3_0 ((uint32_t)0x00000040)
\r
4282 #define GPIO_OSPEEDER_OSPEEDR3_1 ((uint32_t)0x00000080)
\r
4284 #define GPIO_OSPEEDER_OSPEEDR4 ((uint32_t)0x00000300)
\r
4285 #define GPIO_OSPEEDER_OSPEEDR4_0 ((uint32_t)0x00000100)
\r
4286 #define GPIO_OSPEEDER_OSPEEDR4_1 ((uint32_t)0x00000200)
\r
4288 #define GPIO_OSPEEDER_OSPEEDR5 ((uint32_t)0x00000C00)
\r
4289 #define GPIO_OSPEEDER_OSPEEDR5_0 ((uint32_t)0x00000400)
\r
4290 #define GPIO_OSPEEDER_OSPEEDR5_1 ((uint32_t)0x00000800)
\r
4292 #define GPIO_OSPEEDER_OSPEEDR6 ((uint32_t)0x00003000)
\r
4293 #define GPIO_OSPEEDER_OSPEEDR6_0 ((uint32_t)0x00001000)
\r
4294 #define GPIO_OSPEEDER_OSPEEDR6_1 ((uint32_t)0x00002000)
\r
4296 #define GPIO_OSPEEDER_OSPEEDR7 ((uint32_t)0x0000C000)
\r
4297 #define GPIO_OSPEEDER_OSPEEDR7_0 ((uint32_t)0x00004000)
\r
4298 #define GPIO_OSPEEDER_OSPEEDR7_1 ((uint32_t)0x00008000)
\r
4300 #define GPIO_OSPEEDER_OSPEEDR8 ((uint32_t)0x00030000)
\r
4301 #define GPIO_OSPEEDER_OSPEEDR8_0 ((uint32_t)0x00010000)
\r
4302 #define GPIO_OSPEEDER_OSPEEDR8_1 ((uint32_t)0x00020000)
\r
4304 #define GPIO_OSPEEDER_OSPEEDR9 ((uint32_t)0x000C0000)
\r
4305 #define GPIO_OSPEEDER_OSPEEDR9_0 ((uint32_t)0x00040000)
\r
4306 #define GPIO_OSPEEDER_OSPEEDR9_1 ((uint32_t)0x00080000)
\r
4308 #define GPIO_OSPEEDER_OSPEEDR10 ((uint32_t)0x00300000)
\r
4309 #define GPIO_OSPEEDER_OSPEEDR10_0 ((uint32_t)0x00100000)
\r
4310 #define GPIO_OSPEEDER_OSPEEDR10_1 ((uint32_t)0x00200000)
\r
4312 #define GPIO_OSPEEDER_OSPEEDR11 ((uint32_t)0x00C00000)
\r
4313 #define GPIO_OSPEEDER_OSPEEDR11_0 ((uint32_t)0x00400000)
\r
4314 #define GPIO_OSPEEDER_OSPEEDR11_1 ((uint32_t)0x00800000)
\r
4316 #define GPIO_OSPEEDER_OSPEEDR12 ((uint32_t)0x03000000)
\r
4317 #define GPIO_OSPEEDER_OSPEEDR12_0 ((uint32_t)0x01000000)
\r
4318 #define GPIO_OSPEEDER_OSPEEDR12_1 ((uint32_t)0x02000000)
\r
4320 #define GPIO_OSPEEDER_OSPEEDR13 ((uint32_t)0x0C000000)
\r
4321 #define GPIO_OSPEEDER_OSPEEDR13_0 ((uint32_t)0x04000000)
\r
4322 #define GPIO_OSPEEDER_OSPEEDR13_1 ((uint32_t)0x08000000)
\r
4324 #define GPIO_OSPEEDER_OSPEEDR14 ((uint32_t)0x30000000)
\r
4325 #define GPIO_OSPEEDER_OSPEEDR14_0 ((uint32_t)0x10000000)
\r
4326 #define GPIO_OSPEEDER_OSPEEDR14_1 ((uint32_t)0x20000000)
\r
4328 #define GPIO_OSPEEDER_OSPEEDR15 ((uint32_t)0xC0000000)
\r
4329 #define GPIO_OSPEEDER_OSPEEDR15_0 ((uint32_t)0x40000000)
\r
4330 #define GPIO_OSPEEDER_OSPEEDR15_1 ((uint32_t)0x80000000)
\r
4332 /****************** Bits definition for GPIO_PUPDR register *****************/
\r
4333 #define GPIO_PUPDR_PUPDR0 ((uint32_t)0x00000003)
\r
4334 #define GPIO_PUPDR_PUPDR0_0 ((uint32_t)0x00000001)
\r
4335 #define GPIO_PUPDR_PUPDR0_1 ((uint32_t)0x00000002)
\r
4337 #define GPIO_PUPDR_PUPDR1 ((uint32_t)0x0000000C)
\r
4338 #define GPIO_PUPDR_PUPDR1_0 ((uint32_t)0x00000004)
\r
4339 #define GPIO_PUPDR_PUPDR1_1 ((uint32_t)0x00000008)
\r
4341 #define GPIO_PUPDR_PUPDR2 ((uint32_t)0x00000030)
\r
4342 #define GPIO_PUPDR_PUPDR2_0 ((uint32_t)0x00000010)
\r
4343 #define GPIO_PUPDR_PUPDR2_1 ((uint32_t)0x00000020)
\r
4345 #define GPIO_PUPDR_PUPDR3 ((uint32_t)0x000000C0)
\r
4346 #define GPIO_PUPDR_PUPDR3_0 ((uint32_t)0x00000040)
\r
4347 #define GPIO_PUPDR_PUPDR3_1 ((uint32_t)0x00000080)
\r
4349 #define GPIO_PUPDR_PUPDR4 ((uint32_t)0x00000300)
\r
4350 #define GPIO_PUPDR_PUPDR4_0 ((uint32_t)0x00000100)
\r
4351 #define GPIO_PUPDR_PUPDR4_1 ((uint32_t)0x00000200)
\r
4353 #define GPIO_PUPDR_PUPDR5 ((uint32_t)0x00000C00)
\r
4354 #define GPIO_PUPDR_PUPDR5_0 ((uint32_t)0x00000400)
\r
4355 #define GPIO_PUPDR_PUPDR5_1 ((uint32_t)0x00000800)
\r
4357 #define GPIO_PUPDR_PUPDR6 ((uint32_t)0x00003000)
\r
4358 #define GPIO_PUPDR_PUPDR6_0 ((uint32_t)0x00001000)
\r
4359 #define GPIO_PUPDR_PUPDR6_1 ((uint32_t)0x00002000)
\r
4361 #define GPIO_PUPDR_PUPDR7 ((uint32_t)0x0000C000)
\r
4362 #define GPIO_PUPDR_PUPDR7_0 ((uint32_t)0x00004000)
\r
4363 #define GPIO_PUPDR_PUPDR7_1 ((uint32_t)0x00008000)
\r
4365 #define GPIO_PUPDR_PUPDR8 ((uint32_t)0x00030000)
\r
4366 #define GPIO_PUPDR_PUPDR8_0 ((uint32_t)0x00010000)
\r
4367 #define GPIO_PUPDR_PUPDR8_1 ((uint32_t)0x00020000)
\r
4369 #define GPIO_PUPDR_PUPDR9 ((uint32_t)0x000C0000)
\r
4370 #define GPIO_PUPDR_PUPDR9_0 ((uint32_t)0x00040000)
\r
4371 #define GPIO_PUPDR_PUPDR9_1 ((uint32_t)0x00080000)
\r
4373 #define GPIO_PUPDR_PUPDR10 ((uint32_t)0x00300000)
\r
4374 #define GPIO_PUPDR_PUPDR10_0 ((uint32_t)0x00100000)
\r
4375 #define GPIO_PUPDR_PUPDR10_1 ((uint32_t)0x00200000)
\r
4377 #define GPIO_PUPDR_PUPDR11 ((uint32_t)0x00C00000)
\r
4378 #define GPIO_PUPDR_PUPDR11_0 ((uint32_t)0x00400000)
\r
4379 #define GPIO_PUPDR_PUPDR11_1 ((uint32_t)0x00800000)
\r
4381 #define GPIO_PUPDR_PUPDR12 ((uint32_t)0x03000000)
\r
4382 #define GPIO_PUPDR_PUPDR12_0 ((uint32_t)0x01000000)
\r
4383 #define GPIO_PUPDR_PUPDR12_1 ((uint32_t)0x02000000)
\r
4385 #define GPIO_PUPDR_PUPDR13 ((uint32_t)0x0C000000)
\r
4386 #define GPIO_PUPDR_PUPDR13_0 ((uint32_t)0x04000000)
\r
4387 #define GPIO_PUPDR_PUPDR13_1 ((uint32_t)0x08000000)
\r
4389 #define GPIO_PUPDR_PUPDR14 ((uint32_t)0x30000000)
\r
4390 #define GPIO_PUPDR_PUPDR14_0 ((uint32_t)0x10000000)
\r
4391 #define GPIO_PUPDR_PUPDR14_1 ((uint32_t)0x20000000)
\r
4393 #define GPIO_PUPDR_PUPDR15 ((uint32_t)0xC0000000)
\r
4394 #define GPIO_PUPDR_PUPDR15_0 ((uint32_t)0x40000000)
\r
4395 #define GPIO_PUPDR_PUPDR15_1 ((uint32_t)0x80000000)
\r
4397 /****************** Bits definition for GPIO_IDR register *******************/
\r
4398 #define GPIO_IDR_IDR_0 ((uint32_t)0x00000001)
\r
4399 #define GPIO_IDR_IDR_1 ((uint32_t)0x00000002)
\r
4400 #define GPIO_IDR_IDR_2 ((uint32_t)0x00000004)
\r
4401 #define GPIO_IDR_IDR_3 ((uint32_t)0x00000008)
\r
4402 #define GPIO_IDR_IDR_4 ((uint32_t)0x00000010)
\r
4403 #define GPIO_IDR_IDR_5 ((uint32_t)0x00000020)
\r
4404 #define GPIO_IDR_IDR_6 ((uint32_t)0x00000040)
\r
4405 #define GPIO_IDR_IDR_7 ((uint32_t)0x00000080)
\r
4406 #define GPIO_IDR_IDR_8 ((uint32_t)0x00000100)
\r
4407 #define GPIO_IDR_IDR_9 ((uint32_t)0x00000200)
\r
4408 #define GPIO_IDR_IDR_10 ((uint32_t)0x00000400)
\r
4409 #define GPIO_IDR_IDR_11 ((uint32_t)0x00000800)
\r
4410 #define GPIO_IDR_IDR_12 ((uint32_t)0x00001000)
\r
4411 #define GPIO_IDR_IDR_13 ((uint32_t)0x00002000)
\r
4412 #define GPIO_IDR_IDR_14 ((uint32_t)0x00004000)
\r
4413 #define GPIO_IDR_IDR_15 ((uint32_t)0x00008000)
\r
4414 /* Old GPIO_IDR register bits definition, maintained for legacy purpose */
\r
4415 #define GPIO_OTYPER_IDR_0 GPIO_IDR_IDR_0
\r
4416 #define GPIO_OTYPER_IDR_1 GPIO_IDR_IDR_1
\r
4417 #define GPIO_OTYPER_IDR_2 GPIO_IDR_IDR_2
\r
4418 #define GPIO_OTYPER_IDR_3 GPIO_IDR_IDR_3
\r
4419 #define GPIO_OTYPER_IDR_4 GPIO_IDR_IDR_4
\r
4420 #define GPIO_OTYPER_IDR_5 GPIO_IDR_IDR_5
\r
4421 #define GPIO_OTYPER_IDR_6 GPIO_IDR_IDR_6
\r
4422 #define GPIO_OTYPER_IDR_7 GPIO_IDR_IDR_7
\r
4423 #define GPIO_OTYPER_IDR_8 GPIO_IDR_IDR_8
\r
4424 #define GPIO_OTYPER_IDR_9 GPIO_IDR_IDR_9
\r
4425 #define GPIO_OTYPER_IDR_10 GPIO_IDR_IDR_10
\r
4426 #define GPIO_OTYPER_IDR_11 GPIO_IDR_IDR_11
\r
4427 #define GPIO_OTYPER_IDR_12 GPIO_IDR_IDR_12
\r
4428 #define GPIO_OTYPER_IDR_13 GPIO_IDR_IDR_13
\r
4429 #define GPIO_OTYPER_IDR_14 GPIO_IDR_IDR_14
\r
4430 #define GPIO_OTYPER_IDR_15 GPIO_IDR_IDR_15
\r
4432 /****************** Bits definition for GPIO_ODR register *******************/
\r
4433 #define GPIO_ODR_ODR_0 ((uint32_t)0x00000001)
\r
4434 #define GPIO_ODR_ODR_1 ((uint32_t)0x00000002)
\r
4435 #define GPIO_ODR_ODR_2 ((uint32_t)0x00000004)
\r
4436 #define GPIO_ODR_ODR_3 ((uint32_t)0x00000008)
\r
4437 #define GPIO_ODR_ODR_4 ((uint32_t)0x00000010)
\r
4438 #define GPIO_ODR_ODR_5 ((uint32_t)0x00000020)
\r
4439 #define GPIO_ODR_ODR_6 ((uint32_t)0x00000040)
\r
4440 #define GPIO_ODR_ODR_7 ((uint32_t)0x00000080)
\r
4441 #define GPIO_ODR_ODR_8 ((uint32_t)0x00000100)
\r
4442 #define GPIO_ODR_ODR_9 ((uint32_t)0x00000200)
\r
4443 #define GPIO_ODR_ODR_10 ((uint32_t)0x00000400)
\r
4444 #define GPIO_ODR_ODR_11 ((uint32_t)0x00000800)
\r
4445 #define GPIO_ODR_ODR_12 ((uint32_t)0x00001000)
\r
4446 #define GPIO_ODR_ODR_13 ((uint32_t)0x00002000)
\r
4447 #define GPIO_ODR_ODR_14 ((uint32_t)0x00004000)
\r
4448 #define GPIO_ODR_ODR_15 ((uint32_t)0x00008000)
\r
4449 /* Old GPIO_ODR register bits definition, maintained for legacy purpose */
\r
4450 #define GPIO_OTYPER_ODR_0 GPIO_ODR_ODR_0
\r
4451 #define GPIO_OTYPER_ODR_1 GPIO_ODR_ODR_1
\r
4452 #define GPIO_OTYPER_ODR_2 GPIO_ODR_ODR_2
\r
4453 #define GPIO_OTYPER_ODR_3 GPIO_ODR_ODR_3
\r
4454 #define GPIO_OTYPER_ODR_4 GPIO_ODR_ODR_4
\r
4455 #define GPIO_OTYPER_ODR_5 GPIO_ODR_ODR_5
\r
4456 #define GPIO_OTYPER_ODR_6 GPIO_ODR_ODR_6
\r
4457 #define GPIO_OTYPER_ODR_7 GPIO_ODR_ODR_7
\r
4458 #define GPIO_OTYPER_ODR_8 GPIO_ODR_ODR_8
\r
4459 #define GPIO_OTYPER_ODR_9 GPIO_ODR_ODR_9
\r
4460 #define GPIO_OTYPER_ODR_10 GPIO_ODR_ODR_10
\r
4461 #define GPIO_OTYPER_ODR_11 GPIO_ODR_ODR_11
\r
4462 #define GPIO_OTYPER_ODR_12 GPIO_ODR_ODR_12
\r
4463 #define GPIO_OTYPER_ODR_13 GPIO_ODR_ODR_13
\r
4464 #define GPIO_OTYPER_ODR_14 GPIO_ODR_ODR_14
\r
4465 #define GPIO_OTYPER_ODR_15 GPIO_ODR_ODR_15
\r
4467 /****************** Bits definition for GPIO_BSRR register ******************/
\r
4468 #define GPIO_BSRR_BS_0 ((uint32_t)0x00000001)
\r
4469 #define GPIO_BSRR_BS_1 ((uint32_t)0x00000002)
\r
4470 #define GPIO_BSRR_BS_2 ((uint32_t)0x00000004)
\r
4471 #define GPIO_BSRR_BS_3 ((uint32_t)0x00000008)
\r
4472 #define GPIO_BSRR_BS_4 ((uint32_t)0x00000010)
\r
4473 #define GPIO_BSRR_BS_5 ((uint32_t)0x00000020)
\r
4474 #define GPIO_BSRR_BS_6 ((uint32_t)0x00000040)
\r
4475 #define GPIO_BSRR_BS_7 ((uint32_t)0x00000080)
\r
4476 #define GPIO_BSRR_BS_8 ((uint32_t)0x00000100)
\r
4477 #define GPIO_BSRR_BS_9 ((uint32_t)0x00000200)
\r
4478 #define GPIO_BSRR_BS_10 ((uint32_t)0x00000400)
\r
4479 #define GPIO_BSRR_BS_11 ((uint32_t)0x00000800)
\r
4480 #define GPIO_BSRR_BS_12 ((uint32_t)0x00001000)
\r
4481 #define GPIO_BSRR_BS_13 ((uint32_t)0x00002000)
\r
4482 #define GPIO_BSRR_BS_14 ((uint32_t)0x00004000)
\r
4483 #define GPIO_BSRR_BS_15 ((uint32_t)0x00008000)
\r
4484 #define GPIO_BSRR_BR_0 ((uint32_t)0x00010000)
\r
4485 #define GPIO_BSRR_BR_1 ((uint32_t)0x00020000)
\r
4486 #define GPIO_BSRR_BR_2 ((uint32_t)0x00040000)
\r
4487 #define GPIO_BSRR_BR_3 ((uint32_t)0x00080000)
\r
4488 #define GPIO_BSRR_BR_4 ((uint32_t)0x00100000)
\r
4489 #define GPIO_BSRR_BR_5 ((uint32_t)0x00200000)
\r
4490 #define GPIO_BSRR_BR_6 ((uint32_t)0x00400000)
\r
4491 #define GPIO_BSRR_BR_7 ((uint32_t)0x00800000)
\r
4492 #define GPIO_BSRR_BR_8 ((uint32_t)0x01000000)
\r
4493 #define GPIO_BSRR_BR_9 ((uint32_t)0x02000000)
\r
4494 #define GPIO_BSRR_BR_10 ((uint32_t)0x04000000)
\r
4495 #define GPIO_BSRR_BR_11 ((uint32_t)0x08000000)
\r
4496 #define GPIO_BSRR_BR_12 ((uint32_t)0x10000000)
\r
4497 #define GPIO_BSRR_BR_13 ((uint32_t)0x20000000)
\r
4498 #define GPIO_BSRR_BR_14 ((uint32_t)0x40000000)
\r
4499 #define GPIO_BSRR_BR_15 ((uint32_t)0x80000000)
\r
4501 /******************************************************************************/
\r
4503 /* Inter-integrated Circuit Interface */
\r
4505 /******************************************************************************/
\r
4506 /******************* Bit definition for I2C_CR1 register ********************/
\r
4507 #define I2C_CR1_PE ((uint32_t)0x00000001) /*!<Peripheral Enable */
\r
4508 #define I2C_CR1_SMBUS ((uint32_t)0x00000002) /*!<SMBus Mode */
\r
4509 #define I2C_CR1_SMBTYPE ((uint32_t)0x00000008) /*!<SMBus Type */
\r
4510 #define I2C_CR1_ENARP ((uint32_t)0x00000010) /*!<ARP Enable */
\r
4511 #define I2C_CR1_ENPEC ((uint32_t)0x00000020) /*!<PEC Enable */
\r
4512 #define I2C_CR1_ENGC ((uint32_t)0x00000040) /*!<General Call Enable */
\r
4513 #define I2C_CR1_NOSTRETCH ((uint32_t)0x00000080) /*!<Clock Stretching Disable (Slave mode) */
\r
4514 #define I2C_CR1_START ((uint32_t)0x00000100) /*!<Start Generation */
\r
4515 #define I2C_CR1_STOP ((uint32_t)0x00000200) /*!<Stop Generation */
\r
4516 #define I2C_CR1_ACK ((uint32_t)0x00000400) /*!<Acknowledge Enable */
\r
4517 #define I2C_CR1_POS ((uint32_t)0x00000800) /*!<Acknowledge/PEC Position (for data reception) */
\r
4518 #define I2C_CR1_PEC ((uint32_t)0x00001000) /*!<Packet Error Checking */
\r
4519 #define I2C_CR1_ALERT ((uint32_t)0x00002000) /*!<SMBus Alert */
\r
4520 #define I2C_CR1_SWRST ((uint32_t)0x00008000) /*!<Software Reset */
\r
4522 /******************* Bit definition for I2C_CR2 register ********************/
\r
4523 #define I2C_CR2_FREQ ((uint32_t)0x0000003F) /*!<FREQ[5:0] bits (Peripheral Clock Frequency) */
\r
4524 #define I2C_CR2_FREQ_0 ((uint32_t)0x00000001) /*!<Bit 0 */
\r
4525 #define I2C_CR2_FREQ_1 ((uint32_t)0x00000002) /*!<Bit 1 */
\r
4526 #define I2C_CR2_FREQ_2 ((uint32_t)0x00000004) /*!<Bit 2 */
\r
4527 #define I2C_CR2_FREQ_3 ((uint32_t)0x00000008) /*!<Bit 3 */
\r
4528 #define I2C_CR2_FREQ_4 ((uint32_t)0x00000010) /*!<Bit 4 */
\r
4529 #define I2C_CR2_FREQ_5 ((uint32_t)0x00000020) /*!<Bit 5 */
\r
4531 #define I2C_CR2_ITERREN ((uint32_t)0x00000100) /*!<Error Interrupt Enable */
\r
4532 #define I2C_CR2_ITEVTEN ((uint32_t)0x00000200) /*!<Event Interrupt Enable */
\r
4533 #define I2C_CR2_ITBUFEN ((uint32_t)0x00000400) /*!<Buffer Interrupt Enable */
\r
4534 #define I2C_CR2_DMAEN ((uint32_t)0x00000800) /*!<DMA Requests Enable */
\r
4535 #define I2C_CR2_LAST ((uint32_t)0x00001000) /*!<DMA Last Transfer */
\r
4537 /******************* Bit definition for I2C_OAR1 register *******************/
\r
4538 #define I2C_OAR1_ADD1_7 ((uint32_t)0x000000FE) /*!<Interface Address */
\r
4539 #define I2C_OAR1_ADD8_9 ((uint32_t)0x00000300) /*!<Interface Address */
\r
4541 #define I2C_OAR1_ADD0 ((uint32_t)0x00000001) /*!<Bit 0 */
\r
4542 #define I2C_OAR1_ADD1 ((uint32_t)0x00000002) /*!<Bit 1 */
\r
4543 #define I2C_OAR1_ADD2 ((uint32_t)0x00000004) /*!<Bit 2 */
\r
4544 #define I2C_OAR1_ADD3 ((uint32_t)0x00000008) /*!<Bit 3 */
\r
4545 #define I2C_OAR1_ADD4 ((uint32_t)0x00000010) /*!<Bit 4 */
\r
4546 #define I2C_OAR1_ADD5 ((uint32_t)0x00000020) /*!<Bit 5 */
\r
4547 #define I2C_OAR1_ADD6 ((uint32_t)0x00000040) /*!<Bit 6 */
\r
4548 #define I2C_OAR1_ADD7 ((uint32_t)0x00000080) /*!<Bit 7 */
\r
4549 #define I2C_OAR1_ADD8 ((uint32_t)0x00000100) /*!<Bit 8 */
\r
4550 #define I2C_OAR1_ADD9 ((uint32_t)0x00000200) /*!<Bit 9 */
\r
4552 #define I2C_OAR1_ADDMODE ((uint32_t)0x00008000) /*!<Addressing Mode (Slave mode) */
\r
4554 /******************* Bit definition for I2C_OAR2 register *******************/
\r
4555 #define I2C_OAR2_ENDUAL ((uint32_t)0x00000001) /*!<Dual addressing mode enable */
\r
4556 #define I2C_OAR2_ADD2 ((uint32_t)0x000000FE) /*!<Interface address */
\r
4558 /******************** Bit definition for I2C_DR register ********************/
\r
4559 #define I2C_DR_DR ((uint32_t)0x000000FF) /*!<8-bit Data Register */
\r
4561 /******************* Bit definition for I2C_SR1 register ********************/
\r
4562 #define I2C_SR1_SB ((uint32_t)0x00000001) /*!<Start Bit (Master mode) */
\r
4563 #define I2C_SR1_ADDR ((uint32_t)0x00000002) /*!<Address sent (master mode)/matched (slave mode) */
\r
4564 #define I2C_SR1_BTF ((uint32_t)0x00000004) /*!<Byte Transfer Finished */
\r
4565 #define I2C_SR1_ADD10 ((uint32_t)0x00000008) /*!<10-bit header sent (Master mode) */
\r
4566 #define I2C_SR1_STOPF ((uint32_t)0x00000010) /*!<Stop detection (Slave mode) */
\r
4567 #define I2C_SR1_RXNE ((uint32_t)0x00000040) /*!<Data Register not Empty (receivers) */
\r
4568 #define I2C_SR1_TXE ((uint32_t)0x00000080) /*!<Data Register Empty (transmitters) */
\r
4569 #define I2C_SR1_BERR ((uint32_t)0x00000100) /*!<Bus Error */
\r
4570 #define I2C_SR1_ARLO ((uint32_t)0x00000200) /*!<Arbitration Lost (master mode) */
\r
4571 #define I2C_SR1_AF ((uint32_t)0x00000400) /*!<Acknowledge Failure */
\r
4572 #define I2C_SR1_OVR ((uint32_t)0x00000800) /*!<Overrun/Underrun */
\r
4573 #define I2C_SR1_PECERR ((uint32_t)0x00001000) /*!<PEC Error in reception */
\r
4574 #define I2C_SR1_TIMEOUT ((uint32_t)0x00004000) /*!<Timeout or Tlow Error */
\r
4575 #define I2C_SR1_SMBALERT ((uint32_t)0x00008000) /*!<SMBus Alert */
\r
4577 /******************* Bit definition for I2C_SR2 register ********************/
\r
4578 #define I2C_SR2_MSL ((uint32_t)0x00000001) /*!<Master/Slave */
\r
4579 #define I2C_SR2_BUSY ((uint32_t)0x00000002) /*!<Bus Busy */
\r
4580 #define I2C_SR2_TRA ((uint32_t)0x00000004) /*!<Transmitter/Receiver */
\r
4581 #define I2C_SR2_GENCALL ((uint32_t)0x00000010) /*!<General Call Address (Slave mode) */
\r
4582 #define I2C_SR2_SMBDEFAULT ((uint32_t)0x00000020) /*!<SMBus Device Default Address (Slave mode) */
\r
4583 #define I2C_SR2_SMBHOST ((uint32_t)0x00000040) /*!<SMBus Host Header (Slave mode) */
\r
4584 #define I2C_SR2_DUALF ((uint32_t)0x00000080) /*!<Dual Flag (Slave mode) */
\r
4585 #define I2C_SR2_PEC ((uint32_t)0x0000FF00) /*!<Packet Error Checking Register */
\r
4587 /******************* Bit definition for I2C_CCR register ********************/
\r
4588 #define I2C_CCR_CCR ((uint32_t)0x00000FFF) /*!<Clock Control Register in Fast/Standard mode (Master mode) */
\r
4589 #define I2C_CCR_DUTY ((uint32_t)0x00004000) /*!<Fast Mode Duty Cycle */
\r
4590 #define I2C_CCR_FS ((uint32_t)0x00008000) /*!<I2C Master Mode Selection */
\r
4592 /****************** Bit definition for I2C_TRISE register *******************/
\r
4593 #define I2C_TRISE_TRISE ((uint32_t)0x0000003F) /*!<Maximum Rise Time in Fast/Standard mode (Master mode) */
\r
4595 /****************** Bit definition for I2C_FLTR register *******************/
\r
4596 #define I2C_FLTR_DNF ((uint32_t)0x0000000F) /*!<Digital Noise Filter */
\r
4597 #define I2C_FLTR_ANOFF ((uint32_t)0x00000010) /*!<Analog Noise Filter OFF */
\r
4599 /******************************************************************************/
\r
4601 /* Independent WATCHDOG */
\r
4603 /******************************************************************************/
\r
4604 /******************* Bit definition for IWDG_KR register ********************/
\r
4605 #define IWDG_KR_KEY ((uint32_t)0xFFFF) /*!<Key value (write only, read 0000h) */
\r
4607 /******************* Bit definition for IWDG_PR register ********************/
\r
4608 #define IWDG_PR_PR ((uint32_t)0x07) /*!<PR[2:0] (Prescaler divider) */
\r
4609 #define IWDG_PR_PR_0 ((uint32_t)0x01) /*!<Bit 0 */
\r
4610 #define IWDG_PR_PR_1 ((uint32_t)0x02) /*!<Bit 1 */
\r
4611 #define IWDG_PR_PR_2 ((uint32_t)0x04) /*!<Bit 2 */
\r
4613 /******************* Bit definition for IWDG_RLR register *******************/
\r
4614 #define IWDG_RLR_RL ((uint32_t)0x0FFF) /*!<Watchdog counter reload value */
\r
4616 /******************* Bit definition for IWDG_SR register ********************/
\r
4617 #define IWDG_SR_PVU ((uint32_t)0x01) /*!<Watchdog prescaler value update */
\r
4618 #define IWDG_SR_RVU ((uint32_t)0x02) /*!<Watchdog counter reload value update */
\r
4621 /******************************************************************************/
\r
4623 /* Power Control */
\r
4625 /******************************************************************************/
\r
4626 /******************** Bit definition for PWR_CR register ********************/
\r
4627 #define PWR_CR_LPDS ((uint32_t)0x00000001) /*!< Low-Power Deepsleep */
\r
4628 #define PWR_CR_PDDS ((uint32_t)0x00000002) /*!< Power Down Deepsleep */
\r
4629 #define PWR_CR_CWUF ((uint32_t)0x00000004) /*!< Clear Wakeup Flag */
\r
4630 #define PWR_CR_CSBF ((uint32_t)0x00000008) /*!< Clear Standby Flag */
\r
4631 #define PWR_CR_PVDE ((uint32_t)0x00000010) /*!< Power Voltage Detector Enable */
\r
4633 #define PWR_CR_PLS ((uint32_t)0x000000E0) /*!< PLS[2:0] bits (PVD Level Selection) */
\r
4634 #define PWR_CR_PLS_0 ((uint32_t)0x00000020) /*!< Bit 0 */
\r
4635 #define PWR_CR_PLS_1 ((uint32_t)0x00000040) /*!< Bit 1 */
\r
4636 #define PWR_CR_PLS_2 ((uint32_t)0x00000080) /*!< Bit 2 */
\r
4638 /*!< PVD level configuration */
\r
4639 #define PWR_CR_PLS_LEV0 ((uint32_t)0x00000000) /*!< PVD level 0 */
\r
4640 #define PWR_CR_PLS_LEV1 ((uint32_t)0x00000020) /*!< PVD level 1 */
\r
4641 #define PWR_CR_PLS_LEV2 ((uint32_t)0x00000040) /*!< PVD level 2 */
\r
4642 #define PWR_CR_PLS_LEV3 ((uint32_t)0x00000060) /*!< PVD level 3 */
\r
4643 #define PWR_CR_PLS_LEV4 ((uint32_t)0x00000080) /*!< PVD level 4 */
\r
4644 #define PWR_CR_PLS_LEV5 ((uint32_t)0x000000A0) /*!< PVD level 5 */
\r
4645 #define PWR_CR_PLS_LEV6 ((uint32_t)0x000000C0) /*!< PVD level 6 */
\r
4646 #define PWR_CR_PLS_LEV7 ((uint32_t)0x000000E0) /*!< PVD level 7 */
\r
4648 #define PWR_CR_DBP ((uint32_t)0x00000100) /*!< Disable Backup Domain write protection */
\r
4649 #define PWR_CR_FPDS ((uint32_t)0x00000200) /*!< Flash power down in Stop mode */
\r
4650 #define PWR_CR_VOS ((uint32_t)0x0000C000) /*!< VOS[1:0] bits (Regulator voltage scaling output selection) */
\r
4651 #define PWR_CR_VOS_0 ((uint32_t)0x00004000) /*!< Bit 0 */
\r
4652 #define PWR_CR_VOS_1 ((uint32_t)0x00008000) /*!< Bit 1 */
\r
4654 /* Legacy define */
\r
4655 #define PWR_CR_PMODE PWR_CR_VOS
\r
4657 /******************* Bit definition for PWR_CSR register ********************/
\r
4658 #define PWR_CSR_WUF ((uint32_t)0x00000001) /*!< Wakeup Flag */
\r
4659 #define PWR_CSR_SBF ((uint32_t)0x00000002) /*!< Standby Flag */
\r
4660 #define PWR_CSR_PVDO ((uint32_t)0x00000004) /*!< PVD Output */
\r
4661 #define PWR_CSR_BRR ((uint32_t)0x00000008) /*!< Backup regulator ready */
\r
4662 #define PWR_CSR_EWUP ((uint32_t)0x00000100) /*!< Enable WKUP pin */
\r
4663 #define PWR_CSR_BRE ((uint32_t)0x00000200) /*!< Backup regulator enable */
\r
4664 #define PWR_CSR_VOSRDY ((uint32_t)0x00004000) /*!< Regulator voltage scaling output selection ready */
\r
4666 /* Legacy define */
\r
4667 #define PWR_CSR_REGRDY PWR_CSR_VOSRDY
\r
4669 /******************************************************************************/
\r
4671 /* Reset and Clock Control */
\r
4673 /******************************************************************************/
\r
4674 /******************** Bit definition for RCC_CR register ********************/
\r
4675 #define RCC_CR_HSION ((uint32_t)0x00000001)
\r
4676 #define RCC_CR_HSIRDY ((uint32_t)0x00000002)
\r
4678 #define RCC_CR_HSITRIM ((uint32_t)0x000000F8)
\r
4679 #define RCC_CR_HSITRIM_0 ((uint32_t)0x00000008)/*!<Bit 0 */
\r
4680 #define RCC_CR_HSITRIM_1 ((uint32_t)0x00000010)/*!<Bit 1 */
\r
4681 #define RCC_CR_HSITRIM_2 ((uint32_t)0x00000020)/*!<Bit 2 */
\r
4682 #define RCC_CR_HSITRIM_3 ((uint32_t)0x00000040)/*!<Bit 3 */
\r
4683 #define RCC_CR_HSITRIM_4 ((uint32_t)0x00000080)/*!<Bit 4 */
\r
4685 #define RCC_CR_HSICAL ((uint32_t)0x0000FF00)
\r
4686 #define RCC_CR_HSICAL_0 ((uint32_t)0x00000100)/*!<Bit 0 */
\r
4687 #define RCC_CR_HSICAL_1 ((uint32_t)0x00000200)/*!<Bit 1 */
\r
4688 #define RCC_CR_HSICAL_2 ((uint32_t)0x00000400)/*!<Bit 2 */
\r
4689 #define RCC_CR_HSICAL_3 ((uint32_t)0x00000800)/*!<Bit 3 */
\r
4690 #define RCC_CR_HSICAL_4 ((uint32_t)0x00001000)/*!<Bit 4 */
\r
4691 #define RCC_CR_HSICAL_5 ((uint32_t)0x00002000)/*!<Bit 5 */
\r
4692 #define RCC_CR_HSICAL_6 ((uint32_t)0x00004000)/*!<Bit 6 */
\r
4693 #define RCC_CR_HSICAL_7 ((uint32_t)0x00008000)/*!<Bit 7 */
\r
4695 #define RCC_CR_HSEON ((uint32_t)0x00010000)
\r
4696 #define RCC_CR_HSERDY ((uint32_t)0x00020000)
\r
4697 #define RCC_CR_HSEBYP ((uint32_t)0x00040000)
\r
4698 #define RCC_CR_CSSON ((uint32_t)0x00080000)
\r
4699 #define RCC_CR_PLLON ((uint32_t)0x01000000)
\r
4700 #define RCC_CR_PLLRDY ((uint32_t)0x02000000)
\r
4701 #define RCC_CR_PLLI2SON ((uint32_t)0x04000000)
\r
4702 #define RCC_CR_PLLI2SRDY ((uint32_t)0x08000000)
\r
4704 /******************** Bit definition for RCC_PLLCFGR register ***************/
\r
4705 #define RCC_PLLCFGR_PLLM ((uint32_t)0x0000003F)
\r
4706 #define RCC_PLLCFGR_PLLM_0 ((uint32_t)0x00000001)
\r
4707 #define RCC_PLLCFGR_PLLM_1 ((uint32_t)0x00000002)
\r
4708 #define RCC_PLLCFGR_PLLM_2 ((uint32_t)0x00000004)
\r
4709 #define RCC_PLLCFGR_PLLM_3 ((uint32_t)0x00000008)
\r
4710 #define RCC_PLLCFGR_PLLM_4 ((uint32_t)0x00000010)
\r
4711 #define RCC_PLLCFGR_PLLM_5 ((uint32_t)0x00000020)
\r
4713 #define RCC_PLLCFGR_PLLN ((uint32_t)0x00007FC0)
\r
4714 #define RCC_PLLCFGR_PLLN_0 ((uint32_t)0x00000040)
\r
4715 #define RCC_PLLCFGR_PLLN_1 ((uint32_t)0x00000080)
\r
4716 #define RCC_PLLCFGR_PLLN_2 ((uint32_t)0x00000100)
\r
4717 #define RCC_PLLCFGR_PLLN_3 ((uint32_t)0x00000200)
\r
4718 #define RCC_PLLCFGR_PLLN_4 ((uint32_t)0x00000400)
\r
4719 #define RCC_PLLCFGR_PLLN_5 ((uint32_t)0x00000800)
\r
4720 #define RCC_PLLCFGR_PLLN_6 ((uint32_t)0x00001000)
\r
4721 #define RCC_PLLCFGR_PLLN_7 ((uint32_t)0x00002000)
\r
4722 #define RCC_PLLCFGR_PLLN_8 ((uint32_t)0x00004000)
\r
4724 #define RCC_PLLCFGR_PLLP ((uint32_t)0x00030000)
\r
4725 #define RCC_PLLCFGR_PLLP_0 ((uint32_t)0x00010000)
\r
4726 #define RCC_PLLCFGR_PLLP_1 ((uint32_t)0x00020000)
\r
4728 #define RCC_PLLCFGR_PLLSRC ((uint32_t)0x00400000)
\r
4729 #define RCC_PLLCFGR_PLLSRC_HSE ((uint32_t)0x00400000)
\r
4730 #define RCC_PLLCFGR_PLLSRC_HSI ((uint32_t)0x00000000)
\r
4732 #define RCC_PLLCFGR_PLLQ ((uint32_t)0x0F000000)
\r
4733 #define RCC_PLLCFGR_PLLQ_0 ((uint32_t)0x01000000)
\r
4734 #define RCC_PLLCFGR_PLLQ_1 ((uint32_t)0x02000000)
\r
4735 #define RCC_PLLCFGR_PLLQ_2 ((uint32_t)0x04000000)
\r
4736 #define RCC_PLLCFGR_PLLQ_3 ((uint32_t)0x08000000)
\r
4738 /******************** Bit definition for RCC_CFGR register ******************/
\r
4739 /*!< SW configuration */
\r
4740 #define RCC_CFGR_SW ((uint32_t)0x00000003) /*!< SW[1:0] bits (System clock Switch) */
\r
4741 #define RCC_CFGR_SW_0 ((uint32_t)0x00000001) /*!< Bit 0 */
\r
4742 #define RCC_CFGR_SW_1 ((uint32_t)0x00000002) /*!< Bit 1 */
\r
4744 #define RCC_CFGR_SW_HSI ((uint32_t)0x00000000) /*!< HSI selected as system clock */
\r
4745 #define RCC_CFGR_SW_HSE ((uint32_t)0x00000001) /*!< HSE selected as system clock */
\r
4746 #define RCC_CFGR_SW_PLL ((uint32_t)0x00000002) /*!< PLL selected as system clock */
\r
4748 /*!< SWS configuration */
\r
4749 #define RCC_CFGR_SWS ((uint32_t)0x0000000C) /*!< SWS[1:0] bits (System Clock Switch Status) */
\r
4750 #define RCC_CFGR_SWS_0 ((uint32_t)0x00000004) /*!< Bit 0 */
\r
4751 #define RCC_CFGR_SWS_1 ((uint32_t)0x00000008) /*!< Bit 1 */
\r
4753 #define RCC_CFGR_SWS_HSI ((uint32_t)0x00000000) /*!< HSI oscillator used as system clock */
\r
4754 #define RCC_CFGR_SWS_HSE ((uint32_t)0x00000004) /*!< HSE oscillator used as system clock */
\r
4755 #define RCC_CFGR_SWS_PLL ((uint32_t)0x00000008) /*!< PLL used as system clock */
\r
4757 /*!< HPRE configuration */
\r
4758 #define RCC_CFGR_HPRE ((uint32_t)0x000000F0) /*!< HPRE[3:0] bits (AHB prescaler) */
\r
4759 #define RCC_CFGR_HPRE_0 ((uint32_t)0x00000010) /*!< Bit 0 */
\r
4760 #define RCC_CFGR_HPRE_1 ((uint32_t)0x00000020) /*!< Bit 1 */
\r
4761 #define RCC_CFGR_HPRE_2 ((uint32_t)0x00000040) /*!< Bit 2 */
\r
4762 #define RCC_CFGR_HPRE_3 ((uint32_t)0x00000080) /*!< Bit 3 */
\r
4764 #define RCC_CFGR_HPRE_DIV1 ((uint32_t)0x00000000) /*!< SYSCLK not divided */
\r
4765 #define RCC_CFGR_HPRE_DIV2 ((uint32_t)0x00000080) /*!< SYSCLK divided by 2 */
\r
4766 #define RCC_CFGR_HPRE_DIV4 ((uint32_t)0x00000090) /*!< SYSCLK divided by 4 */
\r
4767 #define RCC_CFGR_HPRE_DIV8 ((uint32_t)0x000000A0) /*!< SYSCLK divided by 8 */
\r
4768 #define RCC_CFGR_HPRE_DIV16 ((uint32_t)0x000000B0) /*!< SYSCLK divided by 16 */
\r
4769 #define RCC_CFGR_HPRE_DIV64 ((uint32_t)0x000000C0) /*!< SYSCLK divided by 64 */
\r
4770 #define RCC_CFGR_HPRE_DIV128 ((uint32_t)0x000000D0) /*!< SYSCLK divided by 128 */
\r
4771 #define RCC_CFGR_HPRE_DIV256 ((uint32_t)0x000000E0) /*!< SYSCLK divided by 256 */
\r
4772 #define RCC_CFGR_HPRE_DIV512 ((uint32_t)0x000000F0) /*!< SYSCLK divided by 512 */
\r
4774 /*!< PPRE1 configuration */
\r
4775 #define RCC_CFGR_PPRE1 ((uint32_t)0x00001C00) /*!< PRE1[2:0] bits (APB1 prescaler) */
\r
4776 #define RCC_CFGR_PPRE1_0 ((uint32_t)0x00000400) /*!< Bit 0 */
\r
4777 #define RCC_CFGR_PPRE1_1 ((uint32_t)0x00000800) /*!< Bit 1 */
\r
4778 #define RCC_CFGR_PPRE1_2 ((uint32_t)0x00001000) /*!< Bit 2 */
\r
4780 #define RCC_CFGR_PPRE1_DIV1 ((uint32_t)0x00000000) /*!< HCLK not divided */
\r
4781 #define RCC_CFGR_PPRE1_DIV2 ((uint32_t)0x00001000) /*!< HCLK divided by 2 */
\r
4782 #define RCC_CFGR_PPRE1_DIV4 ((uint32_t)0x00001400) /*!< HCLK divided by 4 */
\r
4783 #define RCC_CFGR_PPRE1_DIV8 ((uint32_t)0x00001800) /*!< HCLK divided by 8 */
\r
4784 #define RCC_CFGR_PPRE1_DIV16 ((uint32_t)0x00001C00) /*!< HCLK divided by 16 */
\r
4786 /*!< PPRE2 configuration */
\r
4787 #define RCC_CFGR_PPRE2 ((uint32_t)0x0000E000) /*!< PRE2[2:0] bits (APB2 prescaler) */
\r
4788 #define RCC_CFGR_PPRE2_0 ((uint32_t)0x00002000) /*!< Bit 0 */
\r
4789 #define RCC_CFGR_PPRE2_1 ((uint32_t)0x00004000) /*!< Bit 1 */
\r
4790 #define RCC_CFGR_PPRE2_2 ((uint32_t)0x00008000) /*!< Bit 2 */
\r
4792 #define RCC_CFGR_PPRE2_DIV1 ((uint32_t)0x00000000) /*!< HCLK not divided */
\r
4793 #define RCC_CFGR_PPRE2_DIV2 ((uint32_t)0x00008000) /*!< HCLK divided by 2 */
\r
4794 #define RCC_CFGR_PPRE2_DIV4 ((uint32_t)0x0000A000) /*!< HCLK divided by 4 */
\r
4795 #define RCC_CFGR_PPRE2_DIV8 ((uint32_t)0x0000C000) /*!< HCLK divided by 8 */
\r
4796 #define RCC_CFGR_PPRE2_DIV16 ((uint32_t)0x0000E000) /*!< HCLK divided by 16 */
\r
4798 /*!< RTCPRE configuration */
\r
4799 #define RCC_CFGR_RTCPRE ((uint32_t)0x001F0000)
\r
4800 #define RCC_CFGR_RTCPRE_0 ((uint32_t)0x00010000)
\r
4801 #define RCC_CFGR_RTCPRE_1 ((uint32_t)0x00020000)
\r
4802 #define RCC_CFGR_RTCPRE_2 ((uint32_t)0x00040000)
\r
4803 #define RCC_CFGR_RTCPRE_3 ((uint32_t)0x00080000)
\r
4804 #define RCC_CFGR_RTCPRE_4 ((uint32_t)0x00100000)
\r
4806 /*!< MCO1 configuration */
\r
4807 #define RCC_CFGR_MCO1 ((uint32_t)0x00600000)
\r
4808 #define RCC_CFGR_MCO1_0 ((uint32_t)0x00200000)
\r
4809 #define RCC_CFGR_MCO1_1 ((uint32_t)0x00400000)
\r
4811 #define RCC_CFGR_I2SSRC ((uint32_t)0x00800000)
\r
4813 #define RCC_CFGR_MCO1PRE ((uint32_t)0x07000000)
\r
4814 #define RCC_CFGR_MCO1PRE_0 ((uint32_t)0x01000000)
\r
4815 #define RCC_CFGR_MCO1PRE_1 ((uint32_t)0x02000000)
\r
4816 #define RCC_CFGR_MCO1PRE_2 ((uint32_t)0x04000000)
\r
4818 #define RCC_CFGR_MCO2PRE ((uint32_t)0x38000000)
\r
4819 #define RCC_CFGR_MCO2PRE_0 ((uint32_t)0x08000000)
\r
4820 #define RCC_CFGR_MCO2PRE_1 ((uint32_t)0x10000000)
\r
4821 #define RCC_CFGR_MCO2PRE_2 ((uint32_t)0x20000000)
\r
4823 #define RCC_CFGR_MCO2 ((uint32_t)0xC0000000)
\r
4824 #define RCC_CFGR_MCO2_0 ((uint32_t)0x40000000)
\r
4825 #define RCC_CFGR_MCO2_1 ((uint32_t)0x80000000)
\r
4827 /******************** Bit definition for RCC_CIR register *******************/
\r
4828 #define RCC_CIR_LSIRDYF ((uint32_t)0x00000001)
\r
4829 #define RCC_CIR_LSERDYF ((uint32_t)0x00000002)
\r
4830 #define RCC_CIR_HSIRDYF ((uint32_t)0x00000004)
\r
4831 #define RCC_CIR_HSERDYF ((uint32_t)0x00000008)
\r
4832 #define RCC_CIR_PLLRDYF ((uint32_t)0x00000010)
\r
4833 #define RCC_CIR_PLLI2SRDYF ((uint32_t)0x00000020)
\r
4835 #define RCC_CIR_CSSF ((uint32_t)0x00000080)
\r
4836 #define RCC_CIR_LSIRDYIE ((uint32_t)0x00000100)
\r
4837 #define RCC_CIR_LSERDYIE ((uint32_t)0x00000200)
\r
4838 #define RCC_CIR_HSIRDYIE ((uint32_t)0x00000400)
\r
4839 #define RCC_CIR_HSERDYIE ((uint32_t)0x00000800)
\r
4840 #define RCC_CIR_PLLRDYIE ((uint32_t)0x00001000)
\r
4841 #define RCC_CIR_PLLI2SRDYIE ((uint32_t)0x00002000)
\r
4843 #define RCC_CIR_LSIRDYC ((uint32_t)0x00010000)
\r
4844 #define RCC_CIR_LSERDYC ((uint32_t)0x00020000)
\r
4845 #define RCC_CIR_HSIRDYC ((uint32_t)0x00040000)
\r
4846 #define RCC_CIR_HSERDYC ((uint32_t)0x00080000)
\r
4847 #define RCC_CIR_PLLRDYC ((uint32_t)0x00100000)
\r
4848 #define RCC_CIR_PLLI2SRDYC ((uint32_t)0x00200000)
\r
4850 #define RCC_CIR_CSSC ((uint32_t)0x00800000)
\r
4852 /******************** Bit definition for RCC_AHB1RSTR register **************/
\r
4853 #define RCC_AHB1RSTR_GPIOARST ((uint32_t)0x00000001)
\r
4854 #define RCC_AHB1RSTR_GPIOBRST ((uint32_t)0x00000002)
\r
4855 #define RCC_AHB1RSTR_GPIOCRST ((uint32_t)0x00000004)
\r
4856 #define RCC_AHB1RSTR_GPIODRST ((uint32_t)0x00000008)
\r
4857 #define RCC_AHB1RSTR_GPIOERST ((uint32_t)0x00000010)
\r
4858 #define RCC_AHB1RSTR_GPIOFRST ((uint32_t)0x00000020)
\r
4859 #define RCC_AHB1RSTR_GPIOGRST ((uint32_t)0x00000040)
\r
4860 #define RCC_AHB1RSTR_GPIOHRST ((uint32_t)0x00000080)
\r
4861 #define RCC_AHB1RSTR_GPIOIRST ((uint32_t)0x00000100)
\r
4862 #define RCC_AHB1RSTR_CRCRST ((uint32_t)0x00001000)
\r
4863 #define RCC_AHB1RSTR_DMA1RST ((uint32_t)0x00200000)
\r
4864 #define RCC_AHB1RSTR_DMA2RST ((uint32_t)0x00400000)
\r
4865 #define RCC_AHB1RSTR_ETHMACRST ((uint32_t)0x02000000)
\r
4866 #define RCC_AHB1RSTR_OTGHRST ((uint32_t)0x10000000)
\r
4868 /******************** Bit definition for RCC_AHB2RSTR register **************/
\r
4869 #define RCC_AHB2RSTR_DCMIRST ((uint32_t)0x00000001)
\r
4870 #define RCC_AHB2RSTR_RNGRST ((uint32_t)0x00000040)
\r
4871 #define RCC_AHB2RSTR_OTGFSRST ((uint32_t)0x00000080)
\r
4873 /******************** Bit definition for RCC_AHB3RSTR register **************/
\r
4875 #define RCC_AHB3RSTR_FSMCRST ((uint32_t)0x00000001)
\r
4877 /******************** Bit definition for RCC_APB1RSTR register **************/
\r
4878 #define RCC_APB1RSTR_TIM2RST ((uint32_t)0x00000001)
\r
4879 #define RCC_APB1RSTR_TIM3RST ((uint32_t)0x00000002)
\r
4880 #define RCC_APB1RSTR_TIM4RST ((uint32_t)0x00000004)
\r
4881 #define RCC_APB1RSTR_TIM5RST ((uint32_t)0x00000008)
\r
4882 #define RCC_APB1RSTR_TIM6RST ((uint32_t)0x00000010)
\r
4883 #define RCC_APB1RSTR_TIM7RST ((uint32_t)0x00000020)
\r
4884 #define RCC_APB1RSTR_TIM12RST ((uint32_t)0x00000040)
\r
4885 #define RCC_APB1RSTR_TIM13RST ((uint32_t)0x00000080)
\r
4886 #define RCC_APB1RSTR_TIM14RST ((uint32_t)0x00000100)
\r
4887 #define RCC_APB1RSTR_WWDGRST ((uint32_t)0x00000800)
\r
4888 #define RCC_APB1RSTR_SPI2RST ((uint32_t)0x00004000)
\r
4889 #define RCC_APB1RSTR_SPI3RST ((uint32_t)0x00008000)
\r
4890 #define RCC_APB1RSTR_USART2RST ((uint32_t)0x00020000)
\r
4891 #define RCC_APB1RSTR_USART3RST ((uint32_t)0x00040000)
\r
4892 #define RCC_APB1RSTR_UART4RST ((uint32_t)0x00080000)
\r
4893 #define RCC_APB1RSTR_UART5RST ((uint32_t)0x00100000)
\r
4894 #define RCC_APB1RSTR_I2C1RST ((uint32_t)0x00200000)
\r
4895 #define RCC_APB1RSTR_I2C2RST ((uint32_t)0x00400000)
\r
4896 #define RCC_APB1RSTR_I2C3RST ((uint32_t)0x00800000)
\r
4897 #define RCC_APB1RSTR_CAN1RST ((uint32_t)0x02000000)
\r
4898 #define RCC_APB1RSTR_CAN2RST ((uint32_t)0x04000000)
\r
4899 #define RCC_APB1RSTR_PWRRST ((uint32_t)0x10000000)
\r
4900 #define RCC_APB1RSTR_DACRST ((uint32_t)0x20000000)
\r
4902 /******************** Bit definition for RCC_APB2RSTR register **************/
\r
4903 #define RCC_APB2RSTR_TIM1RST ((uint32_t)0x00000001)
\r
4904 #define RCC_APB2RSTR_TIM8RST ((uint32_t)0x00000002)
\r
4905 #define RCC_APB2RSTR_USART1RST ((uint32_t)0x00000010)
\r
4906 #define RCC_APB2RSTR_USART6RST ((uint32_t)0x00000020)
\r
4907 #define RCC_APB2RSTR_ADCRST ((uint32_t)0x00000100)
\r
4908 #define RCC_APB2RSTR_SDIORST ((uint32_t)0x00000800)
\r
4909 #define RCC_APB2RSTR_SPI1RST ((uint32_t)0x00001000)
\r
4910 #define RCC_APB2RSTR_SYSCFGRST ((uint32_t)0x00004000)
\r
4911 #define RCC_APB2RSTR_TIM9RST ((uint32_t)0x00010000)
\r
4912 #define RCC_APB2RSTR_TIM10RST ((uint32_t)0x00020000)
\r
4913 #define RCC_APB2RSTR_TIM11RST ((uint32_t)0x00040000)
\r
4915 /* Old SPI1RST bit definition, maintained for legacy purpose */
\r
4916 #define RCC_APB2RSTR_SPI1 RCC_APB2RSTR_SPI1RST
\r
4918 /******************** Bit definition for RCC_AHB1ENR register ***************/
\r
4919 #define RCC_AHB1ENR_GPIOAEN ((uint32_t)0x00000001)
\r
4920 #define RCC_AHB1ENR_GPIOBEN ((uint32_t)0x00000002)
\r
4921 #define RCC_AHB1ENR_GPIOCEN ((uint32_t)0x00000004)
\r
4922 #define RCC_AHB1ENR_GPIODEN ((uint32_t)0x00000008)
\r
4923 #define RCC_AHB1ENR_GPIOEEN ((uint32_t)0x00000010)
\r
4924 #define RCC_AHB1ENR_GPIOFEN ((uint32_t)0x00000020)
\r
4925 #define RCC_AHB1ENR_GPIOGEN ((uint32_t)0x00000040)
\r
4926 #define RCC_AHB1ENR_GPIOHEN ((uint32_t)0x00000080)
\r
4927 #define RCC_AHB1ENR_GPIOIEN ((uint32_t)0x00000100)
\r
4928 #define RCC_AHB1ENR_CRCEN ((uint32_t)0x00001000)
\r
4929 #define RCC_AHB1ENR_BKPSRAMEN ((uint32_t)0x00040000)
\r
4930 #define RCC_AHB1ENR_CCMDATARAMEN ((uint32_t)0x00100000)
\r
4931 #define RCC_AHB1ENR_DMA1EN ((uint32_t)0x00200000)
\r
4932 #define RCC_AHB1ENR_DMA2EN ((uint32_t)0x00400000)
\r
4934 #define RCC_AHB1ENR_ETHMACEN ((uint32_t)0x02000000)
\r
4935 #define RCC_AHB1ENR_ETHMACTXEN ((uint32_t)0x04000000)
\r
4936 #define RCC_AHB1ENR_ETHMACRXEN ((uint32_t)0x08000000)
\r
4937 #define RCC_AHB1ENR_ETHMACPTPEN ((uint32_t)0x10000000)
\r
4938 #define RCC_AHB1ENR_OTGHSEN ((uint32_t)0x20000000)
\r
4939 #define RCC_AHB1ENR_OTGHSULPIEN ((uint32_t)0x40000000)
\r
4941 /******************** Bit definition for RCC_AHB2ENR register ***************/
\r
4942 #define RCC_AHB2ENR_DCMIEN ((uint32_t)0x00000001)
\r
4943 #define RCC_AHB2ENR_RNGEN ((uint32_t)0x00000040)
\r
4944 #define RCC_AHB2ENR_OTGFSEN ((uint32_t)0x00000080)
\r
4946 /******************** Bit definition for RCC_AHB3ENR register ***************/
\r
4948 #define RCC_AHB3ENR_FSMCEN ((uint32_t)0x00000001)
\r
4950 /******************** Bit definition for RCC_APB1ENR register ***************/
\r
4951 #define RCC_APB1ENR_TIM2EN ((uint32_t)0x00000001)
\r
4952 #define RCC_APB1ENR_TIM3EN ((uint32_t)0x00000002)
\r
4953 #define RCC_APB1ENR_TIM4EN ((uint32_t)0x00000004)
\r
4954 #define RCC_APB1ENR_TIM5EN ((uint32_t)0x00000008)
\r
4955 #define RCC_APB1ENR_TIM6EN ((uint32_t)0x00000010)
\r
4956 #define RCC_APB1ENR_TIM7EN ((uint32_t)0x00000020)
\r
4957 #define RCC_APB1ENR_TIM12EN ((uint32_t)0x00000040)
\r
4958 #define RCC_APB1ENR_TIM13EN ((uint32_t)0x00000080)
\r
4959 #define RCC_APB1ENR_TIM14EN ((uint32_t)0x00000100)
\r
4960 #define RCC_APB1ENR_WWDGEN ((uint32_t)0x00000800)
\r
4961 #define RCC_APB1ENR_SPI2EN ((uint32_t)0x00004000)
\r
4962 #define RCC_APB1ENR_SPI3EN ((uint32_t)0x00008000)
\r
4963 #define RCC_APB1ENR_USART2EN ((uint32_t)0x00020000)
\r
4964 #define RCC_APB1ENR_USART3EN ((uint32_t)0x00040000)
\r
4965 #define RCC_APB1ENR_UART4EN ((uint32_t)0x00080000)
\r
4966 #define RCC_APB1ENR_UART5EN ((uint32_t)0x00100000)
\r
4967 #define RCC_APB1ENR_I2C1EN ((uint32_t)0x00200000)
\r
4968 #define RCC_APB1ENR_I2C2EN ((uint32_t)0x00400000)
\r
4969 #define RCC_APB1ENR_I2C3EN ((uint32_t)0x00800000)
\r
4970 #define RCC_APB1ENR_CAN1EN ((uint32_t)0x02000000)
\r
4971 #define RCC_APB1ENR_CAN2EN ((uint32_t)0x04000000)
\r
4972 #define RCC_APB1ENR_PWREN ((uint32_t)0x10000000)
\r
4973 #define RCC_APB1ENR_DACEN ((uint32_t)0x20000000)
\r
4975 /******************** Bit definition for RCC_APB2ENR register ***************/
\r
4976 #define RCC_APB2ENR_TIM1EN ((uint32_t)0x00000001)
\r
4977 #define RCC_APB2ENR_TIM8EN ((uint32_t)0x00000002)
\r
4978 #define RCC_APB2ENR_USART1EN ((uint32_t)0x00000010)
\r
4979 #define RCC_APB2ENR_USART6EN ((uint32_t)0x00000020)
\r
4980 #define RCC_APB2ENR_ADC1EN ((uint32_t)0x00000100)
\r
4981 #define RCC_APB2ENR_ADC2EN ((uint32_t)0x00000200)
\r
4982 #define RCC_APB2ENR_ADC3EN ((uint32_t)0x00000400)
\r
4983 #define RCC_APB2ENR_SDIOEN ((uint32_t)0x00000800)
\r
4984 #define RCC_APB2ENR_SPI1EN ((uint32_t)0x00001000)
\r
4985 #define RCC_APB2ENR_SYSCFGEN ((uint32_t)0x00004000)
\r
4986 #define RCC_APB2ENR_TIM9EN ((uint32_t)0x00010000)
\r
4987 #define RCC_APB2ENR_TIM10EN ((uint32_t)0x00020000)
\r
4988 #define RCC_APB2ENR_TIM11EN ((uint32_t)0x00040000)
\r
4989 #define RCC_APB2ENR_SPI5EN ((uint32_t)0x00100000)
\r
4990 #define RCC_APB2ENR_SPI6EN ((uint32_t)0x00200000)
\r
4992 /******************** Bit definition for RCC_AHB1LPENR register *************/
\r
4993 #define RCC_AHB1LPENR_GPIOALPEN ((uint32_t)0x00000001)
\r
4994 #define RCC_AHB1LPENR_GPIOBLPEN ((uint32_t)0x00000002)
\r
4995 #define RCC_AHB1LPENR_GPIOCLPEN ((uint32_t)0x00000004)
\r
4996 #define RCC_AHB1LPENR_GPIODLPEN ((uint32_t)0x00000008)
\r
4997 #define RCC_AHB1LPENR_GPIOELPEN ((uint32_t)0x00000010)
\r
4998 #define RCC_AHB1LPENR_GPIOFLPEN ((uint32_t)0x00000020)
\r
4999 #define RCC_AHB1LPENR_GPIOGLPEN ((uint32_t)0x00000040)
\r
5000 #define RCC_AHB1LPENR_GPIOHLPEN ((uint32_t)0x00000080)
\r
5001 #define RCC_AHB1LPENR_GPIOILPEN ((uint32_t)0x00000100)
\r
5002 #define RCC_AHB1LPENR_CRCLPEN ((uint32_t)0x00001000)
\r
5003 #define RCC_AHB1LPENR_FLITFLPEN ((uint32_t)0x00008000)
\r
5004 #define RCC_AHB1LPENR_SRAM1LPEN ((uint32_t)0x00010000)
\r
5005 #define RCC_AHB1LPENR_SRAM2LPEN ((uint32_t)0x00020000)
\r
5006 #define RCC_AHB1LPENR_BKPSRAMLPEN ((uint32_t)0x00040000)
\r
5007 #define RCC_AHB1LPENR_SRAM3LPEN ((uint32_t)0x00080000)
\r
5008 #define RCC_AHB1LPENR_DMA1LPEN ((uint32_t)0x00200000)
\r
5009 #define RCC_AHB1LPENR_DMA2LPEN ((uint32_t)0x00400000)
\r
5010 #define RCC_AHB1LPENR_ETHMACLPEN ((uint32_t)0x02000000)
\r
5011 #define RCC_AHB1LPENR_ETHMACTXLPEN ((uint32_t)0x04000000)
\r
5012 #define RCC_AHB1LPENR_ETHMACRXLPEN ((uint32_t)0x08000000)
\r
5013 #define RCC_AHB1LPENR_ETHMACPTPLPEN ((uint32_t)0x10000000)
\r
5014 #define RCC_AHB1LPENR_OTGHSLPEN ((uint32_t)0x20000000)
\r
5015 #define RCC_AHB1LPENR_OTGHSULPILPEN ((uint32_t)0x40000000)
\r
5017 /******************** Bit definition for RCC_AHB2LPENR register *************/
\r
5018 #define RCC_AHB2LPENR_DCMILPEN ((uint32_t)0x00000001)
\r
5019 #define RCC_AHB2LPENR_RNGLPEN ((uint32_t)0x00000040)
\r
5020 #define RCC_AHB2LPENR_OTGFSLPEN ((uint32_t)0x00000080)
\r
5022 /******************** Bit definition for RCC_AHB3LPENR register *************/
\r
5024 #define RCC_AHB3LPENR_FSMCLPEN ((uint32_t)0x00000001)
\r
5026 /******************** Bit definition for RCC_APB1LPENR register *************/
\r
5027 #define RCC_APB1LPENR_TIM2LPEN ((uint32_t)0x00000001)
\r
5028 #define RCC_APB1LPENR_TIM3LPEN ((uint32_t)0x00000002)
\r
5029 #define RCC_APB1LPENR_TIM4LPEN ((uint32_t)0x00000004)
\r
5030 #define RCC_APB1LPENR_TIM5LPEN ((uint32_t)0x00000008)
\r
5031 #define RCC_APB1LPENR_TIM6LPEN ((uint32_t)0x00000010)
\r
5032 #define RCC_APB1LPENR_TIM7LPEN ((uint32_t)0x00000020)
\r
5033 #define RCC_APB1LPENR_TIM12LPEN ((uint32_t)0x00000040)
\r
5034 #define RCC_APB1LPENR_TIM13LPEN ((uint32_t)0x00000080)
\r
5035 #define RCC_APB1LPENR_TIM14LPEN ((uint32_t)0x00000100)
\r
5036 #define RCC_APB1LPENR_WWDGLPEN ((uint32_t)0x00000800)
\r
5037 #define RCC_APB1LPENR_SPI2LPEN ((uint32_t)0x00004000)
\r
5038 #define RCC_APB1LPENR_SPI3LPEN ((uint32_t)0x00008000)
\r
5039 #define RCC_APB1LPENR_USART2LPEN ((uint32_t)0x00020000)
\r
5040 #define RCC_APB1LPENR_USART3LPEN ((uint32_t)0x00040000)
\r
5041 #define RCC_APB1LPENR_UART4LPEN ((uint32_t)0x00080000)
\r
5042 #define RCC_APB1LPENR_UART5LPEN ((uint32_t)0x00100000)
\r
5043 #define RCC_APB1LPENR_I2C1LPEN ((uint32_t)0x00200000)
\r
5044 #define RCC_APB1LPENR_I2C2LPEN ((uint32_t)0x00400000)
\r
5045 #define RCC_APB1LPENR_I2C3LPEN ((uint32_t)0x00800000)
\r
5046 #define RCC_APB1LPENR_CAN1LPEN ((uint32_t)0x02000000)
\r
5047 #define RCC_APB1LPENR_CAN2LPEN ((uint32_t)0x04000000)
\r
5048 #define RCC_APB1LPENR_PWRLPEN ((uint32_t)0x10000000)
\r
5049 #define RCC_APB1LPENR_DACLPEN ((uint32_t)0x20000000)
\r
5051 /******************** Bit definition for RCC_APB2LPENR register *************/
\r
5052 #define RCC_APB2LPENR_TIM1LPEN ((uint32_t)0x00000001)
\r
5053 #define RCC_APB2LPENR_TIM8LPEN ((uint32_t)0x00000002)
\r
5054 #define RCC_APB2LPENR_USART1LPEN ((uint32_t)0x00000010)
\r
5055 #define RCC_APB2LPENR_USART6LPEN ((uint32_t)0x00000020)
\r
5056 #define RCC_APB2LPENR_ADC1LPEN ((uint32_t)0x00000100)
\r
5057 #define RCC_APB2LPENR_ADC2LPEN ((uint32_t)0x00000200)
\r
5058 #define RCC_APB2LPENR_ADC3LPEN ((uint32_t)0x00000400)
\r
5059 #define RCC_APB2LPENR_SDIOLPEN ((uint32_t)0x00000800)
\r
5060 #define RCC_APB2LPENR_SPI1LPEN ((uint32_t)0x00001000)
\r
5061 #define RCC_APB2LPENR_SYSCFGLPEN ((uint32_t)0x00004000)
\r
5062 #define RCC_APB2LPENR_TIM9LPEN ((uint32_t)0x00010000)
\r
5063 #define RCC_APB2LPENR_TIM10LPEN ((uint32_t)0x00020000)
\r
5064 #define RCC_APB2LPENR_TIM11LPEN ((uint32_t)0x00040000)
\r
5066 /******************** Bit definition for RCC_BDCR register ******************/
\r
5067 #define RCC_BDCR_LSEON ((uint32_t)0x00000001)
\r
5068 #define RCC_BDCR_LSERDY ((uint32_t)0x00000002)
\r
5069 #define RCC_BDCR_LSEBYP ((uint32_t)0x00000004)
\r
5071 #define RCC_BDCR_RTCSEL ((uint32_t)0x00000300)
\r
5072 #define RCC_BDCR_RTCSEL_0 ((uint32_t)0x00000100)
\r
5073 #define RCC_BDCR_RTCSEL_1 ((uint32_t)0x00000200)
\r
5075 #define RCC_BDCR_RTCEN ((uint32_t)0x00008000)
\r
5076 #define RCC_BDCR_BDRST ((uint32_t)0x00010000)
\r
5078 /******************** Bit definition for RCC_CSR register *******************/
\r
5079 #define RCC_CSR_LSION ((uint32_t)0x00000001)
\r
5080 #define RCC_CSR_LSIRDY ((uint32_t)0x00000002)
\r
5081 #define RCC_CSR_RMVF ((uint32_t)0x01000000)
\r
5082 #define RCC_CSR_BORRSTF ((uint32_t)0x02000000)
\r
5083 #define RCC_CSR_PADRSTF ((uint32_t)0x04000000)
\r
5084 #define RCC_CSR_PORRSTF ((uint32_t)0x08000000)
\r
5085 #define RCC_CSR_SFTRSTF ((uint32_t)0x10000000)
\r
5086 #define RCC_CSR_WDGRSTF ((uint32_t)0x20000000)
\r
5087 #define RCC_CSR_WWDGRSTF ((uint32_t)0x40000000)
\r
5088 #define RCC_CSR_LPWRRSTF ((uint32_t)0x80000000)
\r
5090 /******************** Bit definition for RCC_SSCGR register *****************/
\r
5091 #define RCC_SSCGR_MODPER ((uint32_t)0x00001FFF)
\r
5092 #define RCC_SSCGR_INCSTEP ((uint32_t)0x0FFFE000)
\r
5093 #define RCC_SSCGR_SPREADSEL ((uint32_t)0x40000000)
\r
5094 #define RCC_SSCGR_SSCGEN ((uint32_t)0x80000000)
\r
5096 /******************** Bit definition for RCC_PLLI2SCFGR register ************/
\r
5097 #define RCC_PLLI2SCFGR_PLLI2SN ((uint32_t)0x00007FC0)
\r
5098 #define RCC_PLLI2SCFGR_PLLI2SN_0 ((uint32_t)0x00000040)
\r
5099 #define RCC_PLLI2SCFGR_PLLI2SN_1 ((uint32_t)0x00000080)
\r
5100 #define RCC_PLLI2SCFGR_PLLI2SN_2 ((uint32_t)0x00000100)
\r
5101 #define RCC_PLLI2SCFGR_PLLI2SN_3 ((uint32_t)0x00000200)
\r
5102 #define RCC_PLLI2SCFGR_PLLI2SN_4 ((uint32_t)0x00000400)
\r
5103 #define RCC_PLLI2SCFGR_PLLI2SN_5 ((uint32_t)0x00000800)
\r
5104 #define RCC_PLLI2SCFGR_PLLI2SN_6 ((uint32_t)0x00001000)
\r
5105 #define RCC_PLLI2SCFGR_PLLI2SN_7 ((uint32_t)0x00002000)
\r
5106 #define RCC_PLLI2SCFGR_PLLI2SN_8 ((uint32_t)0x00004000)
\r
5108 #define RCC_PLLI2SCFGR_PLLI2SR ((uint32_t)0x70000000)
\r
5109 #define RCC_PLLI2SCFGR_PLLI2SR_0 ((uint32_t)0x10000000)
\r
5110 #define RCC_PLLI2SCFGR_PLLI2SR_1 ((uint32_t)0x20000000)
\r
5111 #define RCC_PLLI2SCFGR_PLLI2SR_2 ((uint32_t)0x40000000)
\r
5113 /******************************************************************************/
\r
5117 /******************************************************************************/
\r
5118 /******************** Bits definition for RNG_CR register *******************/
\r
5119 #define RNG_CR_RNGEN ((uint32_t)0x00000004)
\r
5120 #define RNG_CR_IE ((uint32_t)0x00000008)
\r
5122 /******************** Bits definition for RNG_SR register *******************/
\r
5123 #define RNG_SR_DRDY ((uint32_t)0x00000001)
\r
5124 #define RNG_SR_CECS ((uint32_t)0x00000002)
\r
5125 #define RNG_SR_SECS ((uint32_t)0x00000004)
\r
5126 #define RNG_SR_CEIS ((uint32_t)0x00000020)
\r
5127 #define RNG_SR_SEIS ((uint32_t)0x00000040)
\r
5129 /******************************************************************************/
\r
5131 /* Real-Time Clock (RTC) */
\r
5133 /******************************************************************************/
\r
5134 /******************** Bits definition for RTC_TR register *******************/
\r
5135 #define RTC_TR_PM ((uint32_t)0x00400000)
\r
5136 #define RTC_TR_HT ((uint32_t)0x00300000)
\r
5137 #define RTC_TR_HT_0 ((uint32_t)0x00100000)
\r
5138 #define RTC_TR_HT_1 ((uint32_t)0x00200000)
\r
5139 #define RTC_TR_HU ((uint32_t)0x000F0000)
\r
5140 #define RTC_TR_HU_0 ((uint32_t)0x00010000)
\r
5141 #define RTC_TR_HU_1 ((uint32_t)0x00020000)
\r
5142 #define RTC_TR_HU_2 ((uint32_t)0x00040000)
\r
5143 #define RTC_TR_HU_3 ((uint32_t)0x00080000)
\r
5144 #define RTC_TR_MNT ((uint32_t)0x00007000)
\r
5145 #define RTC_TR_MNT_0 ((uint32_t)0x00001000)
\r
5146 #define RTC_TR_MNT_1 ((uint32_t)0x00002000)
\r
5147 #define RTC_TR_MNT_2 ((uint32_t)0x00004000)
\r
5148 #define RTC_TR_MNU ((uint32_t)0x00000F00)
\r
5149 #define RTC_TR_MNU_0 ((uint32_t)0x00000100)
\r
5150 #define RTC_TR_MNU_1 ((uint32_t)0x00000200)
\r
5151 #define RTC_TR_MNU_2 ((uint32_t)0x00000400)
\r
5152 #define RTC_TR_MNU_3 ((uint32_t)0x00000800)
\r
5153 #define RTC_TR_ST ((uint32_t)0x00000070)
\r
5154 #define RTC_TR_ST_0 ((uint32_t)0x00000010)
\r
5155 #define RTC_TR_ST_1 ((uint32_t)0x00000020)
\r
5156 #define RTC_TR_ST_2 ((uint32_t)0x00000040)
\r
5157 #define RTC_TR_SU ((uint32_t)0x0000000F)
\r
5158 #define RTC_TR_SU_0 ((uint32_t)0x00000001)
\r
5159 #define RTC_TR_SU_1 ((uint32_t)0x00000002)
\r
5160 #define RTC_TR_SU_2 ((uint32_t)0x00000004)
\r
5161 #define RTC_TR_SU_3 ((uint32_t)0x00000008)
\r
5163 /******************** Bits definition for RTC_DR register *******************/
\r
5164 #define RTC_DR_YT ((uint32_t)0x00F00000)
\r
5165 #define RTC_DR_YT_0 ((uint32_t)0x00100000)
\r
5166 #define RTC_DR_YT_1 ((uint32_t)0x00200000)
\r
5167 #define RTC_DR_YT_2 ((uint32_t)0x00400000)
\r
5168 #define RTC_DR_YT_3 ((uint32_t)0x00800000)
\r
5169 #define RTC_DR_YU ((uint32_t)0x000F0000)
\r
5170 #define RTC_DR_YU_0 ((uint32_t)0x00010000)
\r
5171 #define RTC_DR_YU_1 ((uint32_t)0x00020000)
\r
5172 #define RTC_DR_YU_2 ((uint32_t)0x00040000)
\r
5173 #define RTC_DR_YU_3 ((uint32_t)0x00080000)
\r
5174 #define RTC_DR_WDU ((uint32_t)0x0000E000)
\r
5175 #define RTC_DR_WDU_0 ((uint32_t)0x00002000)
\r
5176 #define RTC_DR_WDU_1 ((uint32_t)0x00004000)
\r
5177 #define RTC_DR_WDU_2 ((uint32_t)0x00008000)
\r
5178 #define RTC_DR_MT ((uint32_t)0x00001000)
\r
5179 #define RTC_DR_MU ((uint32_t)0x00000F00)
\r
5180 #define RTC_DR_MU_0 ((uint32_t)0x00000100)
\r
5181 #define RTC_DR_MU_1 ((uint32_t)0x00000200)
\r
5182 #define RTC_DR_MU_2 ((uint32_t)0x00000400)
\r
5183 #define RTC_DR_MU_3 ((uint32_t)0x00000800)
\r
5184 #define RTC_DR_DT ((uint32_t)0x00000030)
\r
5185 #define RTC_DR_DT_0 ((uint32_t)0x00000010)
\r
5186 #define RTC_DR_DT_1 ((uint32_t)0x00000020)
\r
5187 #define RTC_DR_DU ((uint32_t)0x0000000F)
\r
5188 #define RTC_DR_DU_0 ((uint32_t)0x00000001)
\r
5189 #define RTC_DR_DU_1 ((uint32_t)0x00000002)
\r
5190 #define RTC_DR_DU_2 ((uint32_t)0x00000004)
\r
5191 #define RTC_DR_DU_3 ((uint32_t)0x00000008)
\r
5193 /******************** Bits definition for RTC_CR register *******************/
\r
5194 #define RTC_CR_COE ((uint32_t)0x00800000)
\r
5195 #define RTC_CR_OSEL ((uint32_t)0x00600000)
\r
5196 #define RTC_CR_OSEL_0 ((uint32_t)0x00200000)
\r
5197 #define RTC_CR_OSEL_1 ((uint32_t)0x00400000)
\r
5198 #define RTC_CR_POL ((uint32_t)0x00100000)
\r
5199 #define RTC_CR_COSEL ((uint32_t)0x00080000)
\r
5200 #define RTC_CR_BCK ((uint32_t)0x00040000)
\r
5201 #define RTC_CR_SUB1H ((uint32_t)0x00020000)
\r
5202 #define RTC_CR_ADD1H ((uint32_t)0x00010000)
\r
5203 #define RTC_CR_TSIE ((uint32_t)0x00008000)
\r
5204 #define RTC_CR_WUTIE ((uint32_t)0x00004000)
\r
5205 #define RTC_CR_ALRBIE ((uint32_t)0x00002000)
\r
5206 #define RTC_CR_ALRAIE ((uint32_t)0x00001000)
\r
5207 #define RTC_CR_TSE ((uint32_t)0x00000800)
\r
5208 #define RTC_CR_WUTE ((uint32_t)0x00000400)
\r
5209 #define RTC_CR_ALRBE ((uint32_t)0x00000200)
\r
5210 #define RTC_CR_ALRAE ((uint32_t)0x00000100)
\r
5211 #define RTC_CR_DCE ((uint32_t)0x00000080)
\r
5212 #define RTC_CR_FMT ((uint32_t)0x00000040)
\r
5213 #define RTC_CR_BYPSHAD ((uint32_t)0x00000020)
\r
5214 #define RTC_CR_REFCKON ((uint32_t)0x00000010)
\r
5215 #define RTC_CR_TSEDGE ((uint32_t)0x00000008)
\r
5216 #define RTC_CR_WUCKSEL ((uint32_t)0x00000007)
\r
5217 #define RTC_CR_WUCKSEL_0 ((uint32_t)0x00000001)
\r
5218 #define RTC_CR_WUCKSEL_1 ((uint32_t)0x00000002)
\r
5219 #define RTC_CR_WUCKSEL_2 ((uint32_t)0x00000004)
\r
5221 /******************** Bits definition for RTC_ISR register ******************/
\r
5222 #define RTC_ISR_RECALPF ((uint32_t)0x00010000)
\r
5223 #define RTC_ISR_TAMP1F ((uint32_t)0x00002000)
\r
5224 #define RTC_ISR_TAMP2F ((uint32_t)0x00004000)
\r
5225 #define RTC_ISR_TSOVF ((uint32_t)0x00001000)
\r
5226 #define RTC_ISR_TSF ((uint32_t)0x00000800)
\r
5227 #define RTC_ISR_WUTF ((uint32_t)0x00000400)
\r
5228 #define RTC_ISR_ALRBF ((uint32_t)0x00000200)
\r
5229 #define RTC_ISR_ALRAF ((uint32_t)0x00000100)
\r
5230 #define RTC_ISR_INIT ((uint32_t)0x00000080)
\r
5231 #define RTC_ISR_INITF ((uint32_t)0x00000040)
\r
5232 #define RTC_ISR_RSF ((uint32_t)0x00000020)
\r
5233 #define RTC_ISR_INITS ((uint32_t)0x00000010)
\r
5234 #define RTC_ISR_SHPF ((uint32_t)0x00000008)
\r
5235 #define RTC_ISR_WUTWF ((uint32_t)0x00000004)
\r
5236 #define RTC_ISR_ALRBWF ((uint32_t)0x00000002)
\r
5237 #define RTC_ISR_ALRAWF ((uint32_t)0x00000001)
\r
5239 /******************** Bits definition for RTC_PRER register *****************/
\r
5240 #define RTC_PRER_PREDIV_A ((uint32_t)0x007F0000)
\r
5241 #define RTC_PRER_PREDIV_S ((uint32_t)0x00001FFF)
\r
5243 /******************** Bits definition for RTC_WUTR register *****************/
\r
5244 #define RTC_WUTR_WUT ((uint32_t)0x0000FFFF)
\r
5246 /******************** Bits definition for RTC_CALIBR register ***************/
\r
5247 #define RTC_CALIBR_DCS ((uint32_t)0x00000080)
\r
5248 #define RTC_CALIBR_DC ((uint32_t)0x0000001F)
\r
5250 /******************** Bits definition for RTC_ALRMAR register ***************/
\r
5251 #define RTC_ALRMAR_MSK4 ((uint32_t)0x80000000)
\r
5252 #define RTC_ALRMAR_WDSEL ((uint32_t)0x40000000)
\r
5253 #define RTC_ALRMAR_DT ((uint32_t)0x30000000)
\r
5254 #define RTC_ALRMAR_DT_0 ((uint32_t)0x10000000)
\r
5255 #define RTC_ALRMAR_DT_1 ((uint32_t)0x20000000)
\r
5256 #define RTC_ALRMAR_DU ((uint32_t)0x0F000000)
\r
5257 #define RTC_ALRMAR_DU_0 ((uint32_t)0x01000000)
\r
5258 #define RTC_ALRMAR_DU_1 ((uint32_t)0x02000000)
\r
5259 #define RTC_ALRMAR_DU_2 ((uint32_t)0x04000000)
\r
5260 #define RTC_ALRMAR_DU_3 ((uint32_t)0x08000000)
\r
5261 #define RTC_ALRMAR_MSK3 ((uint32_t)0x00800000)
\r
5262 #define RTC_ALRMAR_PM ((uint32_t)0x00400000)
\r
5263 #define RTC_ALRMAR_HT ((uint32_t)0x00300000)
\r
5264 #define RTC_ALRMAR_HT_0 ((uint32_t)0x00100000)
\r
5265 #define RTC_ALRMAR_HT_1 ((uint32_t)0x00200000)
\r
5266 #define RTC_ALRMAR_HU ((uint32_t)0x000F0000)
\r
5267 #define RTC_ALRMAR_HU_0 ((uint32_t)0x00010000)
\r
5268 #define RTC_ALRMAR_HU_1 ((uint32_t)0x00020000)
\r
5269 #define RTC_ALRMAR_HU_2 ((uint32_t)0x00040000)
\r
5270 #define RTC_ALRMAR_HU_3 ((uint32_t)0x00080000)
\r
5271 #define RTC_ALRMAR_MSK2 ((uint32_t)0x00008000)
\r
5272 #define RTC_ALRMAR_MNT ((uint32_t)0x00007000)
\r
5273 #define RTC_ALRMAR_MNT_0 ((uint32_t)0x00001000)
\r
5274 #define RTC_ALRMAR_MNT_1 ((uint32_t)0x00002000)
\r
5275 #define RTC_ALRMAR_MNT_2 ((uint32_t)0x00004000)
\r
5276 #define RTC_ALRMAR_MNU ((uint32_t)0x00000F00)
\r
5277 #define RTC_ALRMAR_MNU_0 ((uint32_t)0x00000100)
\r
5278 #define RTC_ALRMAR_MNU_1 ((uint32_t)0x00000200)
\r
5279 #define RTC_ALRMAR_MNU_2 ((uint32_t)0x00000400)
\r
5280 #define RTC_ALRMAR_MNU_3 ((uint32_t)0x00000800)
\r
5281 #define RTC_ALRMAR_MSK1 ((uint32_t)0x00000080)
\r
5282 #define RTC_ALRMAR_ST ((uint32_t)0x00000070)
\r
5283 #define RTC_ALRMAR_ST_0 ((uint32_t)0x00000010)
\r
5284 #define RTC_ALRMAR_ST_1 ((uint32_t)0x00000020)
\r
5285 #define RTC_ALRMAR_ST_2 ((uint32_t)0x00000040)
\r
5286 #define RTC_ALRMAR_SU ((uint32_t)0x0000000F)
\r
5287 #define RTC_ALRMAR_SU_0 ((uint32_t)0x00000001)
\r
5288 #define RTC_ALRMAR_SU_1 ((uint32_t)0x00000002)
\r
5289 #define RTC_ALRMAR_SU_2 ((uint32_t)0x00000004)
\r
5290 #define RTC_ALRMAR_SU_3 ((uint32_t)0x00000008)
\r
5292 /******************** Bits definition for RTC_ALRMBR register ***************/
\r
5293 #define RTC_ALRMBR_MSK4 ((uint32_t)0x80000000)
\r
5294 #define RTC_ALRMBR_WDSEL ((uint32_t)0x40000000)
\r
5295 #define RTC_ALRMBR_DT ((uint32_t)0x30000000)
\r
5296 #define RTC_ALRMBR_DT_0 ((uint32_t)0x10000000)
\r
5297 #define RTC_ALRMBR_DT_1 ((uint32_t)0x20000000)
\r
5298 #define RTC_ALRMBR_DU ((uint32_t)0x0F000000)
\r
5299 #define RTC_ALRMBR_DU_0 ((uint32_t)0x01000000)
\r
5300 #define RTC_ALRMBR_DU_1 ((uint32_t)0x02000000)
\r
5301 #define RTC_ALRMBR_DU_2 ((uint32_t)0x04000000)
\r
5302 #define RTC_ALRMBR_DU_3 ((uint32_t)0x08000000)
\r
5303 #define RTC_ALRMBR_MSK3 ((uint32_t)0x00800000)
\r
5304 #define RTC_ALRMBR_PM ((uint32_t)0x00400000)
\r
5305 #define RTC_ALRMBR_HT ((uint32_t)0x00300000)
\r
5306 #define RTC_ALRMBR_HT_0 ((uint32_t)0x00100000)
\r
5307 #define RTC_ALRMBR_HT_1 ((uint32_t)0x00200000)
\r
5308 #define RTC_ALRMBR_HU ((uint32_t)0x000F0000)
\r
5309 #define RTC_ALRMBR_HU_0 ((uint32_t)0x00010000)
\r
5310 #define RTC_ALRMBR_HU_1 ((uint32_t)0x00020000)
\r
5311 #define RTC_ALRMBR_HU_2 ((uint32_t)0x00040000)
\r
5312 #define RTC_ALRMBR_HU_3 ((uint32_t)0x00080000)
\r
5313 #define RTC_ALRMBR_MSK2 ((uint32_t)0x00008000)
\r
5314 #define RTC_ALRMBR_MNT ((uint32_t)0x00007000)
\r
5315 #define RTC_ALRMBR_MNT_0 ((uint32_t)0x00001000)
\r
5316 #define RTC_ALRMBR_MNT_1 ((uint32_t)0x00002000)
\r
5317 #define RTC_ALRMBR_MNT_2 ((uint32_t)0x00004000)
\r
5318 #define RTC_ALRMBR_MNU ((uint32_t)0x00000F00)
\r
5319 #define RTC_ALRMBR_MNU_0 ((uint32_t)0x00000100)
\r
5320 #define RTC_ALRMBR_MNU_1 ((uint32_t)0x00000200)
\r
5321 #define RTC_ALRMBR_MNU_2 ((uint32_t)0x00000400)
\r
5322 #define RTC_ALRMBR_MNU_3 ((uint32_t)0x00000800)
\r
5323 #define RTC_ALRMBR_MSK1 ((uint32_t)0x00000080)
\r
5324 #define RTC_ALRMBR_ST ((uint32_t)0x00000070)
\r
5325 #define RTC_ALRMBR_ST_0 ((uint32_t)0x00000010)
\r
5326 #define RTC_ALRMBR_ST_1 ((uint32_t)0x00000020)
\r
5327 #define RTC_ALRMBR_ST_2 ((uint32_t)0x00000040)
\r
5328 #define RTC_ALRMBR_SU ((uint32_t)0x0000000F)
\r
5329 #define RTC_ALRMBR_SU_0 ((uint32_t)0x00000001)
\r
5330 #define RTC_ALRMBR_SU_1 ((uint32_t)0x00000002)
\r
5331 #define RTC_ALRMBR_SU_2 ((uint32_t)0x00000004)
\r
5332 #define RTC_ALRMBR_SU_3 ((uint32_t)0x00000008)
\r
5334 /******************** Bits definition for RTC_WPR register ******************/
\r
5335 #define RTC_WPR_KEY ((uint32_t)0x000000FF)
\r
5337 /******************** Bits definition for RTC_SSR register ******************/
\r
5338 #define RTC_SSR_SS ((uint32_t)0x0000FFFF)
\r
5340 /******************** Bits definition for RTC_SHIFTR register ***************/
\r
5341 #define RTC_SHIFTR_SUBFS ((uint32_t)0x00007FFF)
\r
5342 #define RTC_SHIFTR_ADD1S ((uint32_t)0x80000000)
\r
5344 /******************** Bits definition for RTC_TSTR register *****************/
\r
5345 #define RTC_TSTR_PM ((uint32_t)0x00400000)
\r
5346 #define RTC_TSTR_HT ((uint32_t)0x00300000)
\r
5347 #define RTC_TSTR_HT_0 ((uint32_t)0x00100000)
\r
5348 #define RTC_TSTR_HT_1 ((uint32_t)0x00200000)
\r
5349 #define RTC_TSTR_HU ((uint32_t)0x000F0000)
\r
5350 #define RTC_TSTR_HU_0 ((uint32_t)0x00010000)
\r
5351 #define RTC_TSTR_HU_1 ((uint32_t)0x00020000)
\r
5352 #define RTC_TSTR_HU_2 ((uint32_t)0x00040000)
\r
5353 #define RTC_TSTR_HU_3 ((uint32_t)0x00080000)
\r
5354 #define RTC_TSTR_MNT ((uint32_t)0x00007000)
\r
5355 #define RTC_TSTR_MNT_0 ((uint32_t)0x00001000)
\r
5356 #define RTC_TSTR_MNT_1 ((uint32_t)0x00002000)
\r
5357 #define RTC_TSTR_MNT_2 ((uint32_t)0x00004000)
\r
5358 #define RTC_TSTR_MNU ((uint32_t)0x00000F00)
\r
5359 #define RTC_TSTR_MNU_0 ((uint32_t)0x00000100)
\r
5360 #define RTC_TSTR_MNU_1 ((uint32_t)0x00000200)
\r
5361 #define RTC_TSTR_MNU_2 ((uint32_t)0x00000400)
\r
5362 #define RTC_TSTR_MNU_3 ((uint32_t)0x00000800)
\r
5363 #define RTC_TSTR_ST ((uint32_t)0x00000070)
\r
5364 #define RTC_TSTR_ST_0 ((uint32_t)0x00000010)
\r
5365 #define RTC_TSTR_ST_1 ((uint32_t)0x00000020)
\r
5366 #define RTC_TSTR_ST_2 ((uint32_t)0x00000040)
\r
5367 #define RTC_TSTR_SU ((uint32_t)0x0000000F)
\r
5368 #define RTC_TSTR_SU_0 ((uint32_t)0x00000001)
\r
5369 #define RTC_TSTR_SU_1 ((uint32_t)0x00000002)
\r
5370 #define RTC_TSTR_SU_2 ((uint32_t)0x00000004)
\r
5371 #define RTC_TSTR_SU_3 ((uint32_t)0x00000008)
\r
5373 /******************** Bits definition for RTC_TSDR register *****************/
\r
5374 #define RTC_TSDR_WDU ((uint32_t)0x0000E000)
\r
5375 #define RTC_TSDR_WDU_0 ((uint32_t)0x00002000)
\r
5376 #define RTC_TSDR_WDU_1 ((uint32_t)0x00004000)
\r
5377 #define RTC_TSDR_WDU_2 ((uint32_t)0x00008000)
\r
5378 #define RTC_TSDR_MT ((uint32_t)0x00001000)
\r
5379 #define RTC_TSDR_MU ((uint32_t)0x00000F00)
\r
5380 #define RTC_TSDR_MU_0 ((uint32_t)0x00000100)
\r
5381 #define RTC_TSDR_MU_1 ((uint32_t)0x00000200)
\r
5382 #define RTC_TSDR_MU_2 ((uint32_t)0x00000400)
\r
5383 #define RTC_TSDR_MU_3 ((uint32_t)0x00000800)
\r
5384 #define RTC_TSDR_DT ((uint32_t)0x00000030)
\r
5385 #define RTC_TSDR_DT_0 ((uint32_t)0x00000010)
\r
5386 #define RTC_TSDR_DT_1 ((uint32_t)0x00000020)
\r
5387 #define RTC_TSDR_DU ((uint32_t)0x0000000F)
\r
5388 #define RTC_TSDR_DU_0 ((uint32_t)0x00000001)
\r
5389 #define RTC_TSDR_DU_1 ((uint32_t)0x00000002)
\r
5390 #define RTC_TSDR_DU_2 ((uint32_t)0x00000004)
\r
5391 #define RTC_TSDR_DU_3 ((uint32_t)0x00000008)
\r
5393 /******************** Bits definition for RTC_TSSSR register ****************/
\r
5394 #define RTC_TSSSR_SS ((uint32_t)0x0000FFFF)
\r
5396 /******************** Bits definition for RTC_CAL register *****************/
\r
5397 #define RTC_CALR_CALP ((uint32_t)0x00008000)
\r
5398 #define RTC_CALR_CALW8 ((uint32_t)0x00004000)
\r
5399 #define RTC_CALR_CALW16 ((uint32_t)0x00002000)
\r
5400 #define RTC_CALR_CALM ((uint32_t)0x000001FF)
\r
5401 #define RTC_CALR_CALM_0 ((uint32_t)0x00000001)
\r
5402 #define RTC_CALR_CALM_1 ((uint32_t)0x00000002)
\r
5403 #define RTC_CALR_CALM_2 ((uint32_t)0x00000004)
\r
5404 #define RTC_CALR_CALM_3 ((uint32_t)0x00000008)
\r
5405 #define RTC_CALR_CALM_4 ((uint32_t)0x00000010)
\r
5406 #define RTC_CALR_CALM_5 ((uint32_t)0x00000020)
\r
5407 #define RTC_CALR_CALM_6 ((uint32_t)0x00000040)
\r
5408 #define RTC_CALR_CALM_7 ((uint32_t)0x00000080)
\r
5409 #define RTC_CALR_CALM_8 ((uint32_t)0x00000100)
\r
5411 /******************** Bits definition for RTC_TAFCR register ****************/
\r
5412 #define RTC_TAFCR_ALARMOUTTYPE ((uint32_t)0x00040000)
\r
5413 #define RTC_TAFCR_TSINSEL ((uint32_t)0x00020000)
\r
5414 #define RTC_TAFCR_TAMPINSEL ((uint32_t)0x00010000)
\r
5415 #define RTC_TAFCR_TAMPPUDIS ((uint32_t)0x00008000)
\r
5416 #define RTC_TAFCR_TAMPPRCH ((uint32_t)0x00006000)
\r
5417 #define RTC_TAFCR_TAMPPRCH_0 ((uint32_t)0x00002000)
\r
5418 #define RTC_TAFCR_TAMPPRCH_1 ((uint32_t)0x00004000)
\r
5419 #define RTC_TAFCR_TAMPFLT ((uint32_t)0x00001800)
\r
5420 #define RTC_TAFCR_TAMPFLT_0 ((uint32_t)0x00000800)
\r
5421 #define RTC_TAFCR_TAMPFLT_1 ((uint32_t)0x00001000)
\r
5422 #define RTC_TAFCR_TAMPFREQ ((uint32_t)0x00000700)
\r
5423 #define RTC_TAFCR_TAMPFREQ_0 ((uint32_t)0x00000100)
\r
5424 #define RTC_TAFCR_TAMPFREQ_1 ((uint32_t)0x00000200)
\r
5425 #define RTC_TAFCR_TAMPFREQ_2 ((uint32_t)0x00000400)
\r
5426 #define RTC_TAFCR_TAMPTS ((uint32_t)0x00000080)
\r
5427 #define RTC_TAFCR_TAMP2TRG ((uint32_t)0x00000010)
\r
5428 #define RTC_TAFCR_TAMP2E ((uint32_t)0x00000008)
\r
5429 #define RTC_TAFCR_TAMPIE ((uint32_t)0x00000004)
\r
5430 #define RTC_TAFCR_TAMP1TRG ((uint32_t)0x00000002)
\r
5431 #define RTC_TAFCR_TAMP1E ((uint32_t)0x00000001)
\r
5433 /******************** Bits definition for RTC_ALRMASSR register *************/
\r
5434 #define RTC_ALRMASSR_MASKSS ((uint32_t)0x0F000000)
\r
5435 #define RTC_ALRMASSR_MASKSS_0 ((uint32_t)0x01000000)
\r
5436 #define RTC_ALRMASSR_MASKSS_1 ((uint32_t)0x02000000)
\r
5437 #define RTC_ALRMASSR_MASKSS_2 ((uint32_t)0x04000000)
\r
5438 #define RTC_ALRMASSR_MASKSS_3 ((uint32_t)0x08000000)
\r
5439 #define RTC_ALRMASSR_SS ((uint32_t)0x00007FFF)
\r
5441 /******************** Bits definition for RTC_ALRMBSSR register *************/
\r
5442 #define RTC_ALRMBSSR_MASKSS ((uint32_t)0x0F000000)
\r
5443 #define RTC_ALRMBSSR_MASKSS_0 ((uint32_t)0x01000000)
\r
5444 #define RTC_ALRMBSSR_MASKSS_1 ((uint32_t)0x02000000)
\r
5445 #define RTC_ALRMBSSR_MASKSS_2 ((uint32_t)0x04000000)
\r
5446 #define RTC_ALRMBSSR_MASKSS_3 ((uint32_t)0x08000000)
\r
5447 #define RTC_ALRMBSSR_SS ((uint32_t)0x00007FFF)
\r
5449 /******************** Bits definition for RTC_BKP0R register ****************/
\r
5450 #define RTC_BKP0R ((uint32_t)0xFFFFFFFF)
\r
5452 /******************** Bits definition for RTC_BKP1R register ****************/
\r
5453 #define RTC_BKP1R ((uint32_t)0xFFFFFFFF)
\r
5455 /******************** Bits definition for RTC_BKP2R register ****************/
\r
5456 #define RTC_BKP2R ((uint32_t)0xFFFFFFFF)
\r
5458 /******************** Bits definition for RTC_BKP3R register ****************/
\r
5459 #define RTC_BKP3R ((uint32_t)0xFFFFFFFF)
\r
5461 /******************** Bits definition for RTC_BKP4R register ****************/
\r
5462 #define RTC_BKP4R ((uint32_t)0xFFFFFFFF)
\r
5464 /******************** Bits definition for RTC_BKP5R register ****************/
\r
5465 #define RTC_BKP5R ((uint32_t)0xFFFFFFFF)
\r
5467 /******************** Bits definition for RTC_BKP6R register ****************/
\r
5468 #define RTC_BKP6R ((uint32_t)0xFFFFFFFF)
\r
5470 /******************** Bits definition for RTC_BKP7R register ****************/
\r
5471 #define RTC_BKP7R ((uint32_t)0xFFFFFFFF)
\r
5473 /******************** Bits definition for RTC_BKP8R register ****************/
\r
5474 #define RTC_BKP8R ((uint32_t)0xFFFFFFFF)
\r
5476 /******************** Bits definition for RTC_BKP9R register ****************/
\r
5477 #define RTC_BKP9R ((uint32_t)0xFFFFFFFF)
\r
5479 /******************** Bits definition for RTC_BKP10R register ***************/
\r
5480 #define RTC_BKP10R ((uint32_t)0xFFFFFFFF)
\r
5482 /******************** Bits definition for RTC_BKP11R register ***************/
\r
5483 #define RTC_BKP11R ((uint32_t)0xFFFFFFFF)
\r
5485 /******************** Bits definition for RTC_BKP12R register ***************/
\r
5486 #define RTC_BKP12R ((uint32_t)0xFFFFFFFF)
\r
5488 /******************** Bits definition for RTC_BKP13R register ***************/
\r
5489 #define RTC_BKP13R ((uint32_t)0xFFFFFFFF)
\r
5491 /******************** Bits definition for RTC_BKP14R register ***************/
\r
5492 #define RTC_BKP14R ((uint32_t)0xFFFFFFFF)
\r
5494 /******************** Bits definition for RTC_BKP15R register ***************/
\r
5495 #define RTC_BKP15R ((uint32_t)0xFFFFFFFF)
\r
5497 /******************** Bits definition for RTC_BKP16R register ***************/
\r
5498 #define RTC_BKP16R ((uint32_t)0xFFFFFFFF)
\r
5500 /******************** Bits definition for RTC_BKP17R register ***************/
\r
5501 #define RTC_BKP17R ((uint32_t)0xFFFFFFFF)
\r
5503 /******************** Bits definition for RTC_BKP18R register ***************/
\r
5504 #define RTC_BKP18R ((uint32_t)0xFFFFFFFF)
\r
5506 /******************** Bits definition for RTC_BKP19R register ***************/
\r
5507 #define RTC_BKP19R ((uint32_t)0xFFFFFFFF)
\r
5511 /******************************************************************************/
\r
5513 /* SD host Interface */
\r
5515 /******************************************************************************/
\r
5516 /****************** Bit definition for SDIO_POWER register ******************/
\r
5517 #define SDIO_POWER_PWRCTRL ((uint32_t)0x03) /*!<PWRCTRL[1:0] bits (Power supply control bits) */
\r
5518 #define SDIO_POWER_PWRCTRL_0 ((uint32_t)0x01) /*!<Bit 0 */
\r
5519 #define SDIO_POWER_PWRCTRL_1 ((uint32_t)0x02) /*!<Bit 1 */
\r
5521 /****************** Bit definition for SDIO_CLKCR register ******************/
\r
5522 #define SDIO_CLKCR_CLKDIV ((uint32_t)0x00FF) /*!<Clock divide factor */
\r
5523 #define SDIO_CLKCR_CLKEN ((uint32_t)0x0100) /*!<Clock enable bit */
\r
5524 #define SDIO_CLKCR_PWRSAV ((uint32_t)0x0200) /*!<Power saving configuration bit */
\r
5525 #define SDIO_CLKCR_BYPASS ((uint32_t)0x0400) /*!<Clock divider bypass enable bit */
\r
5527 #define SDIO_CLKCR_WIDBUS ((uint32_t)0x1800) /*!<WIDBUS[1:0] bits (Wide bus mode enable bit) */
\r
5528 #define SDIO_CLKCR_WIDBUS_0 ((uint32_t)0x0800) /*!<Bit 0 */
\r
5529 #define SDIO_CLKCR_WIDBUS_1 ((uint32_t)0x1000) /*!<Bit 1 */
\r
5531 #define SDIO_CLKCR_NEGEDGE ((uint32_t)0x2000) /*!<SDIO_CK dephasing selection bit */
\r
5532 #define SDIO_CLKCR_HWFC_EN ((uint32_t)0x4000) /*!<HW Flow Control enable */
\r
5534 /******************* Bit definition for SDIO_ARG register *******************/
\r
5535 #define SDIO_ARG_CMDARG ((uint32_t)0xFFFFFFFF) /*!<Command argument */
\r
5537 /******************* Bit definition for SDIO_CMD register *******************/
\r
5538 #define SDIO_CMD_CMDINDEX ((uint32_t)0x003F) /*!<Command Index */
\r
5540 #define SDIO_CMD_WAITRESP ((uint32_t)0x00C0) /*!<WAITRESP[1:0] bits (Wait for response bits) */
\r
5541 #define SDIO_CMD_WAITRESP_0 ((uint32_t)0x0040) /*!< Bit 0 */
\r
5542 #define SDIO_CMD_WAITRESP_1 ((uint32_t)0x0080) /*!< Bit 1 */
\r
5544 #define SDIO_CMD_WAITINT ((uint32_t)0x0100) /*!<CPSM Waits for Interrupt Request */
\r
5545 #define SDIO_CMD_WAITPEND ((uint32_t)0x0200) /*!<CPSM Waits for ends of data transfer (CmdPend internal signal) */
\r
5546 #define SDIO_CMD_CPSMEN ((uint32_t)0x0400) /*!<Command path state machine (CPSM) Enable bit */
\r
5547 #define SDIO_CMD_SDIOSUSPEND ((uint32_t)0x0800) /*!<SD I/O suspend command */
\r
5548 #define SDIO_CMD_ENCMDCOMPL ((uint32_t)0x1000) /*!<Enable CMD completion */
\r
5549 #define SDIO_CMD_NIEN ((uint32_t)0x2000) /*!<Not Interrupt Enable */
\r
5550 #define SDIO_CMD_CEATACMD ((uint32_t)0x4000) /*!<CE-ATA command */
\r
5552 /***************** Bit definition for SDIO_RESPCMD register *****************/
\r
5553 #define SDIO_RESPCMD_RESPCMD ((uint32_t)0x3F) /*!<Response command index */
\r
5555 /****************** Bit definition for SDIO_RESP0 register ******************/
\r
5556 #define SDIO_RESP0_CARDSTATUS0 ((uint32_t)0xFFFFFFFF) /*!<Card Status */
\r
5558 /****************** Bit definition for SDIO_RESP1 register ******************/
\r
5559 #define SDIO_RESP1_CARDSTATUS1 ((uint32_t)0xFFFFFFFF) /*!<Card Status */
\r
5561 /****************** Bit definition for SDIO_RESP2 register ******************/
\r
5562 #define SDIO_RESP2_CARDSTATUS2 ((uint32_t)0xFFFFFFFF) /*!<Card Status */
\r
5564 /****************** Bit definition for SDIO_RESP3 register ******************/
\r
5565 #define SDIO_RESP3_CARDSTATUS3 ((uint32_t)0xFFFFFFFF) /*!<Card Status */
\r
5567 /****************** Bit definition for SDIO_RESP4 register ******************/
\r
5568 #define SDIO_RESP4_CARDSTATUS4 ((uint32_t)0xFFFFFFFF) /*!<Card Status */
\r
5570 /****************** Bit definition for SDIO_DTIMER register *****************/
\r
5571 #define SDIO_DTIMER_DATATIME ((uint32_t)0xFFFFFFFF) /*!<Data timeout period. */
\r
5573 /****************** Bit definition for SDIO_DLEN register *******************/
\r
5574 #define SDIO_DLEN_DATALENGTH ((uint32_t)0x01FFFFFF) /*!<Data length value */
\r
5576 /****************** Bit definition for SDIO_DCTRL register ******************/
\r
5577 #define SDIO_DCTRL_DTEN ((uint32_t)0x0001) /*!<Data transfer enabled bit */
\r
5578 #define SDIO_DCTRL_DTDIR ((uint32_t)0x0002) /*!<Data transfer direction selection */
\r
5579 #define SDIO_DCTRL_DTMODE ((uint32_t)0x0004) /*!<Data transfer mode selection */
\r
5580 #define SDIO_DCTRL_DMAEN ((uint32_t)0x0008) /*!<DMA enabled bit */
\r
5582 #define SDIO_DCTRL_DBLOCKSIZE ((uint32_t)0x00F0) /*!<DBLOCKSIZE[3:0] bits (Data block size) */
\r
5583 #define SDIO_DCTRL_DBLOCKSIZE_0 ((uint32_t)0x0010) /*!<Bit 0 */
\r
5584 #define SDIO_DCTRL_DBLOCKSIZE_1 ((uint32_t)0x0020) /*!<Bit 1 */
\r
5585 #define SDIO_DCTRL_DBLOCKSIZE_2 ((uint32_t)0x0040) /*!<Bit 2 */
\r
5586 #define SDIO_DCTRL_DBLOCKSIZE_3 ((uint32_t)0x0080) /*!<Bit 3 */
\r
5588 #define SDIO_DCTRL_RWSTART ((uint32_t)0x0100) /*!<Read wait start */
\r
5589 #define SDIO_DCTRL_RWSTOP ((uint32_t)0x0200) /*!<Read wait stop */
\r
5590 #define SDIO_DCTRL_RWMOD ((uint32_t)0x0400) /*!<Read wait mode */
\r
5591 #define SDIO_DCTRL_SDIOEN ((uint32_t)0x0800) /*!<SD I/O enable functions */
\r
5593 /****************** Bit definition for SDIO_DCOUNT register *****************/
\r
5594 #define SDIO_DCOUNT_DATACOUNT ((uint32_t)0x01FFFFFF) /*!<Data count value */
\r
5596 /****************** Bit definition for SDIO_STA register ********************/
\r
5597 #define SDIO_STA_CCRCFAIL ((uint32_t)0x00000001) /*!<Command response received (CRC check failed) */
\r
5598 #define SDIO_STA_DCRCFAIL ((uint32_t)0x00000002) /*!<Data block sent/received (CRC check failed) */
\r
5599 #define SDIO_STA_CTIMEOUT ((uint32_t)0x00000004) /*!<Command response timeout */
\r
5600 #define SDIO_STA_DTIMEOUT ((uint32_t)0x00000008) /*!<Data timeout */
\r
5601 #define SDIO_STA_TXUNDERR ((uint32_t)0x00000010) /*!<Transmit FIFO underrun error */
\r
5602 #define SDIO_STA_RXOVERR ((uint32_t)0x00000020) /*!<Received FIFO overrun error */
\r
5603 #define SDIO_STA_CMDREND ((uint32_t)0x00000040) /*!<Command response received (CRC check passed) */
\r
5604 #define SDIO_STA_CMDSENT ((uint32_t)0x00000080) /*!<Command sent (no response required) */
\r
5605 #define SDIO_STA_DATAEND ((uint32_t)0x00000100) /*!<Data end (data counter, SDIDCOUNT, is zero) */
\r
5606 #define SDIO_STA_STBITERR ((uint32_t)0x00000200) /*!<Start bit not detected on all data signals in wide bus mode */
\r
5607 #define SDIO_STA_DBCKEND ((uint32_t)0x00000400) /*!<Data block sent/received (CRC check passed) */
\r
5608 #define SDIO_STA_CMDACT ((uint32_t)0x00000800) /*!<Command transfer in progress */
\r
5609 #define SDIO_STA_TXACT ((uint32_t)0x00001000) /*!<Data transmit in progress */
\r
5610 #define SDIO_STA_RXACT ((uint32_t)0x00002000) /*!<Data receive in progress */
\r
5611 #define SDIO_STA_TXFIFOHE ((uint32_t)0x00004000) /*!<Transmit FIFO Half Empty: at least 8 words can be written into the FIFO */
\r
5612 #define SDIO_STA_RXFIFOHF ((uint32_t)0x00008000) /*!<Receive FIFO Half Full: there are at least 8 words in the FIFO */
\r
5613 #define SDIO_STA_TXFIFOF ((uint32_t)0x00010000) /*!<Transmit FIFO full */
\r
5614 #define SDIO_STA_RXFIFOF ((uint32_t)0x00020000) /*!<Receive FIFO full */
\r
5615 #define SDIO_STA_TXFIFOE ((uint32_t)0x00040000) /*!<Transmit FIFO empty */
\r
5616 #define SDIO_STA_RXFIFOE ((uint32_t)0x00080000) /*!<Receive FIFO empty */
\r
5617 #define SDIO_STA_TXDAVL ((uint32_t)0x00100000) /*!<Data available in transmit FIFO */
\r
5618 #define SDIO_STA_RXDAVL ((uint32_t)0x00200000) /*!<Data available in receive FIFO */
\r
5619 #define SDIO_STA_SDIOIT ((uint32_t)0x00400000) /*!<SDIO interrupt received */
\r
5620 #define SDIO_STA_CEATAEND ((uint32_t)0x00800000) /*!<CE-ATA command completion signal received for CMD61 */
\r
5622 /******************* Bit definition for SDIO_ICR register *******************/
\r
5623 #define SDIO_ICR_CCRCFAILC ((uint32_t)0x00000001) /*!<CCRCFAIL flag clear bit */
\r
5624 #define SDIO_ICR_DCRCFAILC ((uint32_t)0x00000002) /*!<DCRCFAIL flag clear bit */
\r
5625 #define SDIO_ICR_CTIMEOUTC ((uint32_t)0x00000004) /*!<CTIMEOUT flag clear bit */
\r
5626 #define SDIO_ICR_DTIMEOUTC ((uint32_t)0x00000008) /*!<DTIMEOUT flag clear bit */
\r
5627 #define SDIO_ICR_TXUNDERRC ((uint32_t)0x00000010) /*!<TXUNDERR flag clear bit */
\r
5628 #define SDIO_ICR_RXOVERRC ((uint32_t)0x00000020) /*!<RXOVERR flag clear bit */
\r
5629 #define SDIO_ICR_CMDRENDC ((uint32_t)0x00000040) /*!<CMDREND flag clear bit */
\r
5630 #define SDIO_ICR_CMDSENTC ((uint32_t)0x00000080) /*!<CMDSENT flag clear bit */
\r
5631 #define SDIO_ICR_DATAENDC ((uint32_t)0x00000100) /*!<DATAEND flag clear bit */
\r
5632 #define SDIO_ICR_STBITERRC ((uint32_t)0x00000200) /*!<STBITERR flag clear bit */
\r
5633 #define SDIO_ICR_DBCKENDC ((uint32_t)0x00000400) /*!<DBCKEND flag clear bit */
\r
5634 #define SDIO_ICR_SDIOITC ((uint32_t)0x00400000) /*!<SDIOIT flag clear bit */
\r
5635 #define SDIO_ICR_CEATAENDC ((uint32_t)0x00800000) /*!<CEATAEND flag clear bit */
\r
5637 /****************** Bit definition for SDIO_MASK register *******************/
\r
5638 #define SDIO_MASK_CCRCFAILIE ((uint32_t)0x00000001) /*!<Command CRC Fail Interrupt Enable */
\r
5639 #define SDIO_MASK_DCRCFAILIE ((uint32_t)0x00000002) /*!<Data CRC Fail Interrupt Enable */
\r
5640 #define SDIO_MASK_CTIMEOUTIE ((uint32_t)0x00000004) /*!<Command TimeOut Interrupt Enable */
\r
5641 #define SDIO_MASK_DTIMEOUTIE ((uint32_t)0x00000008) /*!<Data TimeOut Interrupt Enable */
\r
5642 #define SDIO_MASK_TXUNDERRIE ((uint32_t)0x00000010) /*!<Tx FIFO UnderRun Error Interrupt Enable */
\r
5643 #define SDIO_MASK_RXOVERRIE ((uint32_t)0x00000020) /*!<Rx FIFO OverRun Error Interrupt Enable */
\r
5644 #define SDIO_MASK_CMDRENDIE ((uint32_t)0x00000040) /*!<Command Response Received Interrupt Enable */
\r
5645 #define SDIO_MASK_CMDSENTIE ((uint32_t)0x00000080) /*!<Command Sent Interrupt Enable */
\r
5646 #define SDIO_MASK_DATAENDIE ((uint32_t)0x00000100) /*!<Data End Interrupt Enable */
\r
5647 #define SDIO_MASK_STBITERRIE ((uint32_t)0x00000200) /*!<Start Bit Error Interrupt Enable */
\r
5648 #define SDIO_MASK_DBCKENDIE ((uint32_t)0x00000400) /*!<Data Block End Interrupt Enable */
\r
5649 #define SDIO_MASK_CMDACTIE ((uint32_t)0x00000800) /*!<CCommand Acting Interrupt Enable */
\r
5650 #define SDIO_MASK_TXACTIE ((uint32_t)0x00001000) /*!<Data Transmit Acting Interrupt Enable */
\r
5651 #define SDIO_MASK_RXACTIE ((uint32_t)0x00002000) /*!<Data receive acting interrupt enabled */
\r
5652 #define SDIO_MASK_TXFIFOHEIE ((uint32_t)0x00004000) /*!<Tx FIFO Half Empty interrupt Enable */
\r
5653 #define SDIO_MASK_RXFIFOHFIE ((uint32_t)0x00008000) /*!<Rx FIFO Half Full interrupt Enable */
\r
5654 #define SDIO_MASK_TXFIFOFIE ((uint32_t)0x00010000) /*!<Tx FIFO Full interrupt Enable */
\r
5655 #define SDIO_MASK_RXFIFOFIE ((uint32_t)0x00020000) /*!<Rx FIFO Full interrupt Enable */
\r
5656 #define SDIO_MASK_TXFIFOEIE ((uint32_t)0x00040000) /*!<Tx FIFO Empty interrupt Enable */
\r
5657 #define SDIO_MASK_RXFIFOEIE ((uint32_t)0x00080000) /*!<Rx FIFO Empty interrupt Enable */
\r
5658 #define SDIO_MASK_TXDAVLIE ((uint32_t)0x00100000) /*!<Data available in Tx FIFO interrupt Enable */
\r
5659 #define SDIO_MASK_RXDAVLIE ((uint32_t)0x00200000) /*!<Data available in Rx FIFO interrupt Enable */
\r
5660 #define SDIO_MASK_SDIOITIE ((uint32_t)0x00400000) /*!<SDIO Mode Interrupt Received interrupt Enable */
\r
5661 #define SDIO_MASK_CEATAENDIE ((uint32_t)0x00800000) /*!<CE-ATA command completion signal received Interrupt Enable */
\r
5663 /***************** Bit definition for SDIO_FIFOCNT register *****************/
\r
5664 #define SDIO_FIFOCNT_FIFOCOUNT ((uint32_t)0x00FFFFFF) /*!<Remaining number of words to be written to or read from the FIFO */
\r
5666 /****************** Bit definition for SDIO_FIFO register *******************/
\r
5667 #define SDIO_FIFO_FIFODATA ((uint32_t)0xFFFFFFFF) /*!<Receive and transmit FIFO data */
\r
5669 /******************************************************************************/
\r
5671 /* Serial Peripheral Interface */
\r
5673 /******************************************************************************/
\r
5674 /******************* Bit definition for SPI_CR1 register ********************/
\r
5675 #define SPI_CR1_CPHA ((uint32_t)0x00000001) /*!<Clock Phase */
\r
5676 #define SPI_CR1_CPOL ((uint32_t)0x00000002) /*!<Clock Polarity */
\r
5677 #define SPI_CR1_MSTR ((uint32_t)0x00000004) /*!<Master Selection */
\r
5679 #define SPI_CR1_BR ((uint32_t)0x00000038) /*!<BR[2:0] bits (Baud Rate Control) */
\r
5680 #define SPI_CR1_BR_0 ((uint32_t)0x00000008) /*!<Bit 0 */
\r
5681 #define SPI_CR1_BR_1 ((uint32_t)0x00000010) /*!<Bit 1 */
\r
5682 #define SPI_CR1_BR_2 ((uint32_t)0x00000020) /*!<Bit 2 */
\r
5684 #define SPI_CR1_SPE ((uint32_t)0x00000040) /*!<SPI Enable */
\r
5685 #define SPI_CR1_LSBFIRST ((uint32_t)0x00000080) /*!<Frame Format */
\r
5686 #define SPI_CR1_SSI ((uint32_t)0x00000100) /*!<Internal slave select */
\r
5687 #define SPI_CR1_SSM ((uint32_t)0x00000200) /*!<Software slave management */
\r
5688 #define SPI_CR1_RXONLY ((uint32_t)0x00000400) /*!<Receive only */
\r
5689 #define SPI_CR1_DFF ((uint32_t)0x00000800) /*!<Data Frame Format */
\r
5690 #define SPI_CR1_CRCNEXT ((uint32_t)0x00001000) /*!<Transmit CRC next */
\r
5691 #define SPI_CR1_CRCEN ((uint32_t)0x00002000) /*!<Hardware CRC calculation enable */
\r
5692 #define SPI_CR1_BIDIOE ((uint32_t)0x00004000) /*!<Output enable in bidirectional mode */
\r
5693 #define SPI_CR1_BIDIMODE ((uint32_t)0x00008000) /*!<Bidirectional data mode enable */
\r
5695 /******************* Bit definition for SPI_CR2 register ********************/
\r
5696 #define SPI_CR2_RXDMAEN ((uint32_t)0x00000001) /*!<Rx Buffer DMA Enable */
\r
5697 #define SPI_CR2_TXDMAEN ((uint32_t)0x00000002) /*!<Tx Buffer DMA Enable */
\r
5698 #define SPI_CR2_SSOE ((uint32_t)0x00000004) /*!<SS Output Enable */
\r
5699 #define SPI_CR2_FRF ((uint32_t)0x00000010) /*!<Frame Format */
\r
5700 #define SPI_CR2_ERRIE ((uint32_t)0x00000020) /*!<Error Interrupt Enable */
\r
5701 #define SPI_CR2_RXNEIE ((uint32_t)0x00000040) /*!<RX buffer Not Empty Interrupt Enable */
\r
5702 #define SPI_CR2_TXEIE ((uint32_t)0x00000080) /*!<Tx buffer Empty Interrupt Enable */
\r
5704 /******************** Bit definition for SPI_SR register ********************/
\r
5705 #define SPI_SR_RXNE ((uint32_t)0x00000001) /*!<Receive buffer Not Empty */
\r
5706 #define SPI_SR_TXE ((uint32_t)0x00000002) /*!<Transmit buffer Empty */
\r
5707 #define SPI_SR_CHSIDE ((uint32_t)0x00000004) /*!<Channel side */
\r
5708 #define SPI_SR_UDR ((uint32_t)0x00000008) /*!<Underrun flag */
\r
5709 #define SPI_SR_CRCERR ((uint32_t)0x00000010) /*!<CRC Error flag */
\r
5710 #define SPI_SR_MODF ((uint32_t)0x00000020) /*!<Mode fault */
\r
5711 #define SPI_SR_OVR ((uint32_t)0x00000040) /*!<Overrun flag */
\r
5712 #define SPI_SR_BSY ((uint32_t)0x00000080) /*!<Busy flag */
\r
5713 #define SPI_SR_FRE ((uint32_t)0x00000100) /*!<Frame format error flag */
\r
5715 /******************** Bit definition for SPI_DR register ********************/
\r
5716 #define SPI_DR_DR ((uint32_t)0x0000FFFF) /*!<Data Register */
\r
5718 /******************* Bit definition for SPI_CRCPR register ******************/
\r
5719 #define SPI_CRCPR_CRCPOLY ((uint32_t)0x0000FFFF) /*!<CRC polynomial register */
\r
5721 /****************** Bit definition for SPI_RXCRCR register ******************/
\r
5722 #define SPI_RXCRCR_RXCRC ((uint32_t)0x0000FFFF) /*!<Rx CRC Register */
\r
5724 /****************** Bit definition for SPI_TXCRCR register ******************/
\r
5725 #define SPI_TXCRCR_TXCRC ((uint32_t)0x0000FFFF) /*!<Tx CRC Register */
\r
5727 /****************** Bit definition for SPI_I2SCFGR register *****************/
\r
5728 #define SPI_I2SCFGR_CHLEN ((uint32_t)0x00000001) /*!<Channel length (number of bits per audio channel) */
\r
5730 #define SPI_I2SCFGR_DATLEN ((uint32_t)0x00000006) /*!<DATLEN[1:0] bits (Data length to be transferred) */
\r
5731 #define SPI_I2SCFGR_DATLEN_0 ((uint32_t)0x00000002) /*!<Bit 0 */
\r
5732 #define SPI_I2SCFGR_DATLEN_1 ((uint32_t)0x00000004) /*!<Bit 1 */
\r
5734 #define SPI_I2SCFGR_CKPOL ((uint32_t)0x00000008) /*!<steady state clock polarity */
\r
5736 #define SPI_I2SCFGR_I2SSTD ((uint32_t)0x00000030) /*!<I2SSTD[1:0] bits (I2S standard selection) */
\r
5737 #define SPI_I2SCFGR_I2SSTD_0 ((uint32_t)0x00000010) /*!<Bit 0 */
\r
5738 #define SPI_I2SCFGR_I2SSTD_1 ((uint32_t)0x00000020) /*!<Bit 1 */
\r
5740 #define SPI_I2SCFGR_PCMSYNC ((uint32_t)0x00000080) /*!<PCM frame synchronization */
\r
5742 #define SPI_I2SCFGR_I2SCFG ((uint32_t)0x00000300) /*!<I2SCFG[1:0] bits (I2S configuration mode) */
\r
5743 #define SPI_I2SCFGR_I2SCFG_0 ((uint32_t)0x00000100) /*!<Bit 0 */
\r
5744 #define SPI_I2SCFGR_I2SCFG_1 ((uint32_t)0x00000200) /*!<Bit 1 */
\r
5746 #define SPI_I2SCFGR_I2SE ((uint32_t)0x00000400) /*!<I2S Enable */
\r
5747 #define SPI_I2SCFGR_I2SMOD ((uint32_t)0x00000800) /*!<I2S mode selection */
\r
5749 /****************** Bit definition for SPI_I2SPR register *******************/
\r
5750 #define SPI_I2SPR_I2SDIV ((uint32_t)0x000000FF) /*!<I2S Linear prescaler */
\r
5751 #define SPI_I2SPR_ODD ((uint32_t)0x00000100) /*!<Odd factor for the prescaler */
\r
5752 #define SPI_I2SPR_MCKOE ((uint32_t)0x00000200) /*!<Master Clock Output Enable */
\r
5754 /******************************************************************************/
\r
5758 /******************************************************************************/
\r
5759 /****************** Bit definition for SYSCFG_MEMRMP register ***************/
\r
5760 #define SYSCFG_MEMRMP_MEM_MODE ((uint32_t)0x00000007) /*!< SYSCFG_Memory Remap Config */
\r
5761 #define SYSCFG_MEMRMP_MEM_MODE_0 ((uint32_t)0x00000001)
\r
5762 #define SYSCFG_MEMRMP_MEM_MODE_1 ((uint32_t)0x00000002)
\r
5763 #define SYSCFG_MEMRMP_MEM_MODE_2 ((uint32_t)0x00000004)
\r
5765 /****************** Bit definition for SYSCFG_PMC register ******************/
\r
5766 #define SYSCFG_PMC_MII_RMII_SEL ((uint32_t)0x00800000) /*!<Ethernet PHY interface selection */
\r
5767 /* Old MII_RMII_SEL bit definition, maintained for legacy purpose */
\r
5768 #define SYSCFG_PMC_MII_RMII SYSCFG_PMC_MII_RMII_SEL
\r
5770 /***************** Bit definition for SYSCFG_EXTICR1 register ***************/
\r
5771 #define SYSCFG_EXTICR1_EXTI0 ((uint32_t)0x000F) /*!<EXTI 0 configuration */
\r
5772 #define SYSCFG_EXTICR1_EXTI1 ((uint32_t)0x00F0) /*!<EXTI 1 configuration */
\r
5773 #define SYSCFG_EXTICR1_EXTI2 ((uint32_t)0x0F00) /*!<EXTI 2 configuration */
\r
5774 #define SYSCFG_EXTICR1_EXTI3 ((uint32_t)0xF000) /*!<EXTI 3 configuration */
\r
5776 * @brief EXTI0 configuration
\r
5778 #define SYSCFG_EXTICR1_EXTI0_PA ((uint32_t)0x0000) /*!<PA[0] pin */
\r
5779 #define SYSCFG_EXTICR1_EXTI0_PB ((uint32_t)0x0001) /*!<PB[0] pin */
\r
5780 #define SYSCFG_EXTICR1_EXTI0_PC ((uint32_t)0x0002) /*!<PC[0] pin */
\r
5781 #define SYSCFG_EXTICR1_EXTI0_PD ((uint32_t)0x0003) /*!<PD[0] pin */
\r
5782 #define SYSCFG_EXTICR1_EXTI0_PE ((uint32_t)0x0004) /*!<PE[0] pin */
\r
5783 #define SYSCFG_EXTICR1_EXTI0_PF ((uint32_t)0x0005) /*!<PF[0] pin */
\r
5784 #define SYSCFG_EXTICR1_EXTI0_PG ((uint32_t)0x0006) /*!<PG[0] pin */
\r
5785 #define SYSCFG_EXTICR1_EXTI0_PH ((uint32_t)0x0007) /*!<PH[0] pin */
\r
5786 #define SYSCFG_EXTICR1_EXTI0_PI ((uint32_t)0x0008) /*!<PI[0] pin */
\r
5789 * @brief EXTI1 configuration
\r
5791 #define SYSCFG_EXTICR1_EXTI1_PA ((uint32_t)0x0000) /*!<PA[1] pin */
\r
5792 #define SYSCFG_EXTICR1_EXTI1_PB ((uint32_t)0x0010) /*!<PB[1] pin */
\r
5793 #define SYSCFG_EXTICR1_EXTI1_PC ((uint32_t)0x0020) /*!<PC[1] pin */
\r
5794 #define SYSCFG_EXTICR1_EXTI1_PD ((uint32_t)0x0030) /*!<PD[1] pin */
\r
5795 #define SYSCFG_EXTICR1_EXTI1_PE ((uint32_t)0x0040) /*!<PE[1] pin */
\r
5796 #define SYSCFG_EXTICR1_EXTI1_PF ((uint32_t)0x0050) /*!<PF[1] pin */
\r
5797 #define SYSCFG_EXTICR1_EXTI1_PG ((uint32_t)0x0060) /*!<PG[1] pin */
\r
5798 #define SYSCFG_EXTICR1_EXTI1_PH ((uint32_t)0x0070) /*!<PH[1] pin */
\r
5799 #define SYSCFG_EXTICR1_EXTI1_PI ((uint32_t)0x0080) /*!<PI[1] pin */
\r
5802 * @brief EXTI2 configuration
\r
5804 #define SYSCFG_EXTICR1_EXTI2_PA ((uint32_t)0x0000) /*!<PA[2] pin */
\r
5805 #define SYSCFG_EXTICR1_EXTI2_PB ((uint32_t)0x0100) /*!<PB[2] pin */
\r
5806 #define SYSCFG_EXTICR1_EXTI2_PC ((uint32_t)0x0200) /*!<PC[2] pin */
\r
5807 #define SYSCFG_EXTICR1_EXTI2_PD ((uint32_t)0x0300) /*!<PD[2] pin */
\r
5808 #define SYSCFG_EXTICR1_EXTI2_PE ((uint32_t)0x0400) /*!<PE[2] pin */
\r
5809 #define SYSCFG_EXTICR1_EXTI2_PF ((uint32_t)0x0500) /*!<PF[2] pin */
\r
5810 #define SYSCFG_EXTICR1_EXTI2_PG ((uint32_t)0x0600) /*!<PG[2] pin */
\r
5811 #define SYSCFG_EXTICR1_EXTI2_PH ((uint32_t)0x0700) /*!<PH[2] pin */
\r
5812 #define SYSCFG_EXTICR1_EXTI2_PI ((uint32_t)0x0800) /*!<PI[2] pin */
\r
5815 * @brief EXTI3 configuration
\r
5817 #define SYSCFG_EXTICR1_EXTI3_PA ((uint32_t)0x0000) /*!<PA[3] pin */
\r
5818 #define SYSCFG_EXTICR1_EXTI3_PB ((uint32_t)0x1000) /*!<PB[3] pin */
\r
5819 #define SYSCFG_EXTICR1_EXTI3_PC ((uint32_t)0x2000) /*!<PC[3] pin */
\r
5820 #define SYSCFG_EXTICR1_EXTI3_PD ((uint32_t)0x3000) /*!<PD[3] pin */
\r
5821 #define SYSCFG_EXTICR1_EXTI3_PE ((uint32_t)0x4000) /*!<PE[3] pin */
\r
5822 #define SYSCFG_EXTICR1_EXTI3_PF ((uint32_t)0x5000) /*!<PF[3] pin */
\r
5823 #define SYSCFG_EXTICR1_EXTI3_PG ((uint32_t)0x6000) /*!<PG[3] pin */
\r
5824 #define SYSCFG_EXTICR1_EXTI3_PH ((uint32_t)0x7000) /*!<PH[3] pin */
\r
5825 #define SYSCFG_EXTICR1_EXTI3_PI ((uint32_t)0x8000) /*!<PI[3] pin */
\r
5827 /***************** Bit definition for SYSCFG_EXTICR2 register ***************/
\r
5828 #define SYSCFG_EXTICR2_EXTI4 ((uint32_t)0x000F) /*!<EXTI 4 configuration */
\r
5829 #define SYSCFG_EXTICR2_EXTI5 ((uint32_t)0x00F0) /*!<EXTI 5 configuration */
\r
5830 #define SYSCFG_EXTICR2_EXTI6 ((uint32_t)0x0F00) /*!<EXTI 6 configuration */
\r
5831 #define SYSCFG_EXTICR2_EXTI7 ((uint32_t)0xF000) /*!<EXTI 7 configuration */
\r
5833 * @brief EXTI4 configuration
\r
5835 #define SYSCFG_EXTICR2_EXTI4_PA ((uint32_t)0x0000) /*!<PA[4] pin */
\r
5836 #define SYSCFG_EXTICR2_EXTI4_PB ((uint32_t)0x0001) /*!<PB[4] pin */
\r
5837 #define SYSCFG_EXTICR2_EXTI4_PC ((uint32_t)0x0002) /*!<PC[4] pin */
\r
5838 #define SYSCFG_EXTICR2_EXTI4_PD ((uint32_t)0x0003) /*!<PD[4] pin */
\r
5839 #define SYSCFG_EXTICR2_EXTI4_PE ((uint32_t)0x0004) /*!<PE[4] pin */
\r
5840 #define SYSCFG_EXTICR2_EXTI4_PF ((uint32_t)0x0005) /*!<PF[4] pin */
\r
5841 #define SYSCFG_EXTICR2_EXTI4_PG ((uint32_t)0x0006) /*!<PG[4] pin */
\r
5842 #define SYSCFG_EXTICR2_EXTI4_PH ((uint32_t)0x0007) /*!<PH[4] pin */
\r
5843 #define SYSCFG_EXTICR2_EXTI4_PI ((uint32_t)0x0008) /*!<PI[4] pin */
\r
5846 * @brief EXTI5 configuration
\r
5848 #define SYSCFG_EXTICR2_EXTI5_PA ((uint32_t)0x0000) /*!<PA[5] pin */
\r
5849 #define SYSCFG_EXTICR2_EXTI5_PB ((uint32_t)0x0010) /*!<PB[5] pin */
\r
5850 #define SYSCFG_EXTICR2_EXTI5_PC ((uint32_t)0x0020) /*!<PC[5] pin */
\r
5851 #define SYSCFG_EXTICR2_EXTI5_PD ((uint32_t)0x0030) /*!<PD[5] pin */
\r
5852 #define SYSCFG_EXTICR2_EXTI5_PE ((uint32_t)0x0040) /*!<PE[5] pin */
\r
5853 #define SYSCFG_EXTICR2_EXTI5_PF ((uint32_t)0x0050) /*!<PF[5] pin */
\r
5854 #define SYSCFG_EXTICR2_EXTI5_PG ((uint32_t)0x0060) /*!<PG[5] pin */
\r
5855 #define SYSCFG_EXTICR2_EXTI5_PH ((uint32_t)0x0070) /*!<PH[5] pin */
\r
5856 #define SYSCFG_EXTICR2_EXTI5_PI ((uint32_t)0x0080) /*!<PI[5] pin */
\r
5859 * @brief EXTI6 configuration
\r
5861 #define SYSCFG_EXTICR2_EXTI6_PA ((uint32_t)0x0000) /*!<PA[6] pin */
\r
5862 #define SYSCFG_EXTICR2_EXTI6_PB ((uint32_t)0x0100) /*!<PB[6] pin */
\r
5863 #define SYSCFG_EXTICR2_EXTI6_PC ((uint32_t)0x0200) /*!<PC[6] pin */
\r
5864 #define SYSCFG_EXTICR2_EXTI6_PD ((uint32_t)0x0300) /*!<PD[6] pin */
\r
5865 #define SYSCFG_EXTICR2_EXTI6_PE ((uint32_t)0x0400) /*!<PE[6] pin */
\r
5866 #define SYSCFG_EXTICR2_EXTI6_PF ((uint32_t)0x0500) /*!<PF[6] pin */
\r
5867 #define SYSCFG_EXTICR2_EXTI6_PG ((uint32_t)0x0600) /*!<PG[6] pin */
\r
5868 #define SYSCFG_EXTICR2_EXTI6_PH ((uint32_t)0x0700) /*!<PH[6] pin */
\r
5869 #define SYSCFG_EXTICR2_EXTI6_PI ((uint32_t)0x0800) /*!<PI[6] pin */
\r
5872 * @brief EXTI7 configuration
\r
5874 #define SYSCFG_EXTICR2_EXTI7_PA ((uint32_t)0x0000) /*!<PA[7] pin */
\r
5875 #define SYSCFG_EXTICR2_EXTI7_PB ((uint32_t)0x1000) /*!<PB[7] pin */
\r
5876 #define SYSCFG_EXTICR2_EXTI7_PC ((uint32_t)0x2000) /*!<PC[7] pin */
\r
5877 #define SYSCFG_EXTICR2_EXTI7_PD ((uint32_t)0x3000) /*!<PD[7] pin */
\r
5878 #define SYSCFG_EXTICR2_EXTI7_PE ((uint32_t)0x4000) /*!<PE[7] pin */
\r
5879 #define SYSCFG_EXTICR2_EXTI7_PF ((uint32_t)0x5000) /*!<PF[7] pin */
\r
5880 #define SYSCFG_EXTICR2_EXTI7_PG ((uint32_t)0x6000) /*!<PG[7] pin */
\r
5881 #define SYSCFG_EXTICR2_EXTI7_PH ((uint32_t)0x7000) /*!<PH[7] pin */
\r
5882 #define SYSCFG_EXTICR2_EXTI7_PI ((uint32_t)0x8000) /*!<PI[7] pin */
\r
5885 /***************** Bit definition for SYSCFG_EXTICR3 register ***************/
\r
5886 #define SYSCFG_EXTICR3_EXTI8 ((uint32_t)0x000F) /*!<EXTI 8 configuration */
\r
5887 #define SYSCFG_EXTICR3_EXTI9 ((uint32_t)0x00F0) /*!<EXTI 9 configuration */
\r
5888 #define SYSCFG_EXTICR3_EXTI10 ((uint32_t)0x0F00) /*!<EXTI 10 configuration */
\r
5889 #define SYSCFG_EXTICR3_EXTI11 ((uint32_t)0xF000) /*!<EXTI 11 configuration */
\r
5892 * @brief EXTI8 configuration
\r
5894 #define SYSCFG_EXTICR3_EXTI8_PA ((uint32_t)0x0000) /*!<PA[8] pin */
\r
5895 #define SYSCFG_EXTICR3_EXTI8_PB ((uint32_t)0x0001) /*!<PB[8] pin */
\r
5896 #define SYSCFG_EXTICR3_EXTI8_PC ((uint32_t)0x0002) /*!<PC[8] pin */
\r
5897 #define SYSCFG_EXTICR3_EXTI8_PD ((uint32_t)0x0003) /*!<PD[8] pin */
\r
5898 #define SYSCFG_EXTICR3_EXTI8_PE ((uint32_t)0x0004) /*!<PE[8] pin */
\r
5899 #define SYSCFG_EXTICR3_EXTI8_PF ((uint32_t)0x0005) /*!<PF[8] pin */
\r
5900 #define SYSCFG_EXTICR3_EXTI8_PG ((uint32_t)0x0006) /*!<PG[8] pin */
\r
5901 #define SYSCFG_EXTICR3_EXTI8_PH ((uint32_t)0x0007) /*!<PH[8] pin */
\r
5902 #define SYSCFG_EXTICR3_EXTI8_PI ((uint32_t)0x0008) /*!<PI[8] pin */
\r
5905 * @brief EXTI9 configuration
\r
5907 #define SYSCFG_EXTICR3_EXTI9_PA ((uint32_t)0x0000) /*!<PA[9] pin */
\r
5908 #define SYSCFG_EXTICR3_EXTI9_PB ((uint32_t)0x0010) /*!<PB[9] pin */
\r
5909 #define SYSCFG_EXTICR3_EXTI9_PC ((uint32_t)0x0020) /*!<PC[9] pin */
\r
5910 #define SYSCFG_EXTICR3_EXTI9_PD ((uint32_t)0x0030) /*!<PD[9] pin */
\r
5911 #define SYSCFG_EXTICR3_EXTI9_PE ((uint32_t)0x0040) /*!<PE[9] pin */
\r
5912 #define SYSCFG_EXTICR3_EXTI9_PF ((uint32_t)0x0050) /*!<PF[9] pin */
\r
5913 #define SYSCFG_EXTICR3_EXTI9_PG ((uint32_t)0x0060) /*!<PG[9] pin */
\r
5914 #define SYSCFG_EXTICR3_EXTI9_PH ((uint32_t)0x0070) /*!<PH[9] pin */
\r
5915 #define SYSCFG_EXTICR3_EXTI9_PI ((uint32_t)0x0080) /*!<PI[9] pin */
\r
5918 * @brief EXTI10 configuration
\r
5920 #define SYSCFG_EXTICR3_EXTI10_PA ((uint32_t)0x0000) /*!<PA[10] pin */
\r
5921 #define SYSCFG_EXTICR3_EXTI10_PB ((uint32_t)0x0100) /*!<PB[10] pin */
\r
5922 #define SYSCFG_EXTICR3_EXTI10_PC ((uint32_t)0x0200) /*!<PC[10] pin */
\r
5923 #define SYSCFG_EXTICR3_EXTI10_PD ((uint32_t)0x0300) /*!<PD[10] pin */
\r
5924 #define SYSCFG_EXTICR3_EXTI10_PE ((uint32_t)0x0400) /*!<PE[10] pin */
\r
5925 #define SYSCFG_EXTICR3_EXTI10_PF ((uint32_t)0x0500) /*!<PF[10] pin */
\r
5926 #define SYSCFG_EXTICR3_EXTI10_PG ((uint32_t)0x0600) /*!<PG[10] pin */
\r
5927 #define SYSCFG_EXTICR3_EXTI10_PH ((uint32_t)0x0700) /*!<PH[10] pin */
\r
5928 #define SYSCFG_EXTICR3_EXTI10_PI ((uint32_t)0x0800) /*!<PI[10] pin */
\r
5931 * @brief EXTI11 configuration
\r
5933 #define SYSCFG_EXTICR3_EXTI11_PA ((uint32_t)0x0000) /*!<PA[11] pin */
\r
5934 #define SYSCFG_EXTICR3_EXTI11_PB ((uint32_t)0x1000) /*!<PB[11] pin */
\r
5935 #define SYSCFG_EXTICR3_EXTI11_PC ((uint32_t)0x2000) /*!<PC[11] pin */
\r
5936 #define SYSCFG_EXTICR3_EXTI11_PD ((uint32_t)0x3000) /*!<PD[11] pin */
\r
5937 #define SYSCFG_EXTICR3_EXTI11_PE ((uint32_t)0x4000) /*!<PE[11] pin */
\r
5938 #define SYSCFG_EXTICR3_EXTI11_PF ((uint32_t)0x5000) /*!<PF[11] pin */
\r
5939 #define SYSCFG_EXTICR3_EXTI11_PG ((uint32_t)0x6000) /*!<PG[11] pin */
\r
5940 #define SYSCFG_EXTICR3_EXTI11_PH ((uint32_t)0x7000) /*!<PH[11] pin */
\r
5941 #define SYSCFG_EXTICR3_EXTI11_PI ((uint32_t)0x8000) /*!<PI[11] pin */
\r
5943 /***************** Bit definition for SYSCFG_EXTICR4 register ***************/
\r
5944 #define SYSCFG_EXTICR4_EXTI12 ((uint32_t)0x000F) /*!<EXTI 12 configuration */
\r
5945 #define SYSCFG_EXTICR4_EXTI13 ((uint32_t)0x00F0) /*!<EXTI 13 configuration */
\r
5946 #define SYSCFG_EXTICR4_EXTI14 ((uint32_t)0x0F00) /*!<EXTI 14 configuration */
\r
5947 #define SYSCFG_EXTICR4_EXTI15 ((uint32_t)0xF000) /*!<EXTI 15 configuration */
\r
5949 * @brief EXTI12 configuration
\r
5951 #define SYSCFG_EXTICR4_EXTI12_PA ((uint32_t)0x0000) /*!<PA[12] pin */
\r
5952 #define SYSCFG_EXTICR4_EXTI12_PB ((uint32_t)0x0001) /*!<PB[12] pin */
\r
5953 #define SYSCFG_EXTICR4_EXTI12_PC ((uint32_t)0x0002) /*!<PC[12] pin */
\r
5954 #define SYSCFG_EXTICR4_EXTI12_PD ((uint32_t)0x0003) /*!<PD[12] pin */
\r
5955 #define SYSCFG_EXTICR4_EXTI12_PE ((uint32_t)0x0004) /*!<PE[12] pin */
\r
5956 #define SYSCFG_EXTICR4_EXTI12_PF ((uint32_t)0x0005) /*!<PF[12] pin */
\r
5957 #define SYSCFG_EXTICR4_EXTI12_PG ((uint32_t)0x0006) /*!<PG[12] pin */
\r
5958 #define SYSCFG_EXTICR4_EXTI12_PH ((uint32_t)0x0007) /*!<PH[12] pin */
\r
5961 * @brief EXTI13 configuration
\r
5963 #define SYSCFG_EXTICR4_EXTI13_PA ((uint32_t)0x0000) /*!<PA[13] pin */
\r
5964 #define SYSCFG_EXTICR4_EXTI13_PB ((uint32_t)0x0010) /*!<PB[13] pin */
\r
5965 #define SYSCFG_EXTICR4_EXTI13_PC ((uint32_t)0x0020) /*!<PC[13] pin */
\r
5966 #define SYSCFG_EXTICR4_EXTI13_PD ((uint32_t)0x0030) /*!<PD[13] pin */
\r
5967 #define SYSCFG_EXTICR4_EXTI13_PE ((uint32_t)0x0040) /*!<PE[13] pin */
\r
5968 #define SYSCFG_EXTICR4_EXTI13_PF ((uint32_t)0x0050) /*!<PF[13] pin */
\r
5969 #define SYSCFG_EXTICR4_EXTI13_PG ((uint32_t)0x0060) /*!<PG[13] pin */
\r
5970 #define SYSCFG_EXTICR4_EXTI13_PH ((uint32_t)0x0070) /*!<PH[13] pin */
\r
5973 * @brief EXTI14 configuration
\r
5975 #define SYSCFG_EXTICR4_EXTI14_PA ((uint32_t)0x0000) /*!<PA[14] pin */
\r
5976 #define SYSCFG_EXTICR4_EXTI14_PB ((uint32_t)0x0100) /*!<PB[14] pin */
\r
5977 #define SYSCFG_EXTICR4_EXTI14_PC ((uint32_t)0x0200) /*!<PC[14] pin */
\r
5978 #define SYSCFG_EXTICR4_EXTI14_PD ((uint32_t)0x0300) /*!<PD[14] pin */
\r
5979 #define SYSCFG_EXTICR4_EXTI14_PE ((uint32_t)0x0400) /*!<PE[14] pin */
\r
5980 #define SYSCFG_EXTICR4_EXTI14_PF ((uint32_t)0x0500) /*!<PF[14] pin */
\r
5981 #define SYSCFG_EXTICR4_EXTI14_PG ((uint32_t)0x0600) /*!<PG[14] pin */
\r
5982 #define SYSCFG_EXTICR4_EXTI14_PH ((uint32_t)0x0700) /*!<PH[14] pin */
\r
5985 * @brief EXTI15 configuration
\r
5987 #define SYSCFG_EXTICR4_EXTI15_PA ((uint32_t)0x0000) /*!<PA[15] pin */
\r
5988 #define SYSCFG_EXTICR4_EXTI15_PB ((uint32_t)0x1000) /*!<PB[15] pin */
\r
5989 #define SYSCFG_EXTICR4_EXTI15_PC ((uint32_t)0x2000) /*!<PC[15] pin */
\r
5990 #define SYSCFG_EXTICR4_EXTI15_PD ((uint32_t)0x3000) /*!<PD[15] pin */
\r
5991 #define SYSCFG_EXTICR4_EXTI15_PE ((uint32_t)0x4000) /*!<PE[15] pin */
\r
5992 #define SYSCFG_EXTICR4_EXTI15_PF ((uint32_t)0x5000) /*!<PF[15] pin */
\r
5993 #define SYSCFG_EXTICR4_EXTI15_PG ((uint32_t)0x6000) /*!<PG[15] pin */
\r
5994 #define SYSCFG_EXTICR4_EXTI15_PH ((uint32_t)0x7000) /*!<PH[15] pin */
\r
5996 /****************** Bit definition for SYSCFG_CMPCR register ****************/
\r
5997 #define SYSCFG_CMPCR_CMP_PD ((uint32_t)0x00000001) /*!<Compensation cell ready flag */
\r
5998 #define SYSCFG_CMPCR_READY ((uint32_t)0x00000100) /*!<Compensation cell power-down */
\r
6000 /******************************************************************************/
\r
6004 /******************************************************************************/
\r
6005 /******************* Bit definition for TIM_CR1 register ********************/
\r
6006 #define TIM_CR1_CEN ((uint32_t)0x0001) /*!<Counter enable */
\r
6007 #define TIM_CR1_UDIS ((uint32_t)0x0002) /*!<Update disable */
\r
6008 #define TIM_CR1_URS ((uint32_t)0x0004) /*!<Update request source */
\r
6009 #define TIM_CR1_OPM ((uint32_t)0x0008) /*!<One pulse mode */
\r
6010 #define TIM_CR1_DIR ((uint32_t)0x0010) /*!<Direction */
\r
6012 #define TIM_CR1_CMS ((uint32_t)0x0060) /*!<CMS[1:0] bits (Center-aligned mode selection) */
\r
6013 #define TIM_CR1_CMS_0 ((uint32_t)0x0020) /*!<Bit 0 */
\r
6014 #define TIM_CR1_CMS_1 ((uint32_t)0x0040) /*!<Bit 1 */
\r
6016 #define TIM_CR1_ARPE ((uint32_t)0x0080) /*!<Auto-reload preload enable */
\r
6018 #define TIM_CR1_CKD ((uint32_t)0x0300) /*!<CKD[1:0] bits (clock division) */
\r
6019 #define TIM_CR1_CKD_0 ((uint32_t)0x0100) /*!<Bit 0 */
\r
6020 #define TIM_CR1_CKD_1 ((uint32_t)0x0200) /*!<Bit 1 */
\r
6022 /******************* Bit definition for TIM_CR2 register ********************/
\r
6023 #define TIM_CR2_CCPC ((uint32_t)0x0001) /*!<Capture/Compare Preloaded Control */
\r
6024 #define TIM_CR2_CCUS ((uint32_t)0x0004) /*!<Capture/Compare Control Update Selection */
\r
6025 #define TIM_CR2_CCDS ((uint32_t)0x0008) /*!<Capture/Compare DMA Selection */
\r
6027 #define TIM_CR2_MMS ((uint32_t)0x0070) /*!<MMS[2:0] bits (Master Mode Selection) */
\r
6028 #define TIM_CR2_MMS_0 ((uint32_t)0x0010) /*!<Bit 0 */
\r
6029 #define TIM_CR2_MMS_1 ((uint32_t)0x0020) /*!<Bit 1 */
\r
6030 #define TIM_CR2_MMS_2 ((uint32_t)0x0040) /*!<Bit 2 */
\r
6032 #define TIM_CR2_TI1S ((uint32_t)0x0080) /*!<TI1 Selection */
\r
6033 #define TIM_CR2_OIS1 ((uint32_t)0x0100) /*!<Output Idle state 1 (OC1 output) */
\r
6034 #define TIM_CR2_OIS1N ((uint32_t)0x0200) /*!<Output Idle state 1 (OC1N output) */
\r
6035 #define TIM_CR2_OIS2 ((uint32_t)0x0400) /*!<Output Idle state 2 (OC2 output) */
\r
6036 #define TIM_CR2_OIS2N ((uint32_t)0x0800) /*!<Output Idle state 2 (OC2N output) */
\r
6037 #define TIM_CR2_OIS3 ((uint32_t)0x1000) /*!<Output Idle state 3 (OC3 output) */
\r
6038 #define TIM_CR2_OIS3N ((uint32_t)0x2000) /*!<Output Idle state 3 (OC3N output) */
\r
6039 #define TIM_CR2_OIS4 ((uint32_t)0x4000) /*!<Output Idle state 4 (OC4 output) */
\r
6041 /******************* Bit definition for TIM_SMCR register *******************/
\r
6042 #define TIM_SMCR_SMS ((uint32_t)0x0007) /*!<SMS[2:0] bits (Slave mode selection) */
\r
6043 #define TIM_SMCR_SMS_0 ((uint32_t)0x0001) /*!<Bit 0 */
\r
6044 #define TIM_SMCR_SMS_1 ((uint32_t)0x0002) /*!<Bit 1 */
\r
6045 #define TIM_SMCR_SMS_2 ((uint32_t)0x0004) /*!<Bit 2 */
\r
6047 #define TIM_SMCR_TS ((uint32_t)0x0070) /*!<TS[2:0] bits (Trigger selection) */
\r
6048 #define TIM_SMCR_TS_0 ((uint32_t)0x0010) /*!<Bit 0 */
\r
6049 #define TIM_SMCR_TS_1 ((uint32_t)0x0020) /*!<Bit 1 */
\r
6050 #define TIM_SMCR_TS_2 ((uint32_t)0x0040) /*!<Bit 2 */
\r
6052 #define TIM_SMCR_MSM ((uint32_t)0x0080) /*!<Master/slave mode */
\r
6054 #define TIM_SMCR_ETF ((uint32_t)0x0F00) /*!<ETF[3:0] bits (External trigger filter) */
\r
6055 #define TIM_SMCR_ETF_0 ((uint32_t)0x0100) /*!<Bit 0 */
\r
6056 #define TIM_SMCR_ETF_1 ((uint32_t)0x0200) /*!<Bit 1 */
\r
6057 #define TIM_SMCR_ETF_2 ((uint32_t)0x0400) /*!<Bit 2 */
\r
6058 #define TIM_SMCR_ETF_3 ((uint32_t)0x0800) /*!<Bit 3 */
\r
6060 #define TIM_SMCR_ETPS ((uint32_t)0x3000) /*!<ETPS[1:0] bits (External trigger prescaler) */
\r
6061 #define TIM_SMCR_ETPS_0 ((uint32_t)0x1000) /*!<Bit 0 */
\r
6062 #define TIM_SMCR_ETPS_1 ((uint32_t)0x2000) /*!<Bit 1 */
\r
6064 #define TIM_SMCR_ECE ((uint32_t)0x4000) /*!<External clock enable */
\r
6065 #define TIM_SMCR_ETP ((uint32_t)0x8000) /*!<External trigger polarity */
\r
6067 /******************* Bit definition for TIM_DIER register *******************/
\r
6068 #define TIM_DIER_UIE ((uint32_t)0x0001) /*!<Update interrupt enable */
\r
6069 #define TIM_DIER_CC1IE ((uint32_t)0x0002) /*!<Capture/Compare 1 interrupt enable */
\r
6070 #define TIM_DIER_CC2IE ((uint32_t)0x0004) /*!<Capture/Compare 2 interrupt enable */
\r
6071 #define TIM_DIER_CC3IE ((uint32_t)0x0008) /*!<Capture/Compare 3 interrupt enable */
\r
6072 #define TIM_DIER_CC4IE ((uint32_t)0x0010) /*!<Capture/Compare 4 interrupt enable */
\r
6073 #define TIM_DIER_COMIE ((uint32_t)0x0020) /*!<COM interrupt enable */
\r
6074 #define TIM_DIER_TIE ((uint32_t)0x0040) /*!<Trigger interrupt enable */
\r
6075 #define TIM_DIER_BIE ((uint32_t)0x0080) /*!<Break interrupt enable */
\r
6076 #define TIM_DIER_UDE ((uint32_t)0x0100) /*!<Update DMA request enable */
\r
6077 #define TIM_DIER_CC1DE ((uint32_t)0x0200) /*!<Capture/Compare 1 DMA request enable */
\r
6078 #define TIM_DIER_CC2DE ((uint32_t)0x0400) /*!<Capture/Compare 2 DMA request enable */
\r
6079 #define TIM_DIER_CC3DE ((uint32_t)0x0800) /*!<Capture/Compare 3 DMA request enable */
\r
6080 #define TIM_DIER_CC4DE ((uint32_t)0x1000) /*!<Capture/Compare 4 DMA request enable */
\r
6081 #define TIM_DIER_COMDE ((uint32_t)0x2000) /*!<COM DMA request enable */
\r
6082 #define TIM_DIER_TDE ((uint32_t)0x4000) /*!<Trigger DMA request enable */
\r
6084 /******************** Bit definition for TIM_SR register ********************/
\r
6085 #define TIM_SR_UIF ((uint32_t)0x0001) /*!<Update interrupt Flag */
\r
6086 #define TIM_SR_CC1IF ((uint32_t)0x0002) /*!<Capture/Compare 1 interrupt Flag */
\r
6087 #define TIM_SR_CC2IF ((uint32_t)0x0004) /*!<Capture/Compare 2 interrupt Flag */
\r
6088 #define TIM_SR_CC3IF ((uint32_t)0x0008) /*!<Capture/Compare 3 interrupt Flag */
\r
6089 #define TIM_SR_CC4IF ((uint32_t)0x0010) /*!<Capture/Compare 4 interrupt Flag */
\r
6090 #define TIM_SR_COMIF ((uint32_t)0x0020) /*!<COM interrupt Flag */
\r
6091 #define TIM_SR_TIF ((uint32_t)0x0040) /*!<Trigger interrupt Flag */
\r
6092 #define TIM_SR_BIF ((uint32_t)0x0080) /*!<Break interrupt Flag */
\r
6093 #define TIM_SR_CC1OF ((uint32_t)0x0200) /*!<Capture/Compare 1 Overcapture Flag */
\r
6094 #define TIM_SR_CC2OF ((uint32_t)0x0400) /*!<Capture/Compare 2 Overcapture Flag */
\r
6095 #define TIM_SR_CC3OF ((uint32_t)0x0800) /*!<Capture/Compare 3 Overcapture Flag */
\r
6096 #define TIM_SR_CC4OF ((uint32_t)0x1000) /*!<Capture/Compare 4 Overcapture Flag */
\r
6098 /******************* Bit definition for TIM_EGR register ********************/
\r
6099 #define TIM_EGR_UG ((uint32_t)0x01) /*!<Update Generation */
\r
6100 #define TIM_EGR_CC1G ((uint32_t)0x02) /*!<Capture/Compare 1 Generation */
\r
6101 #define TIM_EGR_CC2G ((uint32_t)0x04) /*!<Capture/Compare 2 Generation */
\r
6102 #define TIM_EGR_CC3G ((uint32_t)0x08) /*!<Capture/Compare 3 Generation */
\r
6103 #define TIM_EGR_CC4G ((uint32_t)0x10) /*!<Capture/Compare 4 Generation */
\r
6104 #define TIM_EGR_COMG ((uint32_t)0x20) /*!<Capture/Compare Control Update Generation */
\r
6105 #define TIM_EGR_TG ((uint32_t)0x40) /*!<Trigger Generation */
\r
6106 #define TIM_EGR_BG ((uint32_t)0x80) /*!<Break Generation */
\r
6108 /****************** Bit definition for TIM_CCMR1 register *******************/
\r
6109 #define TIM_CCMR1_CC1S ((uint32_t)0x0003) /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
\r
6110 #define TIM_CCMR1_CC1S_0 ((uint32_t)0x0001) /*!<Bit 0 */
\r
6111 #define TIM_CCMR1_CC1S_1 ((uint32_t)0x0002) /*!<Bit 1 */
\r
6113 #define TIM_CCMR1_OC1FE ((uint32_t)0x0004) /*!<Output Compare 1 Fast enable */
\r
6114 #define TIM_CCMR1_OC1PE ((uint32_t)0x0008) /*!<Output Compare 1 Preload enable */
\r
6116 #define TIM_CCMR1_OC1M ((uint32_t)0x0070) /*!<OC1M[2:0] bits (Output Compare 1 Mode) */
\r
6117 #define TIM_CCMR1_OC1M_0 ((uint32_t)0x0010) /*!<Bit 0 */
\r
6118 #define TIM_CCMR1_OC1M_1 ((uint32_t)0x0020) /*!<Bit 1 */
\r
6119 #define TIM_CCMR1_OC1M_2 ((uint32_t)0x0040) /*!<Bit 2 */
\r
6121 #define TIM_CCMR1_OC1CE ((uint32_t)0x0080) /*!<Output Compare 1Clear Enable */
\r
6123 #define TIM_CCMR1_CC2S ((uint32_t)0x0300) /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
\r
6124 #define TIM_CCMR1_CC2S_0 ((uint32_t)0x0100) /*!<Bit 0 */
\r
6125 #define TIM_CCMR1_CC2S_1 ((uint32_t)0x0200) /*!<Bit 1 */
\r
6127 #define TIM_CCMR1_OC2FE ((uint32_t)0x0400) /*!<Output Compare 2 Fast enable */
\r
6128 #define TIM_CCMR1_OC2PE ((uint32_t)0x0800) /*!<Output Compare 2 Preload enable */
\r
6130 #define TIM_CCMR1_OC2M ((uint32_t)0x7000) /*!<OC2M[2:0] bits (Output Compare 2 Mode) */
\r
6131 #define TIM_CCMR1_OC2M_0 ((uint32_t)0x1000) /*!<Bit 0 */
\r
6132 #define TIM_CCMR1_OC2M_1 ((uint32_t)0x2000) /*!<Bit 1 */
\r
6133 #define TIM_CCMR1_OC2M_2 ((uint32_t)0x4000) /*!<Bit 2 */
\r
6135 #define TIM_CCMR1_OC2CE ((uint32_t)0x8000) /*!<Output Compare 2 Clear Enable */
\r
6137 /*----------------------------------------------------------------------------*/
\r
6139 #define TIM_CCMR1_IC1PSC ((uint32_t)0x000C) /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
\r
6140 #define TIM_CCMR1_IC1PSC_0 ((uint32_t)0x0004) /*!<Bit 0 */
\r
6141 #define TIM_CCMR1_IC1PSC_1 ((uint32_t)0x0008) /*!<Bit 1 */
\r
6143 #define TIM_CCMR1_IC1F ((uint32_t)0x00F0) /*!<IC1F[3:0] bits (Input Capture 1 Filter) */
\r
6144 #define TIM_CCMR1_IC1F_0 ((uint32_t)0x0010) /*!<Bit 0 */
\r
6145 #define TIM_CCMR1_IC1F_1 ((uint32_t)0x0020) /*!<Bit 1 */
\r
6146 #define TIM_CCMR1_IC1F_2 ((uint32_t)0x0040) /*!<Bit 2 */
\r
6147 #define TIM_CCMR1_IC1F_3 ((uint32_t)0x0080) /*!<Bit 3 */
\r
6149 #define TIM_CCMR1_IC2PSC ((uint32_t)0x0C00) /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */
\r
6150 #define TIM_CCMR1_IC2PSC_0 ((uint32_t)0x0400) /*!<Bit 0 */
\r
6151 #define TIM_CCMR1_IC2PSC_1 ((uint32_t)0x0800) /*!<Bit 1 */
\r
6153 #define TIM_CCMR1_IC2F ((uint32_t)0xF000) /*!<IC2F[3:0] bits (Input Capture 2 Filter) */
\r
6154 #define TIM_CCMR1_IC2F_0 ((uint32_t)0x1000) /*!<Bit 0 */
\r
6155 #define TIM_CCMR1_IC2F_1 ((uint32_t)0x2000) /*!<Bit 1 */
\r
6156 #define TIM_CCMR1_IC2F_2 ((uint32_t)0x4000) /*!<Bit 2 */
\r
6157 #define TIM_CCMR1_IC2F_3 ((uint32_t)0x8000) /*!<Bit 3 */
\r
6159 /****************** Bit definition for TIM_CCMR2 register *******************/
\r
6160 #define TIM_CCMR2_CC3S ((uint32_t)0x0003) /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */
\r
6161 #define TIM_CCMR2_CC3S_0 ((uint32_t)0x0001) /*!<Bit 0 */
\r
6162 #define TIM_CCMR2_CC3S_1 ((uint32_t)0x0002) /*!<Bit 1 */
\r
6164 #define TIM_CCMR2_OC3FE ((uint32_t)0x0004) /*!<Output Compare 3 Fast enable */
\r
6165 #define TIM_CCMR2_OC3PE ((uint32_t)0x0008) /*!<Output Compare 3 Preload enable */
\r
6167 #define TIM_CCMR2_OC3M ((uint32_t)0x0070) /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
\r
6168 #define TIM_CCMR2_OC3M_0 ((uint32_t)0x0010) /*!<Bit 0 */
\r
6169 #define TIM_CCMR2_OC3M_1 ((uint32_t)0x0020) /*!<Bit 1 */
\r
6170 #define TIM_CCMR2_OC3M_2 ((uint32_t)0x0040) /*!<Bit 2 */
\r
6172 #define TIM_CCMR2_OC3CE ((uint32_t)0x0080) /*!<Output Compare 3 Clear Enable */
\r
6174 #define TIM_CCMR2_CC4S ((uint32_t)0x0300) /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
\r
6175 #define TIM_CCMR2_CC4S_0 ((uint32_t)0x0100) /*!<Bit 0 */
\r
6176 #define TIM_CCMR2_CC4S_1 ((uint32_t)0x0200) /*!<Bit 1 */
\r
6178 #define TIM_CCMR2_OC4FE ((uint32_t)0x0400) /*!<Output Compare 4 Fast enable */
\r
6179 #define TIM_CCMR2_OC4PE ((uint32_t)0x0800) /*!<Output Compare 4 Preload enable */
\r
6181 #define TIM_CCMR2_OC4M ((uint32_t)0x7000) /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
\r
6182 #define TIM_CCMR2_OC4M_0 ((uint32_t)0x1000) /*!<Bit 0 */
\r
6183 #define TIM_CCMR2_OC4M_1 ((uint32_t)0x2000) /*!<Bit 1 */
\r
6184 #define TIM_CCMR2_OC4M_2 ((uint32_t)0x4000) /*!<Bit 2 */
\r
6186 #define TIM_CCMR2_OC4CE ((uint32_t)0x8000) /*!<Output Compare 4 Clear Enable */
\r
6188 /*----------------------------------------------------------------------------*/
\r
6190 #define TIM_CCMR2_IC3PSC ((uint32_t)0x000C) /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
\r
6191 #define TIM_CCMR2_IC3PSC_0 ((uint32_t)0x0004) /*!<Bit 0 */
\r
6192 #define TIM_CCMR2_IC3PSC_1 ((uint32_t)0x0008) /*!<Bit 1 */
\r
6194 #define TIM_CCMR2_IC3F ((uint32_t)0x00F0) /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
\r
6195 #define TIM_CCMR2_IC3F_0 ((uint32_t)0x0010) /*!<Bit 0 */
\r
6196 #define TIM_CCMR2_IC3F_1 ((uint32_t)0x0020) /*!<Bit 1 */
\r
6197 #define TIM_CCMR2_IC3F_2 ((uint32_t)0x0040) /*!<Bit 2 */
\r
6198 #define TIM_CCMR2_IC3F_3 ((uint32_t)0x0080) /*!<Bit 3 */
\r
6200 #define TIM_CCMR2_IC4PSC ((uint32_t)0x0C00) /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
\r
6201 #define TIM_CCMR2_IC4PSC_0 ((uint32_t)0x0400) /*!<Bit 0 */
\r
6202 #define TIM_CCMR2_IC4PSC_1 ((uint32_t)0x0800) /*!<Bit 1 */
\r
6204 #define TIM_CCMR2_IC4F ((uint32_t)0xF000) /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
\r
6205 #define TIM_CCMR2_IC4F_0 ((uint32_t)0x1000) /*!<Bit 0 */
\r
6206 #define TIM_CCMR2_IC4F_1 ((uint32_t)0x2000) /*!<Bit 1 */
\r
6207 #define TIM_CCMR2_IC4F_2 ((uint32_t)0x4000) /*!<Bit 2 */
\r
6208 #define TIM_CCMR2_IC4F_3 ((uint32_t)0x8000) /*!<Bit 3 */
\r
6210 /******************* Bit definition for TIM_CCER register *******************/
\r
6211 #define TIM_CCER_CC1E ((uint32_t)0x0001) /*!<Capture/Compare 1 output enable */
\r
6212 #define TIM_CCER_CC1P ((uint32_t)0x0002) /*!<Capture/Compare 1 output Polarity */
\r
6213 #define TIM_CCER_CC1NE ((uint32_t)0x0004) /*!<Capture/Compare 1 Complementary output enable */
\r
6214 #define TIM_CCER_CC1NP ((uint32_t)0x0008) /*!<Capture/Compare 1 Complementary output Polarity */
\r
6215 #define TIM_CCER_CC2E ((uint32_t)0x0010) /*!<Capture/Compare 2 output enable */
\r
6216 #define TIM_CCER_CC2P ((uint32_t)0x0020) /*!<Capture/Compare 2 output Polarity */
\r
6217 #define TIM_CCER_CC2NE ((uint32_t)0x0040) /*!<Capture/Compare 2 Complementary output enable */
\r
6218 #define TIM_CCER_CC2NP ((uint32_t)0x0080) /*!<Capture/Compare 2 Complementary output Polarity */
\r
6219 #define TIM_CCER_CC3E ((uint32_t)0x0100) /*!<Capture/Compare 3 output enable */
\r
6220 #define TIM_CCER_CC3P ((uint32_t)0x0200) /*!<Capture/Compare 3 output Polarity */
\r
6221 #define TIM_CCER_CC3NE ((uint32_t)0x0400) /*!<Capture/Compare 3 Complementary output enable */
\r
6222 #define TIM_CCER_CC3NP ((uint32_t)0x0800) /*!<Capture/Compare 3 Complementary output Polarity */
\r
6223 #define TIM_CCER_CC4E ((uint32_t)0x1000) /*!<Capture/Compare 4 output enable */
\r
6224 #define TIM_CCER_CC4P ((uint32_t)0x2000) /*!<Capture/Compare 4 output Polarity */
\r
6225 #define TIM_CCER_CC4NP ((uint32_t)0x8000) /*!<Capture/Compare 4 Complementary output Polarity */
\r
6227 /******************* Bit definition for TIM_CNT register ********************/
\r
6228 #define TIM_CNT_CNT ((uint32_t)0xFFFF) /*!<Counter Value */
\r
6230 /******************* Bit definition for TIM_PSC register ********************/
\r
6231 #define TIM_PSC_PSC ((uint32_t)0xFFFF) /*!<Prescaler Value */
\r
6233 /******************* Bit definition for TIM_ARR register ********************/
\r
6234 #define TIM_ARR_ARR ((uint32_t)0xFFFF) /*!<actual auto-reload Value */
\r
6236 /******************* Bit definition for TIM_RCR register ********************/
\r
6237 #define TIM_RCR_REP ((uint32_t)0xFF) /*!<Repetition Counter Value */
\r
6239 /******************* Bit definition for TIM_CCR1 register *******************/
\r
6240 #define TIM_CCR1_CCR1 ((uint32_t)0xFFFF) /*!<Capture/Compare 1 Value */
\r
6242 /******************* Bit definition for TIM_CCR2 register *******************/
\r
6243 #define TIM_CCR2_CCR2 ((uint32_t)0xFFFF) /*!<Capture/Compare 2 Value */
\r
6245 /******************* Bit definition for TIM_CCR3 register *******************/
\r
6246 #define TIM_CCR3_CCR3 ((uint32_t)0xFFFF) /*!<Capture/Compare 3 Value */
\r
6248 /******************* Bit definition for TIM_CCR4 register *******************/
\r
6249 #define TIM_CCR4_CCR4 ((uint32_t)0xFFFF) /*!<Capture/Compare 4 Value */
\r
6251 /******************* Bit definition for TIM_BDTR register *******************/
\r
6252 #define TIM_BDTR_DTG ((uint32_t)0x00FF) /*!<DTG[0:7] bits (Dead-Time Generator set-up) */
\r
6253 #define TIM_BDTR_DTG_0 ((uint32_t)0x0001) /*!<Bit 0 */
\r
6254 #define TIM_BDTR_DTG_1 ((uint32_t)0x0002) /*!<Bit 1 */
\r
6255 #define TIM_BDTR_DTG_2 ((uint32_t)0x0004) /*!<Bit 2 */
\r
6256 #define TIM_BDTR_DTG_3 ((uint32_t)0x0008) /*!<Bit 3 */
\r
6257 #define TIM_BDTR_DTG_4 ((uint32_t)0x0010) /*!<Bit 4 */
\r
6258 #define TIM_BDTR_DTG_5 ((uint32_t)0x0020) /*!<Bit 5 */
\r
6259 #define TIM_BDTR_DTG_6 ((uint32_t)0x0040) /*!<Bit 6 */
\r
6260 #define TIM_BDTR_DTG_7 ((uint32_t)0x0080) /*!<Bit 7 */
\r
6262 #define TIM_BDTR_LOCK ((uint32_t)0x0300) /*!<LOCK[1:0] bits (Lock Configuration) */
\r
6263 #define TIM_BDTR_LOCK_0 ((uint32_t)0x0100) /*!<Bit 0 */
\r
6264 #define TIM_BDTR_LOCK_1 ((uint32_t)0x0200) /*!<Bit 1 */
\r
6266 #define TIM_BDTR_OSSI ((uint32_t)0x0400) /*!<Off-State Selection for Idle mode */
\r
6267 #define TIM_BDTR_OSSR ((uint32_t)0x0800) /*!<Off-State Selection for Run mode */
\r
6268 #define TIM_BDTR_BKE ((uint32_t)0x1000) /*!<Break enable */
\r
6269 #define TIM_BDTR_BKP ((uint32_t)0x2000) /*!<Break Polarity */
\r
6270 #define TIM_BDTR_AOE ((uint32_t)0x4000) /*!<Automatic Output enable */
\r
6271 #define TIM_BDTR_MOE ((uint32_t)0x8000) /*!<Main Output enable */
\r
6273 /******************* Bit definition for TIM_DCR register ********************/
\r
6274 #define TIM_DCR_DBA ((uint32_t)0x001F) /*!<DBA[4:0] bits (DMA Base Address) */
\r
6275 #define TIM_DCR_DBA_0 ((uint32_t)0x0001) /*!<Bit 0 */
\r
6276 #define TIM_DCR_DBA_1 ((uint32_t)0x0002) /*!<Bit 1 */
\r
6277 #define TIM_DCR_DBA_2 ((uint32_t)0x0004) /*!<Bit 2 */
\r
6278 #define TIM_DCR_DBA_3 ((uint32_t)0x0008) /*!<Bit 3 */
\r
6279 #define TIM_DCR_DBA_4 ((uint32_t)0x0010) /*!<Bit 4 */
\r
6281 #define TIM_DCR_DBL ((uint32_t)0x1F00) /*!<DBL[4:0] bits (DMA Burst Length) */
\r
6282 #define TIM_DCR_DBL_0 ((uint32_t)0x0100) /*!<Bit 0 */
\r
6283 #define TIM_DCR_DBL_1 ((uint32_t)0x0200) /*!<Bit 1 */
\r
6284 #define TIM_DCR_DBL_2 ((uint32_t)0x0400) /*!<Bit 2 */
\r
6285 #define TIM_DCR_DBL_3 ((uint32_t)0x0800) /*!<Bit 3 */
\r
6286 #define TIM_DCR_DBL_4 ((uint32_t)0x1000) /*!<Bit 4 */
\r
6288 /******************* Bit definition for TIM_DMAR register *******************/
\r
6289 #define TIM_DMAR_DMAB ((uint32_t)0xFFFF) /*!<DMA register for burst accesses */
\r
6291 /******************* Bit definition for TIM_OR register *********************/
\r
6292 #define TIM_OR_TI4_RMP ((uint32_t)0x00C0) /*!<TI4_RMP[1:0] bits (TIM5 Input 4 remap) */
\r
6293 #define TIM_OR_TI4_RMP_0 ((uint32_t)0x0040) /*!<Bit 0 */
\r
6294 #define TIM_OR_TI4_RMP_1 ((uint32_t)0x0080) /*!<Bit 1 */
\r
6295 #define TIM_OR_ITR1_RMP ((uint32_t)0x0C00) /*!<ITR1_RMP[1:0] bits (TIM2 Internal trigger 1 remap) */
\r
6296 #define TIM_OR_ITR1_RMP_0 ((uint32_t)0x0400) /*!<Bit 0 */
\r
6297 #define TIM_OR_ITR1_RMP_1 ((uint32_t)0x0800) /*!<Bit 1 */
\r
6300 /******************************************************************************/
\r
6302 /* Universal Synchronous Asynchronous Receiver Transmitter */
\r
6304 /******************************************************************************/
\r
6305 /******************* Bit definition for USART_SR register *******************/
\r
6306 #define USART_SR_PE ((uint32_t)0x0001) /*!<Parity Error */
\r
6307 #define USART_SR_FE ((uint32_t)0x0002) /*!<Framing Error */
\r
6308 #define USART_SR_NE ((uint32_t)0x0004) /*!<Noise Error Flag */
\r
6309 #define USART_SR_ORE ((uint32_t)0x0008) /*!<OverRun Error */
\r
6310 #define USART_SR_IDLE ((uint32_t)0x0010) /*!<IDLE line detected */
\r
6311 #define USART_SR_RXNE ((uint32_t)0x0020) /*!<Read Data Register Not Empty */
\r
6312 #define USART_SR_TC ((uint32_t)0x0040) /*!<Transmission Complete */
\r
6313 #define USART_SR_TXE ((uint32_t)0x0080) /*!<Transmit Data Register Empty */
\r
6314 #define USART_SR_LBD ((uint32_t)0x0100) /*!<LIN Break Detection Flag */
\r
6315 #define USART_SR_CTS ((uint32_t)0x0200) /*!<CTS Flag */
\r
6317 /******************* Bit definition for USART_DR register *******************/
\r
6318 #define USART_DR_DR ((uint32_t)0x01FF) /*!<Data value */
\r
6320 /****************** Bit definition for USART_BRR register *******************/
\r
6321 #define USART_BRR_DIV_Fraction ((uint32_t)0x000F) /*!<Fraction of USARTDIV */
\r
6322 #define USART_BRR_DIV_Mantissa ((uint32_t)0xFFF0) /*!<Mantissa of USARTDIV */
\r
6324 /****************** Bit definition for USART_CR1 register *******************/
\r
6325 #define USART_CR1_SBK ((uint32_t)0x0001) /*!<Send Break */
\r
6326 #define USART_CR1_RWU ((uint32_t)0x0002) /*!<Receiver wakeup */
\r
6327 #define USART_CR1_RE ((uint32_t)0x0004) /*!<Receiver Enable */
\r
6328 #define USART_CR1_TE ((uint32_t)0x0008) /*!<Transmitter Enable */
\r
6329 #define USART_CR1_IDLEIE ((uint32_t)0x0010) /*!<IDLE Interrupt Enable */
\r
6330 #define USART_CR1_RXNEIE ((uint32_t)0x0020) /*!<RXNE Interrupt Enable */
\r
6331 #define USART_CR1_TCIE ((uint32_t)0x0040) /*!<Transmission Complete Interrupt Enable */
\r
6332 #define USART_CR1_TXEIE ((uint32_t)0x0080) /*!<PE Interrupt Enable */
\r
6333 #define USART_CR1_PEIE ((uint32_t)0x0100) /*!<PE Interrupt Enable */
\r
6334 #define USART_CR1_PS ((uint32_t)0x0200) /*!<Parity Selection */
\r
6335 #define USART_CR1_PCE ((uint32_t)0x0400) /*!<Parity Control Enable */
\r
6336 #define USART_CR1_WAKE ((uint32_t)0x0800) /*!<Wakeup method */
\r
6337 #define USART_CR1_M ((uint32_t)0x1000) /*!<Word length */
\r
6338 #define USART_CR1_UE ((uint32_t)0x2000) /*!<USART Enable */
\r
6339 #define USART_CR1_OVER8 ((uint32_t)0x8000) /*!<USART Oversampling by 8 enable */
\r
6341 /****************** Bit definition for USART_CR2 register *******************/
\r
6342 #define USART_CR2_ADD ((uint32_t)0x000F) /*!<Address of the USART node */
\r
6343 #define USART_CR2_LBDL ((uint32_t)0x0020) /*!<LIN Break Detection Length */
\r
6344 #define USART_CR2_LBDIE ((uint32_t)0x0040) /*!<LIN Break Detection Interrupt Enable */
\r
6345 #define USART_CR2_LBCL ((uint32_t)0x0100) /*!<Last Bit Clock pulse */
\r
6346 #define USART_CR2_CPHA ((uint32_t)0x0200) /*!<Clock Phase */
\r
6347 #define USART_CR2_CPOL ((uint32_t)0x0400) /*!<Clock Polarity */
\r
6348 #define USART_CR2_CLKEN ((uint32_t)0x0800) /*!<Clock Enable */
\r
6350 #define USART_CR2_STOP ((uint32_t)0x3000) /*!<STOP[1:0] bits (STOP bits) */
\r
6351 #define USART_CR2_STOP_0 ((uint32_t)0x1000) /*!<Bit 0 */
\r
6352 #define USART_CR2_STOP_1 ((uint32_t)0x2000) /*!<Bit 1 */
\r
6354 #define USART_CR2_LINEN ((uint32_t)0x4000) /*!<LIN mode enable */
\r
6356 /****************** Bit definition for USART_CR3 register *******************/
\r
6357 #define USART_CR3_EIE ((uint32_t)0x0001) /*!<Error Interrupt Enable */
\r
6358 #define USART_CR3_IREN ((uint32_t)0x0002) /*!<IrDA mode Enable */
\r
6359 #define USART_CR3_IRLP ((uint32_t)0x0004) /*!<IrDA Low-Power */
\r
6360 #define USART_CR3_HDSEL ((uint32_t)0x0008) /*!<Half-Duplex Selection */
\r
6361 #define USART_CR3_NACK ((uint32_t)0x0010) /*!<Smartcard NACK enable */
\r
6362 #define USART_CR3_SCEN ((uint32_t)0x0020) /*!<Smartcard mode enable */
\r
6363 #define USART_CR3_DMAR ((uint32_t)0x0040) /*!<DMA Enable Receiver */
\r
6364 #define USART_CR3_DMAT ((uint32_t)0x0080) /*!<DMA Enable Transmitter */
\r
6365 #define USART_CR3_RTSE ((uint32_t)0x0100) /*!<RTS Enable */
\r
6366 #define USART_CR3_CTSE ((uint32_t)0x0200) /*!<CTS Enable */
\r
6367 #define USART_CR3_CTSIE ((uint32_t)0x0400) /*!<CTS Interrupt Enable */
\r
6368 #define USART_CR3_ONEBIT ((uint32_t)0x0800) /*!<USART One bit method enable */
\r
6370 /****************** Bit definition for USART_GTPR register ******************/
\r
6371 #define USART_GTPR_PSC ((uint32_t)0x00FF) /*!<PSC[7:0] bits (Prescaler value) */
\r
6372 #define USART_GTPR_PSC_0 ((uint32_t)0x0001) /*!<Bit 0 */
\r
6373 #define USART_GTPR_PSC_1 ((uint32_t)0x0002) /*!<Bit 1 */
\r
6374 #define USART_GTPR_PSC_2 ((uint32_t)0x0004) /*!<Bit 2 */
\r
6375 #define USART_GTPR_PSC_3 ((uint32_t)0x0008) /*!<Bit 3 */
\r
6376 #define USART_GTPR_PSC_4 ((uint32_t)0x0010) /*!<Bit 4 */
\r
6377 #define USART_GTPR_PSC_5 ((uint32_t)0x0020) /*!<Bit 5 */
\r
6378 #define USART_GTPR_PSC_6 ((uint32_t)0x0040) /*!<Bit 6 */
\r
6379 #define USART_GTPR_PSC_7 ((uint32_t)0x0080) /*!<Bit 7 */
\r
6381 #define USART_GTPR_GT ((uint32_t)0xFF00) /*!<Guard time value */
\r
6383 /******************************************************************************/
\r
6385 /* Window WATCHDOG */
\r
6387 /******************************************************************************/
\r
6388 /******************* Bit definition for WWDG_CR register ********************/
\r
6389 #define WWDG_CR_T ((uint32_t)0x7F) /*!<T[6:0] bits (7-Bit counter (MSB to LSB)) */
\r
6390 #define WWDG_CR_T0 ((uint32_t)0x01) /*!<Bit 0 */
\r
6391 #define WWDG_CR_T1 ((uint32_t)0x02) /*!<Bit 1 */
\r
6392 #define WWDG_CR_T2 ((uint32_t)0x04) /*!<Bit 2 */
\r
6393 #define WWDG_CR_T3 ((uint32_t)0x08) /*!<Bit 3 */
\r
6394 #define WWDG_CR_T4 ((uint32_t)0x10) /*!<Bit 4 */
\r
6395 #define WWDG_CR_T5 ((uint32_t)0x20) /*!<Bit 5 */
\r
6396 #define WWDG_CR_T6 ((uint32_t)0x40) /*!<Bit 6 */
\r
6398 #define WWDG_CR_WDGA ((uint32_t)0x80) /*!<Activation bit */
\r
6400 /******************* Bit definition for WWDG_CFR register *******************/
\r
6401 #define WWDG_CFR_W ((uint32_t)0x007F) /*!<W[6:0] bits (7-bit window value) */
\r
6402 #define WWDG_CFR_W0 ((uint32_t)0x0001) /*!<Bit 0 */
\r
6403 #define WWDG_CFR_W1 ((uint32_t)0x0002) /*!<Bit 1 */
\r
6404 #define WWDG_CFR_W2 ((uint32_t)0x0004) /*!<Bit 2 */
\r
6405 #define WWDG_CFR_W3 ((uint32_t)0x0008) /*!<Bit 3 */
\r
6406 #define WWDG_CFR_W4 ((uint32_t)0x0010) /*!<Bit 4 */
\r
6407 #define WWDG_CFR_W5 ((uint32_t)0x0020) /*!<Bit 5 */
\r
6408 #define WWDG_CFR_W6 ((uint32_t)0x0040) /*!<Bit 6 */
\r
6410 #define WWDG_CFR_WDGTB ((uint32_t)0x0180) /*!<WDGTB[1:0] bits (Timer Base) */
\r
6411 #define WWDG_CFR_WDGTB0 ((uint32_t)0x0080) /*!<Bit 0 */
\r
6412 #define WWDG_CFR_WDGTB1 ((uint32_t)0x0100) /*!<Bit 1 */
\r
6414 #define WWDG_CFR_EWI ((uint32_t)0x0200) /*!<Early Wakeup Interrupt */
\r
6416 /******************* Bit definition for WWDG_SR register ********************/
\r
6417 #define WWDG_SR_EWIF ((uint32_t)0x01) /*!<Early Wakeup Interrupt Flag */
\r
6420 /******************************************************************************/
\r
6424 /******************************************************************************/
\r
6425 /******************** Bit definition for DBGMCU_IDCODE register *************/
\r
6426 #define DBGMCU_IDCODE_DEV_ID ((uint32_t)0x00000FFF)
\r
6427 #define DBGMCU_IDCODE_REV_ID ((uint32_t)0xFFFF0000)
\r
6429 /******************** Bit definition for DBGMCU_CR register *****************/
\r
6430 #define DBGMCU_CR_DBG_SLEEP ((uint32_t)0x00000001)
\r
6431 #define DBGMCU_CR_DBG_STOP ((uint32_t)0x00000002)
\r
6432 #define DBGMCU_CR_DBG_STANDBY ((uint32_t)0x00000004)
\r
6433 #define DBGMCU_CR_TRACE_IOEN ((uint32_t)0x00000020)
\r
6435 #define DBGMCU_CR_TRACE_MODE ((uint32_t)0x000000C0)
\r
6436 #define DBGMCU_CR_TRACE_MODE_0 ((uint32_t)0x00000040)/*!<Bit 0 */
\r
6437 #define DBGMCU_CR_TRACE_MODE_1 ((uint32_t)0x00000080)/*!<Bit 1 */
\r
6439 /******************** Bit definition for DBGMCU_APB1_FZ register ************/
\r
6440 #define DBGMCU_APB1_FZ_DBG_TIM2_STOP ((uint32_t)0x00000001)
\r
6441 #define DBGMCU_APB1_FZ_DBG_TIM3_STOP ((uint32_t)0x00000002)
\r
6442 #define DBGMCU_APB1_FZ_DBG_TIM4_STOP ((uint32_t)0x00000004)
\r
6443 #define DBGMCU_APB1_FZ_DBG_TIM5_STOP ((uint32_t)0x00000008)
\r
6444 #define DBGMCU_APB1_FZ_DBG_TIM6_STOP ((uint32_t)0x00000010)
\r
6445 #define DBGMCU_APB1_FZ_DBG_TIM7_STOP ((uint32_t)0x00000020)
\r
6446 #define DBGMCU_APB1_FZ_DBG_TIM12_STOP ((uint32_t)0x00000040)
\r
6447 #define DBGMCU_APB1_FZ_DBG_TIM13_STOP ((uint32_t)0x00000080)
\r
6448 #define DBGMCU_APB1_FZ_DBG_TIM14_STOP ((uint32_t)0x00000100)
\r
6449 #define DBGMCU_APB1_FZ_DBG_RTC_STOP ((uint32_t)0x00000400)
\r
6450 #define DBGMCU_APB1_FZ_DBG_WWDG_STOP ((uint32_t)0x00000800)
\r
6451 #define DBGMCU_APB1_FZ_DBG_IWDG_STOP ((uint32_t)0x00001000)
\r
6452 #define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT ((uint32_t)0x00200000)
\r
6453 #define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT ((uint32_t)0x00400000)
\r
6454 #define DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT ((uint32_t)0x00800000)
\r
6455 #define DBGMCU_APB1_FZ_DBG_CAN1_STOP ((uint32_t)0x02000000)
\r
6456 #define DBGMCU_APB1_FZ_DBG_CAN2_STOP ((uint32_t)0x04000000)
\r
6457 /* Old IWDGSTOP bit definition, maintained for legacy purpose */
\r
6458 #define DBGMCU_APB1_FZ_DBG_IWDEG_STOP DBGMCU_APB1_FZ_DBG_IWDG_STOP
\r
6460 /******************** Bit definition for DBGMCU_APB2_FZ register ************/
\r
6461 #define DBGMCU_APB2_FZ_DBG_TIM1_STOP ((uint32_t)0x00000001)
\r
6462 #define DBGMCU_APB2_FZ_DBG_TIM8_STOP ((uint32_t)0x00000002)
\r
6463 #define DBGMCU_APB2_FZ_DBG_TIM9_STOP ((uint32_t)0x00010000)
\r
6464 #define DBGMCU_APB2_FZ_DBG_TIM10_STOP ((uint32_t)0x00020000)
\r
6465 #define DBGMCU_APB2_FZ_DBG_TIM11_STOP ((uint32_t)0x00040000)
\r
6467 /******************************************************************************/
\r
6469 /* Ethernet MAC Registers bits definitions */
\r
6471 /******************************************************************************/
\r
6472 /* Bit definition for Ethernet MAC Control Register register */
\r
6473 #define ETH_MACCR_WD ((uint32_t)0x00800000) /* Watchdog disable */
\r
6474 #define ETH_MACCR_JD ((uint32_t)0x00400000) /* Jabber disable */
\r
6475 #define ETH_MACCR_IFG ((uint32_t)0x000E0000) /* Inter-frame gap */
\r
6476 #define ETH_MACCR_IFG_96Bit ((uint32_t)0x00000000) /* Minimum IFG between frames during transmission is 96Bit */
\r
6477 #define ETH_MACCR_IFG_88Bit ((uint32_t)0x00020000) /* Minimum IFG between frames during transmission is 88Bit */
\r
6478 #define ETH_MACCR_IFG_80Bit ((uint32_t)0x00040000) /* Minimum IFG between frames during transmission is 80Bit */
\r
6479 #define ETH_MACCR_IFG_72Bit ((uint32_t)0x00060000) /* Minimum IFG between frames during transmission is 72Bit */
\r
6480 #define ETH_MACCR_IFG_64Bit ((uint32_t)0x00080000) /* Minimum IFG between frames during transmission is 64Bit */
\r
6481 #define ETH_MACCR_IFG_56Bit ((uint32_t)0x000A0000) /* Minimum IFG between frames during transmission is 56Bit */
\r
6482 #define ETH_MACCR_IFG_48Bit ((uint32_t)0x000C0000) /* Minimum IFG between frames during transmission is 48Bit */
\r
6483 #define ETH_MACCR_IFG_40Bit ((uint32_t)0x000E0000) /* Minimum IFG between frames during transmission is 40Bit */
\r
6484 #define ETH_MACCR_CSD ((uint32_t)0x00010000) /* Carrier sense disable (during transmission) */
\r
6485 #define ETH_MACCR_FES ((uint32_t)0x00004000) /* Fast ethernet speed */
\r
6486 #define ETH_MACCR_ROD ((uint32_t)0x00002000) /* Receive own disable */
\r
6487 #define ETH_MACCR_LM ((uint32_t)0x00001000) /* loopback mode */
\r
6488 #define ETH_MACCR_DM ((uint32_t)0x00000800) /* Duplex mode */
\r
6489 #define ETH_MACCR_IPCO ((uint32_t)0x00000400) /* IP Checksum offload */
\r
6490 #define ETH_MACCR_RD ((uint32_t)0x00000200) /* Retry disable */
\r
6491 #define ETH_MACCR_APCS ((uint32_t)0x00000080) /* Automatic Pad/CRC stripping */
\r
6492 #define ETH_MACCR_BL ((uint32_t)0x00000060) /* Back-off limit: random integer number (r) of slot time delays before rescheduling
\r
6493 a transmission attempt during retries after a collision: 0 =< r <2^k */
\r
6494 #define ETH_MACCR_BL_10 ((uint32_t)0x00000000) /* k = min (n, 10) */
\r
6495 #define ETH_MACCR_BL_8 ((uint32_t)0x00000020) /* k = min (n, 8) */
\r
6496 #define ETH_MACCR_BL_4 ((uint32_t)0x00000040) /* k = min (n, 4) */
\r
6497 #define ETH_MACCR_BL_1 ((uint32_t)0x00000060) /* k = min (n, 1) */
\r
6498 #define ETH_MACCR_DC ((uint32_t)0x00000010) /* Defferal check */
\r
6499 #define ETH_MACCR_TE ((uint32_t)0x00000008) /* Transmitter enable */
\r
6500 #define ETH_MACCR_RE ((uint32_t)0x00000004) /* Receiver enable */
\r
6502 /* Bit definition for Ethernet MAC Frame Filter Register */
\r
6503 #define ETH_MACFFR_RA ((uint32_t)0x80000000) /* Receive all */
\r
6504 #define ETH_MACFFR_HPF ((uint32_t)0x00000400) /* Hash or perfect filter */
\r
6505 #define ETH_MACFFR_SAF ((uint32_t)0x00000200) /* Source address filter enable */
\r
6506 #define ETH_MACFFR_SAIF ((uint32_t)0x00000100) /* SA inverse filtering */
\r
6507 #define ETH_MACFFR_PCF ((uint32_t)0x000000C0) /* Pass control frames: 3 cases */
\r
6508 #define ETH_MACFFR_PCF_BlockAll ((uint32_t)0x00000040) /* MAC filters all control frames from reaching the application */
\r
6509 #define ETH_MACFFR_PCF_ForwardAll ((uint32_t)0x00000080) /* MAC forwards all control frames to application even if they fail the Address Filter */
\r
6510 #define ETH_MACFFR_PCF_ForwardPassedAddrFilter ((uint32_t)0x000000C0) /* MAC forwards control frames that pass the Address Filter. */
\r
6511 #define ETH_MACFFR_BFD ((uint32_t)0x00000020) /* Broadcast frame disable */
\r
6512 #define ETH_MACFFR_PAM ((uint32_t)0x00000010) /* Pass all mutlicast */
\r
6513 #define ETH_MACFFR_DAIF ((uint32_t)0x00000008) /* DA Inverse filtering */
\r
6514 #define ETH_MACFFR_HM ((uint32_t)0x00000004) /* Hash multicast */
\r
6515 #define ETH_MACFFR_HU ((uint32_t)0x00000002) /* Hash unicast */
\r
6516 #define ETH_MACFFR_PM ((uint32_t)0x00000001) /* Promiscuous mode */
\r
6518 /* Bit definition for Ethernet MAC Hash Table High Register */
\r
6519 #define ETH_MACHTHR_HTH ((uint32_t)0xFFFFFFFF) /* Hash table high */
\r
6521 /* Bit definition for Ethernet MAC Hash Table Low Register */
\r
6522 #define ETH_MACHTLR_HTL ((uint32_t)0xFFFFFFFF) /* Hash table low */
\r
6524 /* Bit definition for Ethernet MAC MII Address Register */
\r
6525 #define ETH_MACMIIAR_PA ((uint32_t)0x0000F800) /* Physical layer address */
\r
6526 #define ETH_MACMIIAR_MR ((uint32_t)0x000007C0) /* MII register in the selected PHY */
\r
6527 #define ETH_MACMIIAR_CR ((uint32_t)0x0000001C) /* CR clock range: 6 cases */
\r
6528 #define ETH_MACMIIAR_CR_Div42 ((uint32_t)0x00000000) /* HCLK:60-100 MHz; MDC clock= HCLK/42 */
\r
6529 #define ETH_MACMIIAR_CR_Div62 ((uint32_t)0x00000004) /* HCLK:100-150 MHz; MDC clock= HCLK/62 */
\r
6530 #define ETH_MACMIIAR_CR_Div16 ((uint32_t)0x00000008) /* HCLK:20-35 MHz; MDC clock= HCLK/16 */
\r
6531 #define ETH_MACMIIAR_CR_Div26 ((uint32_t)0x0000000C) /* HCLK:35-60 MHz; MDC clock= HCLK/26 */
\r
6532 #define ETH_MACMIIAR_CR_Div102 ((uint32_t)0x00000010) /* HCLK:150-168 MHz; MDC clock= HCLK/102 */
\r
6533 #define ETH_MACMIIAR_MW ((uint32_t)0x00000002) /* MII write */
\r
6534 #define ETH_MACMIIAR_MB ((uint32_t)0x00000001) /* MII busy */
\r
6536 /* Bit definition for Ethernet MAC MII Data Register */
\r
6537 #define ETH_MACMIIDR_MD ((uint32_t)0x0000FFFF) /* MII data: read/write data from/to PHY */
\r
6539 /* Bit definition for Ethernet MAC Flow Control Register */
\r
6540 #define ETH_MACFCR_PT ((uint32_t)0xFFFF0000) /* Pause time */
\r
6541 #define ETH_MACFCR_ZQPD ((uint32_t)0x00000080) /* Zero-quanta pause disable */
\r
6542 #define ETH_MACFCR_PLT ((uint32_t)0x00000030) /* Pause low threshold: 4 cases */
\r
6543 #define ETH_MACFCR_PLT_Minus4 ((uint32_t)0x00000000) /* Pause time minus 4 slot times */
\r
6544 #define ETH_MACFCR_PLT_Minus28 ((uint32_t)0x00000010) /* Pause time minus 28 slot times */
\r
6545 #define ETH_MACFCR_PLT_Minus144 ((uint32_t)0x00000020) /* Pause time minus 144 slot times */
\r
6546 #define ETH_MACFCR_PLT_Minus256 ((uint32_t)0x00000030) /* Pause time minus 256 slot times */
\r
6547 #define ETH_MACFCR_UPFD ((uint32_t)0x00000008) /* Unicast pause frame detect */
\r
6548 #define ETH_MACFCR_RFCE ((uint32_t)0x00000004) /* Receive flow control enable */
\r
6549 #define ETH_MACFCR_TFCE ((uint32_t)0x00000002) /* Transmit flow control enable */
\r
6550 #define ETH_MACFCR_FCBBPA ((uint32_t)0x00000001) /* Flow control busy/backpressure activate */
\r
6552 /* Bit definition for Ethernet MAC VLAN Tag Register */
\r
6553 #define ETH_MACVLANTR_VLANTC ((uint32_t)0x00010000) /* 12-bit VLAN tag comparison */
\r
6554 #define ETH_MACVLANTR_VLANTI ((uint32_t)0x0000FFFF) /* VLAN tag identifier (for receive frames) */
\r
6556 /* Bit definition for Ethernet MAC Remote Wake-UpFrame Filter Register */
\r
6557 #define ETH_MACRWUFFR_D ((uint32_t)0xFFFFFFFF) /* Wake-up frame filter register data */
\r
6558 /* Eight sequential Writes to this address (offset 0x28) will write all Wake-UpFrame Filter Registers.
\r
6559 Eight sequential Reads from this address (offset 0x28) will read all Wake-UpFrame Filter Registers. */
\r
6560 /* Wake-UpFrame Filter Reg0 : Filter 0 Byte Mask
\r
6561 Wake-UpFrame Filter Reg1 : Filter 1 Byte Mask
\r
6562 Wake-UpFrame Filter Reg2 : Filter 2 Byte Mask
\r
6563 Wake-UpFrame Filter Reg3 : Filter 3 Byte Mask
\r
6564 Wake-UpFrame Filter Reg4 : RSVD - Filter3 Command - RSVD - Filter2 Command -
\r
6565 RSVD - Filter1 Command - RSVD - Filter0 Command
\r
6566 Wake-UpFrame Filter Re5 : Filter3 Offset - Filter2 Offset - Filter1 Offset - Filter0 Offset
\r
6567 Wake-UpFrame Filter Re6 : Filter1 CRC16 - Filter0 CRC16
\r
6568 Wake-UpFrame Filter Re7 : Filter3 CRC16 - Filter2 CRC16 */
\r
6570 /* Bit definition for Ethernet MAC PMT Control and Status Register */
\r
6571 #define ETH_MACPMTCSR_WFFRPR ((uint32_t)0x80000000) /* Wake-Up Frame Filter Register Pointer Reset */
\r
6572 #define ETH_MACPMTCSR_GU ((uint32_t)0x00000200) /* Global Unicast */
\r
6573 #define ETH_MACPMTCSR_WFR ((uint32_t)0x00000040) /* Wake-Up Frame Received */
\r
6574 #define ETH_MACPMTCSR_MPR ((uint32_t)0x00000020) /* Magic Packet Received */
\r
6575 #define ETH_MACPMTCSR_WFE ((uint32_t)0x00000004) /* Wake-Up Frame Enable */
\r
6576 #define ETH_MACPMTCSR_MPE ((uint32_t)0x00000002) /* Magic Packet Enable */
\r
6577 #define ETH_MACPMTCSR_PD ((uint32_t)0x00000001) /* Power Down */
\r
6579 /* Bit definition for Ethernet MAC Status Register */
\r
6580 #define ETH_MACSR_TSTS ((uint32_t)0x00000200) /* Time stamp trigger status */
\r
6581 #define ETH_MACSR_MMCTS ((uint32_t)0x00000040) /* MMC transmit status */
\r
6582 #define ETH_MACSR_MMMCRS ((uint32_t)0x00000020) /* MMC receive status */
\r
6583 #define ETH_MACSR_MMCS ((uint32_t)0x00000010) /* MMC status */
\r
6584 #define ETH_MACSR_PMTS ((uint32_t)0x00000008) /* PMT status */
\r
6586 /* Bit definition for Ethernet MAC Interrupt Mask Register */
\r
6587 #define ETH_MACIMR_TSTIM ((uint32_t)0x00000200) /* Time stamp trigger interrupt mask */
\r
6588 #define ETH_MACIMR_PMTIM ((uint32_t)0x00000008) /* PMT interrupt mask */
\r
6590 /* Bit definition for Ethernet MAC Address0 High Register */
\r
6591 #define ETH_MACA0HR_MACA0H ((uint32_t)0x0000FFFF) /* MAC address0 high */
\r
6593 /* Bit definition for Ethernet MAC Address0 Low Register */
\r
6594 #define ETH_MACA0LR_MACA0L ((uint32_t)0xFFFFFFFF) /* MAC address0 low */
\r
6596 /* Bit definition for Ethernet MAC Address1 High Register */
\r
6597 #define ETH_MACA1HR_AE ((uint32_t)0x80000000) /* Address enable */
\r
6598 #define ETH_MACA1HR_SA ((uint32_t)0x40000000) /* Source address */
\r
6599 #define ETH_MACA1HR_MBC ((uint32_t)0x3F000000) /* Mask byte control: bits to mask for comparison of the MAC Address bytes */
\r
6600 #define ETH_MACA1HR_MBC_HBits15_8 ((uint32_t)0x20000000) /* Mask MAC Address high reg bits [15:8] */
\r
6601 #define ETH_MACA1HR_MBC_HBits7_0 ((uint32_t)0x10000000) /* Mask MAC Address high reg bits [7:0] */
\r
6602 #define ETH_MACA1HR_MBC_LBits31_24 ((uint32_t)0x08000000) /* Mask MAC Address low reg bits [31:24] */
\r
6603 #define ETH_MACA1HR_MBC_LBits23_16 ((uint32_t)0x04000000) /* Mask MAC Address low reg bits [23:16] */
\r
6604 #define ETH_MACA1HR_MBC_LBits15_8 ((uint32_t)0x02000000) /* Mask MAC Address low reg bits [15:8] */
\r
6605 #define ETH_MACA1HR_MBC_LBits7_0 ((uint32_t)0x01000000) /* Mask MAC Address low reg bits [7:0] */
\r
6606 #define ETH_MACA1HR_MACA1H ((uint32_t)0x0000FFFF) /* MAC address1 high */
\r
6608 /* Bit definition for Ethernet MAC Address1 Low Register */
\r
6609 #define ETH_MACA1LR_MACA1L ((uint32_t)0xFFFFFFFF) /* MAC address1 low */
\r
6611 /* Bit definition for Ethernet MAC Address2 High Register */
\r
6612 #define ETH_MACA2HR_AE ((uint32_t)0x80000000) /* Address enable */
\r
6613 #define ETH_MACA2HR_SA ((uint32_t)0x40000000) /* Source address */
\r
6614 #define ETH_MACA2HR_MBC ((uint32_t)0x3F000000) /* Mask byte control */
\r
6615 #define ETH_MACA2HR_MBC_HBits15_8 ((uint32_t)0x20000000) /* Mask MAC Address high reg bits [15:8] */
\r
6616 #define ETH_MACA2HR_MBC_HBits7_0 ((uint32_t)0x10000000) /* Mask MAC Address high reg bits [7:0] */
\r
6617 #define ETH_MACA2HR_MBC_LBits31_24 ((uint32_t)0x08000000) /* Mask MAC Address low reg bits [31:24] */
\r
6618 #define ETH_MACA2HR_MBC_LBits23_16 ((uint32_t)0x04000000) /* Mask MAC Address low reg bits [23:16] */
\r
6619 #define ETH_MACA2HR_MBC_LBits15_8 ((uint32_t)0x02000000) /* Mask MAC Address low reg bits [15:8] */
\r
6620 #define ETH_MACA2HR_MBC_LBits7_0 ((uint32_t)0x01000000) /* Mask MAC Address low reg bits [70] */
\r
6621 #define ETH_MACA2HR_MACA2H ((uint32_t)0x0000FFFF) /* MAC address1 high */
\r
6623 /* Bit definition for Ethernet MAC Address2 Low Register */
\r
6624 #define ETH_MACA2LR_MACA2L ((uint32_t)0xFFFFFFFF) /* MAC address2 low */
\r
6626 /* Bit definition for Ethernet MAC Address3 High Register */
\r
6627 #define ETH_MACA3HR_AE ((uint32_t)0x80000000) /* Address enable */
\r
6628 #define ETH_MACA3HR_SA ((uint32_t)0x40000000) /* Source address */
\r
6629 #define ETH_MACA3HR_MBC ((uint32_t)0x3F000000) /* Mask byte control */
\r
6630 #define ETH_MACA3HR_MBC_HBits15_8 ((uint32_t)0x20000000) /* Mask MAC Address high reg bits [15:8] */
\r
6631 #define ETH_MACA3HR_MBC_HBits7_0 ((uint32_t)0x10000000) /* Mask MAC Address high reg bits [7:0] */
\r
6632 #define ETH_MACA3HR_MBC_LBits31_24 ((uint32_t)0x08000000) /* Mask MAC Address low reg bits [31:24] */
\r
6633 #define ETH_MACA3HR_MBC_LBits23_16 ((uint32_t)0x04000000) /* Mask MAC Address low reg bits [23:16] */
\r
6634 #define ETH_MACA3HR_MBC_LBits15_8 ((uint32_t)0x02000000) /* Mask MAC Address low reg bits [15:8] */
\r
6635 #define ETH_MACA3HR_MBC_LBits7_0 ((uint32_t)0x01000000) /* Mask MAC Address low reg bits [70] */
\r
6636 #define ETH_MACA3HR_MACA3H ((uint32_t)0x0000FFFF) /* MAC address3 high */
\r
6638 /* Bit definition for Ethernet MAC Address3 Low Register */
\r
6639 #define ETH_MACA3LR_MACA3L ((uint32_t)0xFFFFFFFF) /* MAC address3 low */
\r
6641 /******************************************************************************/
\r
6642 /* Ethernet MMC Registers bits definition */
\r
6643 /******************************************************************************/
\r
6645 /* Bit definition for Ethernet MMC Contol Register */
\r
6646 #define ETH_MMCCR_MCFHP ((uint32_t)0x00000020) /* MMC counter Full-Half preset */
\r
6647 #define ETH_MMCCR_MCP ((uint32_t)0x00000010) /* MMC counter preset */
\r
6648 #define ETH_MMCCR_MCF ((uint32_t)0x00000008) /* MMC Counter Freeze */
\r
6649 #define ETH_MMCCR_ROR ((uint32_t)0x00000004) /* Reset on Read */
\r
6650 #define ETH_MMCCR_CSR ((uint32_t)0x00000002) /* Counter Stop Rollover */
\r
6651 #define ETH_MMCCR_CR ((uint32_t)0x00000001) /* Counters Reset */
\r
6653 /* Bit definition for Ethernet MMC Receive Interrupt Register */
\r
6654 #define ETH_MMCRIR_RGUFS ((uint32_t)0x00020000) /* Set when Rx good unicast frames counter reaches half the maximum value */
\r
6655 #define ETH_MMCRIR_RFAES ((uint32_t)0x00000040) /* Set when Rx alignment error counter reaches half the maximum value */
\r
6656 #define ETH_MMCRIR_RFCES ((uint32_t)0x00000020) /* Set when Rx crc error counter reaches half the maximum value */
\r
6658 /* Bit definition for Ethernet MMC Transmit Interrupt Register */
\r
6659 #define ETH_MMCTIR_TGFS ((uint32_t)0x00200000) /* Set when Tx good frame count counter reaches half the maximum value */
\r
6660 #define ETH_MMCTIR_TGFMSCS ((uint32_t)0x00008000) /* Set when Tx good multi col counter reaches half the maximum value */
\r
6661 #define ETH_MMCTIR_TGFSCS ((uint32_t)0x00004000) /* Set when Tx good single col counter reaches half the maximum value */
\r
6663 /* Bit definition for Ethernet MMC Receive Interrupt Mask Register */
\r
6664 #define ETH_MMCRIMR_RGUFM ((uint32_t)0x00020000) /* Mask the interrupt when Rx good unicast frames counter reaches half the maximum value */
\r
6665 #define ETH_MMCRIMR_RFAEM ((uint32_t)0x00000040) /* Mask the interrupt when when Rx alignment error counter reaches half the maximum value */
\r
6666 #define ETH_MMCRIMR_RFCEM ((uint32_t)0x00000020) /* Mask the interrupt when Rx crc error counter reaches half the maximum value */
\r
6668 /* Bit definition for Ethernet MMC Transmit Interrupt Mask Register */
\r
6669 #define ETH_MMCTIMR_TGFM ((uint32_t)0x00200000) /* Mask the interrupt when Tx good frame count counter reaches half the maximum value */
\r
6670 #define ETH_MMCTIMR_TGFMSCM ((uint32_t)0x00008000) /* Mask the interrupt when Tx good multi col counter reaches half the maximum value */
\r
6671 #define ETH_MMCTIMR_TGFSCM ((uint32_t)0x00004000) /* Mask the interrupt when Tx good single col counter reaches half the maximum value */
\r
6673 /* Bit definition for Ethernet MMC Transmitted Good Frames after Single Collision Counter Register */
\r
6674 #define ETH_MMCTGFSCCR_TGFSCC ((uint32_t)0xFFFFFFFF) /* Number of successfully transmitted frames after a single collision in Half-duplex mode. */
\r
6676 /* Bit definition for Ethernet MMC Transmitted Good Frames after More than a Single Collision Counter Register */
\r
6677 #define ETH_MMCTGFMSCCR_TGFMSCC ((uint32_t)0xFFFFFFFF) /* Number of successfully transmitted frames after more than a single collision in Half-duplex mode. */
\r
6679 /* Bit definition for Ethernet MMC Transmitted Good Frames Counter Register */
\r
6680 #define ETH_MMCTGFCR_TGFC ((uint32_t)0xFFFFFFFF) /* Number of good frames transmitted. */
\r
6682 /* Bit definition for Ethernet MMC Received Frames with CRC Error Counter Register */
\r
6683 #define ETH_MMCRFCECR_RFCEC ((uint32_t)0xFFFFFFFF) /* Number of frames received with CRC error. */
\r
6685 /* Bit definition for Ethernet MMC Received Frames with Alignement Error Counter Register */
\r
6686 #define ETH_MMCRFAECR_RFAEC ((uint32_t)0xFFFFFFFF) /* Number of frames received with alignment (dribble) error */
\r
6688 /* Bit definition for Ethernet MMC Received Good Unicast Frames Counter Register */
\r
6689 #define ETH_MMCRGUFCR_RGUFC ((uint32_t)0xFFFFFFFF) /* Number of good unicast frames received. */
\r
6691 /******************************************************************************/
\r
6692 /* Ethernet PTP Registers bits definition */
\r
6693 /******************************************************************************/
\r
6695 /* Bit definition for Ethernet PTP Time Stamp Contol Register */
\r
6696 #define ETH_PTPTSCR_TSCNT ((uint32_t)0x00030000) /* Time stamp clock node type */
\r
6697 #define ETH_PTPTSSR_TSSMRME ((uint32_t)0x00008000) /* Time stamp snapshot for message relevant to master enable */
\r
6698 #define ETH_PTPTSSR_TSSEME ((uint32_t)0x00004000) /* Time stamp snapshot for event message enable */
\r
6699 #define ETH_PTPTSSR_TSSIPV4FE ((uint32_t)0x00002000) /* Time stamp snapshot for IPv4 frames enable */
\r
6700 #define ETH_PTPTSSR_TSSIPV6FE ((uint32_t)0x00001000) /* Time stamp snapshot for IPv6 frames enable */
\r
6701 #define ETH_PTPTSSR_TSSPTPOEFE ((uint32_t)0x00000800) /* Time stamp snapshot for PTP over ethernet frames enable */
\r
6702 #define ETH_PTPTSSR_TSPTPPSV2E ((uint32_t)0x00000400) /* Time stamp PTP packet snooping for version2 format enable */
\r
6703 #define ETH_PTPTSSR_TSSSR ((uint32_t)0x00000200) /* Time stamp Sub-seconds rollover */
\r
6704 #define ETH_PTPTSSR_TSSARFE ((uint32_t)0x00000100) /* Time stamp snapshot for all received frames enable */
\r
6706 #define ETH_PTPTSCR_TSARU ((uint32_t)0x00000020) /* Addend register update */
\r
6707 #define ETH_PTPTSCR_TSITE ((uint32_t)0x00000010) /* Time stamp interrupt trigger enable */
\r
6708 #define ETH_PTPTSCR_TSSTU ((uint32_t)0x00000008) /* Time stamp update */
\r
6709 #define ETH_PTPTSCR_TSSTI ((uint32_t)0x00000004) /* Time stamp initialize */
\r
6710 #define ETH_PTPTSCR_TSFCU ((uint32_t)0x00000002) /* Time stamp fine or coarse update */
\r
6711 #define ETH_PTPTSCR_TSE ((uint32_t)0x00000001) /* Time stamp enable */
\r
6713 /* Bit definition for Ethernet PTP Sub-Second Increment Register */
\r
6714 #define ETH_PTPSSIR_STSSI ((uint32_t)0x000000FF) /* System time Sub-second increment value */
\r
6716 /* Bit definition for Ethernet PTP Time Stamp High Register */
\r
6717 #define ETH_PTPTSHR_STS ((uint32_t)0xFFFFFFFF) /* System Time second */
\r
6719 /* Bit definition for Ethernet PTP Time Stamp Low Register */
\r
6720 #define ETH_PTPTSLR_STPNS ((uint32_t)0x80000000) /* System Time Positive or negative time */
\r
6721 #define ETH_PTPTSLR_STSS ((uint32_t)0x7FFFFFFF) /* System Time sub-seconds */
\r
6723 /* Bit definition for Ethernet PTP Time Stamp High Update Register */
\r
6724 #define ETH_PTPTSHUR_TSUS ((uint32_t)0xFFFFFFFF) /* Time stamp update seconds */
\r
6726 /* Bit definition for Ethernet PTP Time Stamp Low Update Register */
\r
6727 #define ETH_PTPTSLUR_TSUPNS ((uint32_t)0x80000000) /* Time stamp update Positive or negative time */
\r
6728 #define ETH_PTPTSLUR_TSUSS ((uint32_t)0x7FFFFFFF) /* Time stamp update sub-seconds */
\r
6730 /* Bit definition for Ethernet PTP Time Stamp Addend Register */
\r
6731 #define ETH_PTPTSAR_TSA ((uint32_t)0xFFFFFFFF) /* Time stamp addend */
\r
6733 /* Bit definition for Ethernet PTP Target Time High Register */
\r
6734 #define ETH_PTPTTHR_TTSH ((uint32_t)0xFFFFFFFF) /* Target time stamp high */
\r
6736 /* Bit definition for Ethernet PTP Target Time Low Register */
\r
6737 #define ETH_PTPTTLR_TTSL ((uint32_t)0xFFFFFFFF) /* Target time stamp low */
\r
6739 /* Bit definition for Ethernet PTP Time Stamp Status Register */
\r
6740 #define ETH_PTPTSSR_TSTTR ((uint32_t)0x00000020) /* Time stamp target time reached */
\r
6741 #define ETH_PTPTSSR_TSSO ((uint32_t)0x00000010) /* Time stamp seconds overflow */
\r
6743 /******************************************************************************/
\r
6744 /* Ethernet DMA Registers bits definition */
\r
6745 /******************************************************************************/
\r
6747 /* Bit definition for Ethernet DMA Bus Mode Register */
\r
6748 #define ETH_DMABMR_AAB ((uint32_t)0x02000000) /* Address-Aligned beats */
\r
6749 #define ETH_DMABMR_FPM ((uint32_t)0x01000000) /* 4xPBL mode */
\r
6750 #define ETH_DMABMR_USP ((uint32_t)0x00800000) /* Use separate PBL */
\r
6751 #define ETH_DMABMR_RDP ((uint32_t)0x007E0000) /* RxDMA PBL */
\r
6752 #define ETH_DMABMR_RDP_1Beat ((uint32_t)0x00020000) /* maximum number of beats to be transferred in one RxDMA transaction is 1 */
\r
6753 #define ETH_DMABMR_RDP_2Beat ((uint32_t)0x00040000) /* maximum number of beats to be transferred in one RxDMA transaction is 2 */
\r
6754 #define ETH_DMABMR_RDP_4Beat ((uint32_t)0x00080000) /* maximum number of beats to be transferred in one RxDMA transaction is 4 */
\r
6755 #define ETH_DMABMR_RDP_8Beat ((uint32_t)0x00100000) /* maximum number of beats to be transferred in one RxDMA transaction is 8 */
\r
6756 #define ETH_DMABMR_RDP_16Beat ((uint32_t)0x00200000) /* maximum number of beats to be transferred in one RxDMA transaction is 16 */
\r
6757 #define ETH_DMABMR_RDP_32Beat ((uint32_t)0x00400000) /* maximum number of beats to be transferred in one RxDMA transaction is 32 */
\r
6758 #define ETH_DMABMR_RDP_4xPBL_4Beat ((uint32_t)0x01020000) /* maximum number of beats to be transferred in one RxDMA transaction is 4 */
\r
6759 #define ETH_DMABMR_RDP_4xPBL_8Beat ((uint32_t)0x01040000) /* maximum number of beats to be transferred in one RxDMA transaction is 8 */
\r
6760 #define ETH_DMABMR_RDP_4xPBL_16Beat ((uint32_t)0x01080000) /* maximum number of beats to be transferred in one RxDMA transaction is 16 */
\r
6761 #define ETH_DMABMR_RDP_4xPBL_32Beat ((uint32_t)0x01100000) /* maximum number of beats to be transferred in one RxDMA transaction is 32 */
\r
6762 #define ETH_DMABMR_RDP_4xPBL_64Beat ((uint32_t)0x01200000) /* maximum number of beats to be transferred in one RxDMA transaction is 64 */
\r
6763 #define ETH_DMABMR_RDP_4xPBL_128Beat ((uint32_t)0x01400000) /* maximum number of beats to be transferred in one RxDMA transaction is 128 */
\r
6764 #define ETH_DMABMR_FB ((uint32_t)0x00010000) /* Fixed Burst */
\r
6765 #define ETH_DMABMR_RTPR ((uint32_t)0x0000C000) /* Rx Tx priority ratio */
\r
6766 #define ETH_DMABMR_RTPR_1_1 ((uint32_t)0x00000000) /* Rx Tx priority ratio */
\r
6767 #define ETH_DMABMR_RTPR_2_1 ((uint32_t)0x00004000) /* Rx Tx priority ratio */
\r
6768 #define ETH_DMABMR_RTPR_3_1 ((uint32_t)0x00008000) /* Rx Tx priority ratio */
\r
6769 #define ETH_DMABMR_RTPR_4_1 ((uint32_t)0x0000C000) /* Rx Tx priority ratio */
\r
6770 #define ETH_DMABMR_PBL ((uint32_t)0x00003F00) /* Programmable burst length */
\r
6771 #define ETH_DMABMR_PBL_1Beat ((uint32_t)0x00000100) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 1 */
\r
6772 #define ETH_DMABMR_PBL_2Beat ((uint32_t)0x00000200) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 2 */
\r
6773 #define ETH_DMABMR_PBL_4Beat ((uint32_t)0x00000400) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */
\r
6774 #define ETH_DMABMR_PBL_8Beat ((uint32_t)0x00000800) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */
\r
6775 #define ETH_DMABMR_PBL_16Beat ((uint32_t)0x00001000) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */
\r
6776 #define ETH_DMABMR_PBL_32Beat ((uint32_t)0x00002000) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */
\r
6777 #define ETH_DMABMR_PBL_4xPBL_4Beat ((uint32_t)0x01000100) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */
\r
6778 #define ETH_DMABMR_PBL_4xPBL_8Beat ((uint32_t)0x01000200) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */
\r
6779 #define ETH_DMABMR_PBL_4xPBL_16Beat ((uint32_t)0x01000400) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */
\r
6780 #define ETH_DMABMR_PBL_4xPBL_32Beat ((uint32_t)0x01000800) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */
\r
6781 #define ETH_DMABMR_PBL_4xPBL_64Beat ((uint32_t)0x01001000) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 64 */
\r
6782 #define ETH_DMABMR_PBL_4xPBL_128Beat ((uint32_t)0x01002000) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 128 */
\r
6783 #define ETH_DMABMR_EDE ((uint32_t)0x00000080) /* Enhanced Descriptor Enable */
\r
6784 #define ETH_DMABMR_DSL ((uint32_t)0x0000007C) /* Descriptor Skip Length */
\r
6785 #define ETH_DMABMR_DA ((uint32_t)0x00000002) /* DMA arbitration scheme */
\r
6786 #define ETH_DMABMR_SR ((uint32_t)0x00000001) /* Software reset */
\r
6788 /* Bit definition for Ethernet DMA Transmit Poll Demand Register */
\r
6789 #define ETH_DMATPDR_TPD ((uint32_t)0xFFFFFFFF) /* Transmit poll demand */
\r
6791 /* Bit definition for Ethernet DMA Receive Poll Demand Register */
\r
6792 #define ETH_DMARPDR_RPD ((uint32_t)0xFFFFFFFF) /* Receive poll demand */
\r
6794 /* Bit definition for Ethernet DMA Receive Descriptor List Address Register */
\r
6795 #define ETH_DMARDLAR_SRL ((uint32_t)0xFFFFFFFF) /* Start of receive list */
\r
6797 /* Bit definition for Ethernet DMA Transmit Descriptor List Address Register */
\r
6798 #define ETH_DMATDLAR_STL ((uint32_t)0xFFFFFFFF) /* Start of transmit list */
\r
6800 /* Bit definition for Ethernet DMA Status Register */
\r
6801 #define ETH_DMASR_TSTS ((uint32_t)0x20000000) /* Time-stamp trigger status */
\r
6802 #define ETH_DMASR_PMTS ((uint32_t)0x10000000) /* PMT status */
\r
6803 #define ETH_DMASR_MMCS ((uint32_t)0x08000000) /* MMC status */
\r
6804 #define ETH_DMASR_EBS ((uint32_t)0x03800000) /* Error bits status */
\r
6805 /* combination with EBS[2:0] for GetFlagStatus function */
\r
6806 #define ETH_DMASR_EBS_DescAccess ((uint32_t)0x02000000) /* Error bits 0-data buffer, 1-desc. access */
\r
6807 #define ETH_DMASR_EBS_ReadTransf ((uint32_t)0x01000000) /* Error bits 0-write trnsf, 1-read transfr */
\r
6808 #define ETH_DMASR_EBS_DataTransfTx ((uint32_t)0x00800000) /* Error bits 0-Rx DMA, 1-Tx DMA */
\r
6809 #define ETH_DMASR_TPS ((uint32_t)0x00700000) /* Transmit process state */
\r
6810 #define ETH_DMASR_TPS_Stopped ((uint32_t)0x00000000) /* Stopped - Reset or Stop Tx Command issued */
\r
6811 #define ETH_DMASR_TPS_Fetching ((uint32_t)0x00100000) /* Running - fetching the Tx descriptor */
\r
6812 #define ETH_DMASR_TPS_Waiting ((uint32_t)0x00200000) /* Running - waiting for status */
\r
6813 #define ETH_DMASR_TPS_Reading ((uint32_t)0x00300000) /* Running - reading the data from host memory */
\r
6814 #define ETH_DMASR_TPS_Suspended ((uint32_t)0x00600000) /* Suspended - Tx Descriptor unavailabe */
\r
6815 #define ETH_DMASR_TPS_Closing ((uint32_t)0x00700000) /* Running - closing Rx descriptor */
\r
6816 #define ETH_DMASR_RPS ((uint32_t)0x000E0000) /* Receive process state */
\r
6817 #define ETH_DMASR_RPS_Stopped ((uint32_t)0x00000000) /* Stopped - Reset or Stop Rx Command issued */
\r
6818 #define ETH_DMASR_RPS_Fetching ((uint32_t)0x00020000) /* Running - fetching the Rx descriptor */
\r
6819 #define ETH_DMASR_RPS_Waiting ((uint32_t)0x00060000) /* Running - waiting for packet */
\r
6820 #define ETH_DMASR_RPS_Suspended ((uint32_t)0x00080000) /* Suspended - Rx Descriptor unavailable */
\r
6821 #define ETH_DMASR_RPS_Closing ((uint32_t)0x000A0000) /* Running - closing descriptor */
\r
6822 #define ETH_DMASR_RPS_Queuing ((uint32_t)0x000E0000) /* Running - queuing the recieve frame into host memory */
\r
6823 #define ETH_DMASR_NIS ((uint32_t)0x00010000) /* Normal interrupt summary */
\r
6824 #define ETH_DMASR_AIS ((uint32_t)0x00008000) /* Abnormal interrupt summary */
\r
6825 #define ETH_DMASR_ERS ((uint32_t)0x00004000) /* Early receive status */
\r
6826 #define ETH_DMASR_FBES ((uint32_t)0x00002000) /* Fatal bus error status */
\r
6827 #define ETH_DMASR_ETS ((uint32_t)0x00000400) /* Early transmit status */
\r
6828 #define ETH_DMASR_RWTS ((uint32_t)0x00000200) /* Receive watchdog timeout status */
\r
6829 #define ETH_DMASR_RPSS ((uint32_t)0x00000100) /* Receive process stopped status */
\r
6830 #define ETH_DMASR_RBUS ((uint32_t)0x00000080) /* Receive buffer unavailable status */
\r
6831 #define ETH_DMASR_RS ((uint32_t)0x00000040) /* Receive status */
\r
6832 #define ETH_DMASR_TUS ((uint32_t)0x00000020) /* Transmit underflow status */
\r
6833 #define ETH_DMASR_ROS ((uint32_t)0x00000010) /* Receive overflow status */
\r
6834 #define ETH_DMASR_TJTS ((uint32_t)0x00000008) /* Transmit jabber timeout status */
\r
6835 #define ETH_DMASR_TBUS ((uint32_t)0x00000004) /* Transmit buffer unavailable status */
\r
6836 #define ETH_DMASR_TPSS ((uint32_t)0x00000002) /* Transmit process stopped status */
\r
6837 #define ETH_DMASR_TS ((uint32_t)0x00000001) /* Transmit status */
\r
6839 /* Bit definition for Ethernet DMA Operation Mode Register */
\r
6840 #define ETH_DMAOMR_DTCEFD ((uint32_t)0x04000000) /* Disable Dropping of TCP/IP checksum error frames */
\r
6841 #define ETH_DMAOMR_RSF ((uint32_t)0x02000000) /* Receive store and forward */
\r
6842 #define ETH_DMAOMR_DFRF ((uint32_t)0x01000000) /* Disable flushing of received frames */
\r
6843 #define ETH_DMAOMR_TSF ((uint32_t)0x00200000) /* Transmit store and forward */
\r
6844 #define ETH_DMAOMR_FTF ((uint32_t)0x00100000) /* Flush transmit FIFO */
\r
6845 #define ETH_DMAOMR_TTC ((uint32_t)0x0001C000) /* Transmit threshold control */
\r
6846 #define ETH_DMAOMR_TTC_64Bytes ((uint32_t)0x00000000) /* threshold level of the MTL Transmit FIFO is 64 Bytes */
\r
6847 #define ETH_DMAOMR_TTC_128Bytes ((uint32_t)0x00004000) /* threshold level of the MTL Transmit FIFO is 128 Bytes */
\r
6848 #define ETH_DMAOMR_TTC_192Bytes ((uint32_t)0x00008000) /* threshold level of the MTL Transmit FIFO is 192 Bytes */
\r
6849 #define ETH_DMAOMR_TTC_256Bytes ((uint32_t)0x0000C000) /* threshold level of the MTL Transmit FIFO is 256 Bytes */
\r
6850 #define ETH_DMAOMR_TTC_40Bytes ((uint32_t)0x00010000) /* threshold level of the MTL Transmit FIFO is 40 Bytes */
\r
6851 #define ETH_DMAOMR_TTC_32Bytes ((uint32_t)0x00014000) /* threshold level of the MTL Transmit FIFO is 32 Bytes */
\r
6852 #define ETH_DMAOMR_TTC_24Bytes ((uint32_t)0x00018000) /* threshold level of the MTL Transmit FIFO is 24 Bytes */
\r
6853 #define ETH_DMAOMR_TTC_16Bytes ((uint32_t)0x0001C000) /* threshold level of the MTL Transmit FIFO is 16 Bytes */
\r
6854 #define ETH_DMAOMR_ST ((uint32_t)0x00002000) /* Start/stop transmission command */
\r
6855 #define ETH_DMAOMR_FEF ((uint32_t)0x00000080) /* Forward error frames */
\r
6856 #define ETH_DMAOMR_FUGF ((uint32_t)0x00000040) /* Forward undersized good frames */
\r
6857 #define ETH_DMAOMR_RTC ((uint32_t)0x00000018) /* receive threshold control */
\r
6858 #define ETH_DMAOMR_RTC_64Bytes ((uint32_t)0x00000000) /* threshold level of the MTL Receive FIFO is 64 Bytes */
\r
6859 #define ETH_DMAOMR_RTC_32Bytes ((uint32_t)0x00000008) /* threshold level of the MTL Receive FIFO is 32 Bytes */
\r
6860 #define ETH_DMAOMR_RTC_96Bytes ((uint32_t)0x00000010) /* threshold level of the MTL Receive FIFO is 96 Bytes */
\r
6861 #define ETH_DMAOMR_RTC_128Bytes ((uint32_t)0x00000018) /* threshold level of the MTL Receive FIFO is 128 Bytes */
\r
6862 #define ETH_DMAOMR_OSF ((uint32_t)0x00000004) /* operate on second frame */
\r
6863 #define ETH_DMAOMR_SR ((uint32_t)0x00000002) /* Start/stop receive */
\r
6865 /* Bit definition for Ethernet DMA Interrupt Enable Register */
\r
6866 #define ETH_DMAIER_NISE ((uint32_t)0x00010000) /* Normal interrupt summary enable */
\r
6867 #define ETH_DMAIER_AISE ((uint32_t)0x00008000) /* Abnormal interrupt summary enable */
\r
6868 #define ETH_DMAIER_ERIE ((uint32_t)0x00004000) /* Early receive interrupt enable */
\r
6869 #define ETH_DMAIER_FBEIE ((uint32_t)0x00002000) /* Fatal bus error interrupt enable */
\r
6870 #define ETH_DMAIER_ETIE ((uint32_t)0x00000400) /* Early transmit interrupt enable */
\r
6871 #define ETH_DMAIER_RWTIE ((uint32_t)0x00000200) /* Receive watchdog timeout interrupt enable */
\r
6872 #define ETH_DMAIER_RPSIE ((uint32_t)0x00000100) /* Receive process stopped interrupt enable */
\r
6873 #define ETH_DMAIER_RBUIE ((uint32_t)0x00000080) /* Receive buffer unavailable interrupt enable */
\r
6874 #define ETH_DMAIER_RIE ((uint32_t)0x00000040) /* Receive interrupt enable */
\r
6875 #define ETH_DMAIER_TUIE ((uint32_t)0x00000020) /* Transmit Underflow interrupt enable */
\r
6876 #define ETH_DMAIER_ROIE ((uint32_t)0x00000010) /* Receive Overflow interrupt enable */
\r
6877 #define ETH_DMAIER_TJTIE ((uint32_t)0x00000008) /* Transmit jabber timeout interrupt enable */
\r
6878 #define ETH_DMAIER_TBUIE ((uint32_t)0x00000004) /* Transmit buffer unavailable interrupt enable */
\r
6879 #define ETH_DMAIER_TPSIE ((uint32_t)0x00000002) /* Transmit process stopped interrupt enable */
\r
6880 #define ETH_DMAIER_TIE ((uint32_t)0x00000001) /* Transmit interrupt enable */
\r
6882 /* Bit definition for Ethernet DMA Missed Frame and Buffer Overflow Counter Register */
\r
6883 #define ETH_DMAMFBOCR_OFOC ((uint32_t)0x10000000) /* Overflow bit for FIFO overflow counter */
\r
6884 #define ETH_DMAMFBOCR_MFA ((uint32_t)0x0FFE0000) /* Number of frames missed by the application */
\r
6885 #define ETH_DMAMFBOCR_OMFC ((uint32_t)0x00010000) /* Overflow bit for missed frame counter */
\r
6886 #define ETH_DMAMFBOCR_MFC ((uint32_t)0x0000FFFF) /* Number of frames missed by the controller */
\r
6888 /* Bit definition for Ethernet DMA Current Host Transmit Descriptor Register */
\r
6889 #define ETH_DMACHTDR_HTDAP ((uint32_t)0xFFFFFFFF) /* Host transmit descriptor address pointer */
\r
6891 /* Bit definition for Ethernet DMA Current Host Receive Descriptor Register */
\r
6892 #define ETH_DMACHRDR_HRDAP ((uint32_t)0xFFFFFFFF) /* Host receive descriptor address pointer */
\r
6894 /* Bit definition for Ethernet DMA Current Host Transmit Buffer Address Register */
\r
6895 #define ETH_DMACHTBAR_HTBAP ((uint32_t)0xFFFFFFFF) /* Host transmit buffer address pointer */
\r
6897 /* Bit definition for Ethernet DMA Current Host Receive Buffer Address Register */
\r
6898 #define ETH_DMACHRBAR_HRBAP ((uint32_t)0xFFFFFFFF) /* Host receive buffer address pointer */
\r
6900 /******************************************************************************/
\r
6904 /******************************************************************************/
\r
6905 /******************** Bit definition forUSB_OTG_GOTGCTL register ********************/
\r
6906 #define USB_OTG_GOTGCTL_SRQSCS ((uint32_t)0x00000001) /*!< Session request success */
\r
6907 #define USB_OTG_GOTGCTL_SRQ ((uint32_t)0x00000002) /*!< Session request */
\r
6908 #define USB_OTG_GOTGCTL_HNGSCS ((uint32_t)0x00000100) /*!< Host negotiation success */
\r
6909 #define USB_OTG_GOTGCTL_HNPRQ ((uint32_t)0x00000200) /*!< HNP request */
\r
6910 #define USB_OTG_GOTGCTL_HSHNPEN ((uint32_t)0x00000400) /*!< Host set HNP enable */
\r
6911 #define USB_OTG_GOTGCTL_DHNPEN ((uint32_t)0x00000800) /*!< Device HNP enabled */
\r
6912 #define USB_OTG_GOTGCTL_CIDSTS ((uint32_t)0x00010000) /*!< Connector ID status */
\r
6913 #define USB_OTG_GOTGCTL_DBCT ((uint32_t)0x00020000) /*!< Long/short debounce time */
\r
6914 #define USB_OTG_GOTGCTL_ASVLD ((uint32_t)0x00040000) /*!< A-session valid */
\r
6915 #define USB_OTG_GOTGCTL_BSVLD ((uint32_t)0x00080000) /*!< B-session valid */
\r
6917 /******************** Bit definition forUSB_OTG_HCFG register ********************/
\r
6919 #define USB_OTG_HCFG_FSLSPCS ((uint32_t)0x00000003) /*!< FS/LS PHY clock select */
\r
6920 #define USB_OTG_HCFG_FSLSPCS_0 ((uint32_t)0x00000001) /*!<Bit 0 */
\r
6921 #define USB_OTG_HCFG_FSLSPCS_1 ((uint32_t)0x00000002) /*!<Bit 1 */
\r
6922 #define USB_OTG_HCFG_FSLSS ((uint32_t)0x00000004) /*!< FS- and LS-only support */
\r
6924 /******************** Bit definition forUSB_OTG_DCFG register ********************/
\r
6926 #define USB_OTG_DCFG_DSPD ((uint32_t)0x00000003) /*!< Device speed */
\r
6927 #define USB_OTG_DCFG_DSPD_0 ((uint32_t)0x00000001) /*!<Bit 0 */
\r
6928 #define USB_OTG_DCFG_DSPD_1 ((uint32_t)0x00000002) /*!<Bit 1 */
\r
6929 #define USB_OTG_DCFG_NZLSOHSK ((uint32_t)0x00000004) /*!< Nonzero-length status OUT handshake */
\r
6931 #define USB_OTG_DCFG_DAD ((uint32_t)0x000007F0) /*!< Device address */
\r
6932 #define USB_OTG_DCFG_DAD_0 ((uint32_t)0x00000010) /*!<Bit 0 */
\r
6933 #define USB_OTG_DCFG_DAD_1 ((uint32_t)0x00000020) /*!<Bit 1 */
\r
6934 #define USB_OTG_DCFG_DAD_2 ((uint32_t)0x00000040) /*!<Bit 2 */
\r
6935 #define USB_OTG_DCFG_DAD_3 ((uint32_t)0x00000080) /*!<Bit 3 */
\r
6936 #define USB_OTG_DCFG_DAD_4 ((uint32_t)0x00000100) /*!<Bit 4 */
\r
6937 #define USB_OTG_DCFG_DAD_5 ((uint32_t)0x00000200) /*!<Bit 5 */
\r
6938 #define USB_OTG_DCFG_DAD_6 ((uint32_t)0x00000400) /*!<Bit 6 */
\r
6940 #define USB_OTG_DCFG_PFIVL ((uint32_t)0x00001800) /*!< Periodic (micro)frame interval */
\r
6941 #define USB_OTG_DCFG_PFIVL_0 ((uint32_t)0x00000800) /*!<Bit 0 */
\r
6942 #define USB_OTG_DCFG_PFIVL_1 ((uint32_t)0x00001000) /*!<Bit 1 */
\r
6944 #define USB_OTG_DCFG_PERSCHIVL ((uint32_t)0x03000000) /*!< Periodic scheduling interval */
\r
6945 #define USB_OTG_DCFG_PERSCHIVL_0 ((uint32_t)0x01000000) /*!<Bit 0 */
\r
6946 #define USB_OTG_DCFG_PERSCHIVL_1 ((uint32_t)0x02000000) /*!<Bit 1 */
\r
6948 /******************** Bit definition forUSB_OTG_PCGCR register ********************/
\r
6949 #define USB_OTG_PCGCR_STPPCLK ((uint32_t)0x00000001) /*!< Stop PHY clock */
\r
6950 #define USB_OTG_PCGCR_GATEHCLK ((uint32_t)0x00000002) /*!< Gate HCLK */
\r
6951 #define USB_OTG_PCGCR_PHYSUSP ((uint32_t)0x00000010) /*!< PHY suspended */
\r
6953 /******************** Bit definition forUSB_OTG_GOTGINT register ********************/
\r
6954 #define USB_OTG_GOTGINT_SEDET ((uint32_t)0x00000004) /*!< Session end detected */
\r
6955 #define USB_OTG_GOTGINT_SRSSCHG ((uint32_t)0x00000100) /*!< Session request success status change */
\r
6956 #define USB_OTG_GOTGINT_HNSSCHG ((uint32_t)0x00000200) /*!< Host negotiation success status change */
\r
6957 #define USB_OTG_GOTGINT_HNGDET ((uint32_t)0x00020000) /*!< Host negotiation detected */
\r
6958 #define USB_OTG_GOTGINT_ADTOCHG ((uint32_t)0x00040000) /*!< A-device timeout change */
\r
6959 #define USB_OTG_GOTGINT_DBCDNE ((uint32_t)0x00080000) /*!< Debounce done */
\r
6961 /******************** Bit definition forUSB_OTG_DCTL register ********************/
\r
6962 #define USB_OTG_DCTL_RWUSIG ((uint32_t)0x00000001) /*!< Remote wakeup signaling */
\r
6963 #define USB_OTG_DCTL_SDIS ((uint32_t)0x00000002) /*!< Soft disconnect */
\r
6964 #define USB_OTG_DCTL_GINSTS ((uint32_t)0x00000004) /*!< Global IN NAK status */
\r
6965 #define USB_OTG_DCTL_GONSTS ((uint32_t)0x00000008) /*!< Global OUT NAK status */
\r
6967 #define USB_OTG_DCTL_TCTL ((uint32_t)0x00000070) /*!< Test control */
\r
6968 #define USB_OTG_DCTL_TCTL_0 ((uint32_t)0x00000010) /*!<Bit 0 */
\r
6969 #define USB_OTG_DCTL_TCTL_1 ((uint32_t)0x00000020) /*!<Bit 1 */
\r
6970 #define USB_OTG_DCTL_TCTL_2 ((uint32_t)0x00000040) /*!<Bit 2 */
\r
6971 #define USB_OTG_DCTL_SGINAK ((uint32_t)0x00000080) /*!< Set global IN NAK */
\r
6972 #define USB_OTG_DCTL_CGINAK ((uint32_t)0x00000100) /*!< Clear global IN NAK */
\r
6973 #define USB_OTG_DCTL_SGONAK ((uint32_t)0x00000200) /*!< Set global OUT NAK */
\r
6974 #define USB_OTG_DCTL_CGONAK ((uint32_t)0x00000400) /*!< Clear global OUT NAK */
\r
6975 #define USB_OTG_DCTL_POPRGDNE ((uint32_t)0x00000800) /*!< Power-on programming done */
\r
6977 /******************** Bit definition forUSB_OTG_HFIR register ********************/
\r
6978 #define USB_OTG_HFIR_FRIVL ((uint32_t)0x0000FFFF) /*!< Frame interval */
\r
6980 /******************** Bit definition forUSB_OTG_HFNUM register ********************/
\r
6981 #define USB_OTG_HFNUM_FRNUM ((uint32_t)0x0000FFFF) /*!< Frame number */
\r
6982 #define USB_OTG_HFNUM_FTREM ((uint32_t)0xFFFF0000) /*!< Frame time remaining */
\r
6984 /******************** Bit definition forUSB_OTG_DSTS register ********************/
\r
6985 #define USB_OTG_DSTS_SUSPSTS ((uint32_t)0x00000001) /*!< Suspend status */
\r
6987 #define USB_OTG_DSTS_ENUMSPD ((uint32_t)0x00000006) /*!< Enumerated speed */
\r
6988 #define USB_OTG_DSTS_ENUMSPD_0 ((uint32_t)0x00000002) /*!<Bit 0 */
\r
6989 #define USB_OTG_DSTS_ENUMSPD_1 ((uint32_t)0x00000004) /*!<Bit 1 */
\r
6990 #define USB_OTG_DSTS_EERR ((uint32_t)0x00000008) /*!< Erratic error */
\r
6991 #define USB_OTG_DSTS_FNSOF ((uint32_t)0x003FFF00) /*!< Frame number of the received SOF */
\r
6993 /******************** Bit definition forUSB_OTG_GAHBCFG register ********************/
\r
6994 #define USB_OTG_GAHBCFG_GINT ((uint32_t)0x00000001) /*!< Global interrupt mask */
\r
6996 #define USB_OTG_GAHBCFG_HBSTLEN ((uint32_t)0x0000001E) /*!< Burst length/type */
\r
6997 #define USB_OTG_GAHBCFG_HBSTLEN_0 ((uint32_t)0x00000002) /*!<Bit 0 */
\r
6998 #define USB_OTG_GAHBCFG_HBSTLEN_1 ((uint32_t)0x00000004) /*!<Bit 1 */
\r
6999 #define USB_OTG_GAHBCFG_HBSTLEN_2 ((uint32_t)0x00000008) /*!<Bit 2 */
\r
7000 #define USB_OTG_GAHBCFG_HBSTLEN_3 ((uint32_t)0x00000010) /*!<Bit 3 */
\r
7001 #define USB_OTG_GAHBCFG_DMAEN ((uint32_t)0x00000020) /*!< DMA enable */
\r
7002 #define USB_OTG_GAHBCFG_TXFELVL ((uint32_t)0x00000080) /*!< TxFIFO empty level */
\r
7003 #define USB_OTG_GAHBCFG_PTXFELVL ((uint32_t)0x00000100) /*!< Periodic TxFIFO empty level */
\r
7005 /******************** Bit definition forUSB_OTG_GUSBCFG register ********************/
\r
7007 #define USB_OTG_GUSBCFG_TOCAL ((uint32_t)0x00000007) /*!< FS timeout calibration */
\r
7008 #define USB_OTG_GUSBCFG_TOCAL_0 ((uint32_t)0x00000001) /*!<Bit 0 */
\r
7009 #define USB_OTG_GUSBCFG_TOCAL_1 ((uint32_t)0x00000002) /*!<Bit 1 */
\r
7010 #define USB_OTG_GUSBCFG_TOCAL_2 ((uint32_t)0x00000004) /*!<Bit 2 */
\r
7011 #define USB_OTG_GUSBCFG_PHYSEL ((uint32_t)0x00000040) /*!< USB 2.0 high-speed ULPI PHY or USB 1.1 full-speed serial transceiver select */
\r
7012 #define USB_OTG_GUSBCFG_SRPCAP ((uint32_t)0x00000100) /*!< SRP-capable */
\r
7013 #define USB_OTG_GUSBCFG_HNPCAP ((uint32_t)0x00000200) /*!< HNP-capable */
\r
7015 #define USB_OTG_GUSBCFG_TRDT ((uint32_t)0x00003C00) /*!< USB turnaround time */
\r
7016 #define USB_OTG_GUSBCFG_TRDT_0 ((uint32_t)0x00000400) /*!<Bit 0 */
\r
7017 #define USB_OTG_GUSBCFG_TRDT_1 ((uint32_t)0x00000800) /*!<Bit 1 */
\r
7018 #define USB_OTG_GUSBCFG_TRDT_2 ((uint32_t)0x00001000) /*!<Bit 2 */
\r
7019 #define USB_OTG_GUSBCFG_TRDT_3 ((uint32_t)0x00002000) /*!<Bit 3 */
\r
7020 #define USB_OTG_GUSBCFG_PHYLPCS ((uint32_t)0x00008000) /*!< PHY Low-power clock select */
\r
7021 #define USB_OTG_GUSBCFG_ULPIFSLS ((uint32_t)0x00020000) /*!< ULPI FS/LS select */
\r
7022 #define USB_OTG_GUSBCFG_ULPIAR ((uint32_t)0x00040000) /*!< ULPI Auto-resume */
\r
7023 #define USB_OTG_GUSBCFG_ULPICSM ((uint32_t)0x00080000) /*!< ULPI Clock SuspendM */
\r
7024 #define USB_OTG_GUSBCFG_ULPIEVBUSD ((uint32_t)0x00100000) /*!< ULPI External VBUS Drive */
\r
7025 #define USB_OTG_GUSBCFG_ULPIEVBUSI ((uint32_t)0x00200000) /*!< ULPI external VBUS indicator */
\r
7026 #define USB_OTG_GUSBCFG_TSDPS ((uint32_t)0x00400000) /*!< TermSel DLine pulsing selection */
\r
7027 #define USB_OTG_GUSBCFG_PCCI ((uint32_t)0x00800000) /*!< Indicator complement */
\r
7028 #define USB_OTG_GUSBCFG_PTCI ((uint32_t)0x01000000) /*!< Indicator pass through */
\r
7029 #define USB_OTG_GUSBCFG_ULPIIPD ((uint32_t)0x02000000) /*!< ULPI interface protect disable */
\r
7030 #define USB_OTG_GUSBCFG_FHMOD ((uint32_t)0x20000000) /*!< Forced host mode */
\r
7031 #define USB_OTG_GUSBCFG_FDMOD ((uint32_t)0x40000000) /*!< Forced peripheral mode */
\r
7032 #define USB_OTG_GUSBCFG_CTXPKT ((uint32_t)0x80000000) /*!< Corrupt Tx packet */
\r
7034 /******************** Bit definition forUSB_OTG_GRSTCTL register ********************/
\r
7035 #define USB_OTG_GRSTCTL_CSRST ((uint32_t)0x00000001) /*!< Core soft reset */
\r
7036 #define USB_OTG_GRSTCTL_HSRST ((uint32_t)0x00000002) /*!< HCLK soft reset */
\r
7037 #define USB_OTG_GRSTCTL_FCRST ((uint32_t)0x00000004) /*!< Host frame counter reset */
\r
7038 #define USB_OTG_GRSTCTL_RXFFLSH ((uint32_t)0x00000010) /*!< RxFIFO flush */
\r
7039 #define USB_OTG_GRSTCTL_TXFFLSH ((uint32_t)0x00000020) /*!< TxFIFO flush */
\r
7041 #define USB_OTG_GRSTCTL_TXFNUM ((uint32_t)0x000007C0) /*!< TxFIFO number */
\r
7042 #define USB_OTG_GRSTCTL_TXFNUM_0 ((uint32_t)0x00000040) /*!<Bit 0 */
\r
7043 #define USB_OTG_GRSTCTL_TXFNUM_1 ((uint32_t)0x00000080) /*!<Bit 1 */
\r
7044 #define USB_OTG_GRSTCTL_TXFNUM_2 ((uint32_t)0x00000100) /*!<Bit 2 */
\r
7045 #define USB_OTG_GRSTCTL_TXFNUM_3 ((uint32_t)0x00000200) /*!<Bit 3 */
\r
7046 #define USB_OTG_GRSTCTL_TXFNUM_4 ((uint32_t)0x00000400) /*!<Bit 4 */
\r
7047 #define USB_OTG_GRSTCTL_DMAREQ ((uint32_t)0x40000000) /*!< DMA request signal */
\r
7048 #define USB_OTG_GRSTCTL_AHBIDL ((uint32_t)0x80000000) /*!< AHB master idle */
\r
7050 /******************** Bit definition forUSB_OTG_DIEPMSK register ********************/
\r
7051 #define USB_OTG_DIEPMSK_XFRCM ((uint32_t)0x00000001) /*!< Transfer completed interrupt mask */
\r
7052 #define USB_OTG_DIEPMSK_EPDM ((uint32_t)0x00000002) /*!< Endpoint disabled interrupt mask */
\r
7053 #define USB_OTG_DIEPMSK_TOM ((uint32_t)0x00000008) /*!< Timeout condition mask (nonisochronous endpoints) */
\r
7054 #define USB_OTG_DIEPMSK_ITTXFEMSK ((uint32_t)0x00000010) /*!< IN token received when TxFIFO empty mask */
\r
7055 #define USB_OTG_DIEPMSK_INEPNMM ((uint32_t)0x00000020) /*!< IN token received with EP mismatch mask */
\r
7056 #define USB_OTG_DIEPMSK_INEPNEM ((uint32_t)0x00000040) /*!< IN endpoint NAK effective mask */
\r
7057 #define USB_OTG_DIEPMSK_TXFURM ((uint32_t)0x00000100) /*!< FIFO underrun mask */
\r
7058 #define USB_OTG_DIEPMSK_BIM ((uint32_t)0x00000200) /*!< BNA interrupt mask */
\r
7060 /******************** Bit definition forUSB_OTG_HPTXSTS register ********************/
\r
7061 #define USB_OTG_HPTXSTS_PTXFSAVL ((uint32_t)0x0000FFFF) /*!< Periodic transmit data FIFO space available */
\r
7063 #define USB_OTG_HPTXSTS_PTXQSAV ((uint32_t)0x00FF0000) /*!< Periodic transmit request queue space available */
\r
7064 #define USB_OTG_HPTXSTS_PTXQSAV_0 ((uint32_t)0x00010000) /*!<Bit 0 */
\r
7065 #define USB_OTG_HPTXSTS_PTXQSAV_1 ((uint32_t)0x00020000) /*!<Bit 1 */
\r
7066 #define USB_OTG_HPTXSTS_PTXQSAV_2 ((uint32_t)0x00040000) /*!<Bit 2 */
\r
7067 #define USB_OTG_HPTXSTS_PTXQSAV_3 ((uint32_t)0x00080000) /*!<Bit 3 */
\r
7068 #define USB_OTG_HPTXSTS_PTXQSAV_4 ((uint32_t)0x00100000) /*!<Bit 4 */
\r
7069 #define USB_OTG_HPTXSTS_PTXQSAV_5 ((uint32_t)0x00200000) /*!<Bit 5 */
\r
7070 #define USB_OTG_HPTXSTS_PTXQSAV_6 ((uint32_t)0x00400000) /*!<Bit 6 */
\r
7071 #define USB_OTG_HPTXSTS_PTXQSAV_7 ((uint32_t)0x00800000) /*!<Bit 7 */
\r
7073 #define USB_OTG_HPTXSTS_PTXQTOP ((uint32_t)0xFF000000) /*!< Top of the periodic transmit request queue */
\r
7074 #define USB_OTG_HPTXSTS_PTXQTOP_0 ((uint32_t)0x01000000) /*!<Bit 0 */
\r
7075 #define USB_OTG_HPTXSTS_PTXQTOP_1 ((uint32_t)0x02000000) /*!<Bit 1 */
\r
7076 #define USB_OTG_HPTXSTS_PTXQTOP_2 ((uint32_t)0x04000000) /*!<Bit 2 */
\r
7077 #define USB_OTG_HPTXSTS_PTXQTOP_3 ((uint32_t)0x08000000) /*!<Bit 3 */
\r
7078 #define USB_OTG_HPTXSTS_PTXQTOP_4 ((uint32_t)0x10000000) /*!<Bit 4 */
\r
7079 #define USB_OTG_HPTXSTS_PTXQTOP_5 ((uint32_t)0x20000000) /*!<Bit 5 */
\r
7080 #define USB_OTG_HPTXSTS_PTXQTOP_6 ((uint32_t)0x40000000) /*!<Bit 6 */
\r
7081 #define USB_OTG_HPTXSTS_PTXQTOP_7 ((uint32_t)0x80000000) /*!<Bit 7 */
\r
7083 /******************** Bit definition forUSB_OTG_HAINT register ********************/
\r
7084 #define USB_OTG_HAINT_HAINT ((uint32_t)0x0000FFFF) /*!< Channel interrupts */
\r
7086 /******************** Bit definition forUSB_OTG_DOEPMSK register ********************/
\r
7087 #define USB_OTG_DOEPMSK_XFRCM ((uint32_t)0x00000001) /*!< Transfer completed interrupt mask */
\r
7088 #define USB_OTG_DOEPMSK_EPDM ((uint32_t)0x00000002) /*!< Endpoint disabled interrupt mask */
\r
7089 #define USB_OTG_DOEPMSK_STUPM ((uint32_t)0x00000008) /*!< SETUP phase done mask */
\r
7090 #define USB_OTG_DOEPMSK_OTEPDM ((uint32_t)0x00000010) /*!< OUT token received when endpoint disabled mask */
\r
7091 #define USB_OTG_DOEPMSK_B2BSTUP ((uint32_t)0x00000040) /*!< Back-to-back SETUP packets received mask */
\r
7092 #define USB_OTG_DOEPMSK_OPEM ((uint32_t)0x00000100) /*!< OUT packet error mask */
\r
7093 #define USB_OTG_DOEPMSK_BOIM ((uint32_t)0x00000200) /*!< BNA interrupt mask */
\r
7095 /******************** Bit definition forUSB_OTG_GINTSTS register ********************/
\r
7096 #define USB_OTG_GINTSTS_CMOD ((uint32_t)0x00000001) /*!< Current mode of operation */
\r
7097 #define USB_OTG_GINTSTS_MMIS ((uint32_t)0x00000002) /*!< Mode mismatch interrupt */
\r
7098 #define USB_OTG_GINTSTS_OTGINT ((uint32_t)0x00000004) /*!< OTG interrupt */
\r
7099 #define USB_OTG_GINTSTS_SOF ((uint32_t)0x00000008) /*!< Start of frame */
\r
7100 #define USB_OTG_GINTSTS_RXFLVL ((uint32_t)0x00000010) /*!< RxFIFO nonempty */
\r
7101 #define USB_OTG_GINTSTS_NPTXFE ((uint32_t)0x00000020) /*!< Nonperiodic TxFIFO empty */
\r
7102 #define USB_OTG_GINTSTS_GINAKEFF ((uint32_t)0x00000040) /*!< Global IN nonperiodic NAK effective */
\r
7103 #define USB_OTG_GINTSTS_BOUTNAKEFF ((uint32_t)0x00000080) /*!< Global OUT NAK effective */
\r
7104 #define USB_OTG_GINTSTS_ESUSP ((uint32_t)0x00000400) /*!< Early suspend */
\r
7105 #define USB_OTG_GINTSTS_USBSUSP ((uint32_t)0x00000800) /*!< USB suspend */
\r
7106 #define USB_OTG_GINTSTS_USBRST ((uint32_t)0x00001000) /*!< USB reset */
\r
7107 #define USB_OTG_GINTSTS_ENUMDNE ((uint32_t)0x00002000) /*!< Enumeration done */
\r
7108 #define USB_OTG_GINTSTS_ISOODRP ((uint32_t)0x00004000) /*!< Isochronous OUT packet dropped interrupt */
\r
7109 #define USB_OTG_GINTSTS_EOPF ((uint32_t)0x00008000) /*!< End of periodic frame interrupt */
\r
7110 #define USB_OTG_GINTSTS_IEPINT ((uint32_t)0x00040000) /*!< IN endpoint interrupt */
\r
7111 #define USB_OTG_GINTSTS_OEPINT ((uint32_t)0x00080000) /*!< OUT endpoint interrupt */
\r
7112 #define USB_OTG_GINTSTS_IISOIXFR ((uint32_t)0x00100000) /*!< Incomplete isochronous IN transfer */
\r
7113 #define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT ((uint32_t)0x00200000) /*!< Incomplete periodic transfer */
\r
7114 #define USB_OTG_GINTSTS_DATAFSUSP ((uint32_t)0x00400000) /*!< Data fetch suspended */
\r
7115 #define USB_OTG_GINTSTS_HPRTINT ((uint32_t)0x01000000) /*!< Host port interrupt */
\r
7116 #define USB_OTG_GINTSTS_HCINT ((uint32_t)0x02000000) /*!< Host channels interrupt */
\r
7117 #define USB_OTG_GINTSTS_PTXFE ((uint32_t)0x04000000) /*!< Periodic TxFIFO empty */
\r
7118 #define USB_OTG_GINTSTS_CIDSCHG ((uint32_t)0x10000000) /*!< Connector ID status change */
\r
7119 #define USB_OTG_GINTSTS_DISCINT ((uint32_t)0x20000000) /*!< Disconnect detected interrupt */
\r
7120 #define USB_OTG_GINTSTS_SRQINT ((uint32_t)0x40000000) /*!< Session request/new session detected interrupt */
\r
7121 #define USB_OTG_GINTSTS_WKUINT ((uint32_t)0x80000000) /*!< Resume/remote wakeup detected interrupt */
\r
7123 /******************** Bit definition forUSB_OTG_GINTMSK register ********************/
\r
7124 #define USB_OTG_GINTMSK_MMISM ((uint32_t)0x00000002) /*!< Mode mismatch interrupt mask */
\r
7125 #define USB_OTG_GINTMSK_OTGINT ((uint32_t)0x00000004) /*!< OTG interrupt mask */
\r
7126 #define USB_OTG_GINTMSK_SOFM ((uint32_t)0x00000008) /*!< Start of frame mask */
\r
7127 #define USB_OTG_GINTMSK_RXFLVLM ((uint32_t)0x00000010) /*!< Receive FIFO nonempty mask */
\r
7128 #define USB_OTG_GINTMSK_NPTXFEM ((uint32_t)0x00000020) /*!< Nonperiodic TxFIFO empty mask */
\r
7129 #define USB_OTG_GINTMSK_GINAKEFFM ((uint32_t)0x00000040) /*!< Global nonperiodic IN NAK effective mask */
\r
7130 #define USB_OTG_GINTMSK_GONAKEFFM ((uint32_t)0x00000080) /*!< Global OUT NAK effective mask */
\r
7131 #define USB_OTG_GINTMSK_ESUSPM ((uint32_t)0x00000400) /*!< Early suspend mask */
\r
7132 #define USB_OTG_GINTMSK_USBSUSPM ((uint32_t)0x00000800) /*!< USB suspend mask */
\r
7133 #define USB_OTG_GINTMSK_USBRST ((uint32_t)0x00001000) /*!< USB reset mask */
\r
7134 #define USB_OTG_GINTMSK_ENUMDNEM ((uint32_t)0x00002000) /*!< Enumeration done mask */
\r
7135 #define USB_OTG_GINTMSK_ISOODRPM ((uint32_t)0x00004000) /*!< Isochronous OUT packet dropped interrupt mask */
\r
7136 #define USB_OTG_GINTMSK_EOPFM ((uint32_t)0x00008000) /*!< End of periodic frame interrupt mask */
\r
7137 #define USB_OTG_GINTMSK_EPMISM ((uint32_t)0x00020000) /*!< Endpoint mismatch interrupt mask */
\r
7138 #define USB_OTG_GINTMSK_IEPINT ((uint32_t)0x00040000) /*!< IN endpoints interrupt mask */
\r
7139 #define USB_OTG_GINTMSK_OEPINT ((uint32_t)0x00080000) /*!< OUT endpoints interrupt mask */
\r
7140 #define USB_OTG_GINTMSK_IISOIXFRM ((uint32_t)0x00100000) /*!< Incomplete isochronous IN transfer mask */
\r
7141 #define USB_OTG_GINTMSK_PXFRM_IISOOXFRM ((uint32_t)0x00200000) /*!< Incomplete periodic transfer mask */
\r
7142 #define USB_OTG_GINTMSK_FSUSPM ((uint32_t)0x00400000) /*!< Data fetch suspended mask */
\r
7143 #define USB_OTG_GINTMSK_PRTIM ((uint32_t)0x01000000) /*!< Host port interrupt mask */
\r
7144 #define USB_OTG_GINTMSK_HCIM ((uint32_t)0x02000000) /*!< Host channels interrupt mask */
\r
7145 #define USB_OTG_GINTMSK_PTXFEM ((uint32_t)0x04000000) /*!< Periodic TxFIFO empty mask */
\r
7146 #define USB_OTG_GINTMSK_CIDSCHGM ((uint32_t)0x10000000) /*!< Connector ID status change mask */
\r
7147 #define USB_OTG_GINTMSK_DISCINT ((uint32_t)0x20000000) /*!< Disconnect detected interrupt mask */
\r
7148 #define USB_OTG_GINTMSK_SRQIM ((uint32_t)0x40000000) /*!< Session request/new session detected interrupt mask */
\r
7149 #define USB_OTG_GINTMSK_WUIM ((uint32_t)0x80000000) /*!< Resume/remote wakeup detected interrupt mask */
\r
7151 /******************** Bit definition forUSB_OTG_DAINT register ********************/
\r
7152 #define USB_OTG_DAINT_IEPINT ((uint32_t)0x0000FFFF) /*!< IN endpoint interrupt bits */
\r
7153 #define USB_OTG_DAINT_OEPINT ((uint32_t)0xFFFF0000) /*!< OUT endpoint interrupt bits */
\r
7155 /******************** Bit definition forUSB_OTG_HAINTMSK register ********************/
\r
7156 #define USB_OTG_HAINTMSK_HAINTM ((uint32_t)0x0000FFFF) /*!< Channel interrupt mask */
\r
7158 /******************** Bit definition for USB_OTG_GRXSTSP register ********************/
\r
7159 #define USB_OTG_GRXSTSP_EPNUM ((uint32_t)0x0000000F) /*!< IN EP interrupt mask bits */
\r
7160 #define USB_OTG_GRXSTSP_BCNT ((uint32_t)0x00007FF0) /*!< OUT EP interrupt mask bits */
\r
7161 #define USB_OTG_GRXSTSP_DPID ((uint32_t)0x00018000) /*!< OUT EP interrupt mask bits */
\r
7162 #define USB_OTG_GRXSTSP_PKTSTS ((uint32_t)0x001E0000) /*!< OUT EP interrupt mask bits */
\r
7164 /******************** Bit definition forUSB_OTG_DAINTMSK register ********************/
\r
7165 #define USB_OTG_DAINTMSK_IEPM ((uint32_t)0x0000FFFF) /*!< IN EP interrupt mask bits */
\r
7166 #define USB_OTG_DAINTMSK_OEPM ((uint32_t)0xFFFF0000) /*!< OUT EP interrupt mask bits */
\r
7168 /******************** Bit definition for OTG register ********************/
\r
7170 #define USB_OTG_CHNUM ((uint32_t)0x0000000F) /*!< Channel number */
\r
7171 #define USB_OTG_CHNUM_0 ((uint32_t)0x00000001) /*!<Bit 0 */
\r
7172 #define USB_OTG_CHNUM_1 ((uint32_t)0x00000002) /*!<Bit 1 */
\r
7173 #define USB_OTG_CHNUM_2 ((uint32_t)0x00000004) /*!<Bit 2 */
\r
7174 #define USB_OTG_CHNUM_3 ((uint32_t)0x00000008) /*!<Bit 3 */
\r
7175 #define USB_OTG_BCNT ((uint32_t)0x00007FF0) /*!< Byte count */
\r
7177 #define USB_OTG_DPID ((uint32_t)0x00018000) /*!< Data PID */
\r
7178 #define USB_OTG_DPID_0 ((uint32_t)0x00008000) /*!<Bit 0 */
\r
7179 #define USB_OTG_DPID_1 ((uint32_t)0x00010000) /*!<Bit 1 */
\r
7181 #define USB_OTG_PKTSTS ((uint32_t)0x001E0000) /*!< Packet status */
\r
7182 #define USB_OTG_PKTSTS_0 ((uint32_t)0x00020000) /*!<Bit 0 */
\r
7183 #define USB_OTG_PKTSTS_1 ((uint32_t)0x00040000) /*!<Bit 1 */
\r
7184 #define USB_OTG_PKTSTS_2 ((uint32_t)0x00080000) /*!<Bit 2 */
\r
7185 #define USB_OTG_PKTSTS_3 ((uint32_t)0x00100000) /*!<Bit 3 */
\r
7187 #define USB_OTG_EPNUM ((uint32_t)0x0000000F) /*!< Endpoint number */
\r
7188 #define USB_OTG_EPNUM_0 ((uint32_t)0x00000001) /*!<Bit 0 */
\r
7189 #define USB_OTG_EPNUM_1 ((uint32_t)0x00000002) /*!<Bit 1 */
\r
7190 #define USB_OTG_EPNUM_2 ((uint32_t)0x00000004) /*!<Bit 2 */
\r
7191 #define USB_OTG_EPNUM_3 ((uint32_t)0x00000008) /*!<Bit 3 */
\r
7193 #define USB_OTG_FRMNUM ((uint32_t)0x01E00000) /*!< Frame number */
\r
7194 #define USB_OTG_FRMNUM_0 ((uint32_t)0x00200000) /*!<Bit 0 */
\r
7195 #define USB_OTG_FRMNUM_1 ((uint32_t)0x00400000) /*!<Bit 1 */
\r
7196 #define USB_OTG_FRMNUM_2 ((uint32_t)0x00800000) /*!<Bit 2 */
\r
7197 #define USB_OTG_FRMNUM_3 ((uint32_t)0x01000000) /*!<Bit 3 */
\r
7199 /******************** Bit definition for OTG register ********************/
\r
7201 #define USB_OTG_CHNUM ((uint32_t)0x0000000F) /*!< Channel number */
\r
7202 #define USB_OTG_CHNUM_0 ((uint32_t)0x00000001) /*!<Bit 0 */
\r
7203 #define USB_OTG_CHNUM_1 ((uint32_t)0x00000002) /*!<Bit 1 */
\r
7204 #define USB_OTG_CHNUM_2 ((uint32_t)0x00000004) /*!<Bit 2 */
\r
7205 #define USB_OTG_CHNUM_3 ((uint32_t)0x00000008) /*!<Bit 3 */
\r
7206 #define USB_OTG_BCNT ((uint32_t)0x00007FF0) /*!< Byte count */
\r
7208 #define USB_OTG_DPID ((uint32_t)0x00018000) /*!< Data PID */
\r
7209 #define USB_OTG_DPID_0 ((uint32_t)0x00008000) /*!<Bit 0 */
\r
7210 #define USB_OTG_DPID_1 ((uint32_t)0x00010000) /*!<Bit 1 */
\r
7212 #define USB_OTG_PKTSTS ((uint32_t)0x001E0000) /*!< Packet status */
\r
7213 #define USB_OTG_PKTSTS_0 ((uint32_t)0x00020000) /*!<Bit 0 */
\r
7214 #define USB_OTG_PKTSTS_1 ((uint32_t)0x00040000) /*!<Bit 1 */
\r
7215 #define USB_OTG_PKTSTS_2 ((uint32_t)0x00080000) /*!<Bit 2 */
\r
7216 #define USB_OTG_PKTSTS_3 ((uint32_t)0x00100000) /*!<Bit 3 */
\r
7218 #define USB_OTG_EPNUM ((uint32_t)0x0000000F) /*!< Endpoint number */
\r
7219 #define USB_OTG_EPNUM_0 ((uint32_t)0x00000001) /*!<Bit 0 */
\r
7220 #define USB_OTG_EPNUM_1 ((uint32_t)0x00000002) /*!<Bit 1 */
\r
7221 #define USB_OTG_EPNUM_2 ((uint32_t)0x00000004) /*!<Bit 2 */
\r
7222 #define USB_OTG_EPNUM_3 ((uint32_t)0x00000008) /*!<Bit 3 */
\r
7224 #define USB_OTG_FRMNUM ((uint32_t)0x01E00000) /*!< Frame number */
\r
7225 #define USB_OTG_FRMNUM_0 ((uint32_t)0x00200000) /*!<Bit 0 */
\r
7226 #define USB_OTG_FRMNUM_1 ((uint32_t)0x00400000) /*!<Bit 1 */
\r
7227 #define USB_OTG_FRMNUM_2 ((uint32_t)0x00800000) /*!<Bit 2 */
\r
7228 #define USB_OTG_FRMNUM_3 ((uint32_t)0x01000000) /*!<Bit 3 */
\r
7230 /******************** Bit definition forUSB_OTG_GRXFSIZ register ********************/
\r
7231 #define USB_OTG_GRXFSIZ_RXFD ((uint32_t)0x0000FFFF) /*!< RxFIFO depth */
\r
7233 /******************** Bit definition forUSB_OTG_DVBUSDIS register ********************/
\r
7234 #define USB_OTG_DVBUSDIS_VBUSDT ((uint32_t)0x0000FFFF) /*!< Device VBUS discharge time */
\r
7236 /******************** Bit definition for OTG register ********************/
\r
7237 #define USB_OTG_NPTXFSA ((uint32_t)0x0000FFFF) /*!< Nonperiodic transmit RAM start address */
\r
7238 #define USB_OTG_NPTXFD ((uint32_t)0xFFFF0000) /*!< Nonperiodic TxFIFO depth */
\r
7239 #define USB_OTG_TX0FSA ((uint32_t)0x0000FFFF) /*!< Endpoint 0 transmit RAM start address */
\r
7240 #define USB_OTG_TX0FD ((uint32_t)0xFFFF0000) /*!< Endpoint 0 TxFIFO depth */
\r
7242 /******************** Bit definition forUSB_OTG_DVBUSPULSE register ********************/
\r
7243 #define USB_OTG_DVBUSPULSE_DVBUSP ((uint32_t)0x00000FFF) /*!< Device VBUS pulsing time */
\r
7245 /******************** Bit definition forUSB_OTG_GNPTXSTS register ********************/
\r
7246 #define USB_OTG_GNPTXSTS_NPTXFSAV ((uint32_t)0x0000FFFF) /*!< Nonperiodic TxFIFO space available */
\r
7248 #define USB_OTG_GNPTXSTS_NPTQXSAV ((uint32_t)0x00FF0000) /*!< Nonperiodic transmit request queue space available */
\r
7249 #define USB_OTG_GNPTXSTS_NPTQXSAV_0 ((uint32_t)0x00010000) /*!<Bit 0 */
\r
7250 #define USB_OTG_GNPTXSTS_NPTQXSAV_1 ((uint32_t)0x00020000) /*!<Bit 1 */
\r
7251 #define USB_OTG_GNPTXSTS_NPTQXSAV_2 ((uint32_t)0x00040000) /*!<Bit 2 */
\r
7252 #define USB_OTG_GNPTXSTS_NPTQXSAV_3 ((uint32_t)0x00080000) /*!<Bit 3 */
\r
7253 #define USB_OTG_GNPTXSTS_NPTQXSAV_4 ((uint32_t)0x00100000) /*!<Bit 4 */
\r
7254 #define USB_OTG_GNPTXSTS_NPTQXSAV_5 ((uint32_t)0x00200000) /*!<Bit 5 */
\r
7255 #define USB_OTG_GNPTXSTS_NPTQXSAV_6 ((uint32_t)0x00400000) /*!<Bit 6 */
\r
7256 #define USB_OTG_GNPTXSTS_NPTQXSAV_7 ((uint32_t)0x00800000) /*!<Bit 7 */
\r
7258 #define USB_OTG_GNPTXSTS_NPTXQTOP ((uint32_t)0x7F000000) /*!< Top of the nonperiodic transmit request queue */
\r
7259 #define USB_OTG_GNPTXSTS_NPTXQTOP_0 ((uint32_t)0x01000000) /*!<Bit 0 */
\r
7260 #define USB_OTG_GNPTXSTS_NPTXQTOP_1 ((uint32_t)0x02000000) /*!<Bit 1 */
\r
7261 #define USB_OTG_GNPTXSTS_NPTXQTOP_2 ((uint32_t)0x04000000) /*!<Bit 2 */
\r
7262 #define USB_OTG_GNPTXSTS_NPTXQTOP_3 ((uint32_t)0x08000000) /*!<Bit 3 */
\r
7263 #define USB_OTG_GNPTXSTS_NPTXQTOP_4 ((uint32_t)0x10000000) /*!<Bit 4 */
\r
7264 #define USB_OTG_GNPTXSTS_NPTXQTOP_5 ((uint32_t)0x20000000) /*!<Bit 5 */
\r
7265 #define USB_OTG_GNPTXSTS_NPTXQTOP_6 ((uint32_t)0x40000000) /*!<Bit 6 */
\r
7267 /******************** Bit definition forUSB_OTG_DTHRCTL register ********************/
\r
7268 #define USB_OTG_DTHRCTL_NONISOTHREN ((uint32_t)0x00000001) /*!< Nonisochronous IN endpoints threshold enable */
\r
7269 #define USB_OTG_DTHRCTL_ISOTHREN ((uint32_t)0x00000002) /*!< ISO IN endpoint threshold enable */
\r
7271 #define USB_OTG_DTHRCTL_TXTHRLEN ((uint32_t)0x000007FC) /*!< Transmit threshold length */
\r
7272 #define USB_OTG_DTHRCTL_TXTHRLEN_0 ((uint32_t)0x00000004) /*!<Bit 0 */
\r
7273 #define USB_OTG_DTHRCTL_TXTHRLEN_1 ((uint32_t)0x00000008) /*!<Bit 1 */
\r
7274 #define USB_OTG_DTHRCTL_TXTHRLEN_2 ((uint32_t)0x00000010) /*!<Bit 2 */
\r
7275 #define USB_OTG_DTHRCTL_TXTHRLEN_3 ((uint32_t)0x00000020) /*!<Bit 3 */
\r
7276 #define USB_OTG_DTHRCTL_TXTHRLEN_4 ((uint32_t)0x00000040) /*!<Bit 4 */
\r
7277 #define USB_OTG_DTHRCTL_TXTHRLEN_5 ((uint32_t)0x00000080) /*!<Bit 5 */
\r
7278 #define USB_OTG_DTHRCTL_TXTHRLEN_6 ((uint32_t)0x00000100) /*!<Bit 6 */
\r
7279 #define USB_OTG_DTHRCTL_TXTHRLEN_7 ((uint32_t)0x00000200) /*!<Bit 7 */
\r
7280 #define USB_OTG_DTHRCTL_TXTHRLEN_8 ((uint32_t)0x00000400) /*!<Bit 8 */
\r
7281 #define USB_OTG_DTHRCTL_RXTHREN ((uint32_t)0x00010000) /*!< Receive threshold enable */
\r
7283 #define USB_OTG_DTHRCTL_RXTHRLEN ((uint32_t)0x03FE0000) /*!< Receive threshold length */
\r
7284 #define USB_OTG_DTHRCTL_RXTHRLEN_0 ((uint32_t)0x00020000) /*!<Bit 0 */
\r
7285 #define USB_OTG_DTHRCTL_RXTHRLEN_1 ((uint32_t)0x00040000) /*!<Bit 1 */
\r
7286 #define USB_OTG_DTHRCTL_RXTHRLEN_2 ((uint32_t)0x00080000) /*!<Bit 2 */
\r
7287 #define USB_OTG_DTHRCTL_RXTHRLEN_3 ((uint32_t)0x00100000) /*!<Bit 3 */
\r
7288 #define USB_OTG_DTHRCTL_RXTHRLEN_4 ((uint32_t)0x00200000) /*!<Bit 4 */
\r
7289 #define USB_OTG_DTHRCTL_RXTHRLEN_5 ((uint32_t)0x00400000) /*!<Bit 5 */
\r
7290 #define USB_OTG_DTHRCTL_RXTHRLEN_6 ((uint32_t)0x00800000) /*!<Bit 6 */
\r
7291 #define USB_OTG_DTHRCTL_RXTHRLEN_7 ((uint32_t)0x01000000) /*!<Bit 7 */
\r
7292 #define USB_OTG_DTHRCTL_RXTHRLEN_8 ((uint32_t)0x02000000) /*!<Bit 8 */
\r
7293 #define USB_OTG_DTHRCTL_ARPEN ((uint32_t)0x08000000) /*!< Arbiter parking enable */
\r
7295 /******************** Bit definition forUSB_OTG_DIEPEMPMSK register ********************/
\r
7296 #define USB_OTG_DIEPEMPMSK_INEPTXFEM ((uint32_t)0x0000FFFF) /*!< IN EP Tx FIFO empty interrupt mask bits */
\r
7298 /******************** Bit definition forUSB_OTG_DEACHINT register ********************/
\r
7299 #define USB_OTG_DEACHINT_IEP1INT ((uint32_t)0x00000002) /*!< IN endpoint 1interrupt bit */
\r
7300 #define USB_OTG_DEACHINT_OEP1INT ((uint32_t)0x00020000) /*!< OUT endpoint 1 interrupt bit */
\r
7302 /******************** Bit definition forUSB_OTG_GCCFG register ********************/
\r
7303 #define USB_OTG_GCCFG_PWRDWN ((uint32_t)0x00010000) /*!< Power down */
\r
7304 #define USB_OTG_GCCFG_I2CPADEN ((uint32_t)0x00020000) /*!< Enable I2C bus connection for the external I2C PHY interface */
\r
7305 #define USB_OTG_GCCFG_VBUSASEN ((uint32_t)0x00040000) /*!< Enable the VBUS sensing device */
\r
7306 #define USB_OTG_GCCFG_VBUSBSEN ((uint32_t)0x00080000) /*!< Enable the VBUS sensing device */
\r
7307 #define USB_OTG_GCCFG_SOFOUTEN ((uint32_t)0x00100000) /*!< SOF output enable */
\r
7308 #define USB_OTG_GCCFG_NOVBUSSENS ((uint32_t)0x00200000) /*!< VBUS sensing disable option */
\r
7310 /******************** Bit definition forUSB_OTG_DEACHINTMSK register ********************/
\r
7311 #define USB_OTG_DEACHINTMSK_IEP1INTM ((uint32_t)0x00000002) /*!< IN Endpoint 1 interrupt mask bit */
\r
7312 #define USB_OTG_DEACHINTMSK_OEP1INTM ((uint32_t)0x00020000) /*!< OUT Endpoint 1 interrupt mask bit */
\r
7314 /******************** Bit definition forUSB_OTG_CID register ********************/
\r
7315 #define USB_OTG_CID_PRODUCT_ID ((uint32_t)0xFFFFFFFF) /*!< Product ID field */
\r
7317 /******************** Bit definition forUSB_OTG_DIEPEACHMSK1 register ********************/
\r
7318 #define USB_OTG_DIEPEACHMSK1_XFRCM ((uint32_t)0x00000001) /*!< Transfer completed interrupt mask */
\r
7319 #define USB_OTG_DIEPEACHMSK1_EPDM ((uint32_t)0x00000002) /*!< Endpoint disabled interrupt mask */
\r
7320 #define USB_OTG_DIEPEACHMSK1_TOM ((uint32_t)0x00000008) /*!< Timeout condition mask (nonisochronous endpoints) */
\r
7321 #define USB_OTG_DIEPEACHMSK1_ITTXFEMSK ((uint32_t)0x00000010) /*!< IN token received when TxFIFO empty mask */
\r
7322 #define USB_OTG_DIEPEACHMSK1_INEPNMM ((uint32_t)0x00000020) /*!< IN token received with EP mismatch mask */
\r
7323 #define USB_OTG_DIEPEACHMSK1_INEPNEM ((uint32_t)0x00000040) /*!< IN endpoint NAK effective mask */
\r
7324 #define USB_OTG_DIEPEACHMSK1_TXFURM ((uint32_t)0x00000100) /*!< FIFO underrun mask */
\r
7325 #define USB_OTG_DIEPEACHMSK1_BIM ((uint32_t)0x00000200) /*!< BNA interrupt mask */
\r
7326 #define USB_OTG_DIEPEACHMSK1_NAKM ((uint32_t)0x00002000) /*!< NAK interrupt mask */
\r
7328 /******************** Bit definition forUSB_OTG_HPRT register ********************/
\r
7329 #define USB_OTG_HPRT_PCSTS ((uint32_t)0x00000001) /*!< Port connect status */
\r
7330 #define USB_OTG_HPRT_PCDET ((uint32_t)0x00000002) /*!< Port connect detected */
\r
7331 #define USB_OTG_HPRT_PENA ((uint32_t)0x00000004) /*!< Port enable */
\r
7332 #define USB_OTG_HPRT_PENCHNG ((uint32_t)0x00000008) /*!< Port enable/disable change */
\r
7333 #define USB_OTG_HPRT_POCA ((uint32_t)0x00000010) /*!< Port overcurrent active */
\r
7334 #define USB_OTG_HPRT_POCCHNG ((uint32_t)0x00000020) /*!< Port overcurrent change */
\r
7335 #define USB_OTG_HPRT_PRES ((uint32_t)0x00000040) /*!< Port resume */
\r
7336 #define USB_OTG_HPRT_PSUSP ((uint32_t)0x00000080) /*!< Port suspend */
\r
7337 #define USB_OTG_HPRT_PRST ((uint32_t)0x00000100) /*!< Port reset */
\r
7339 #define USB_OTG_HPRT_PLSTS ((uint32_t)0x00000C00) /*!< Port line status */
\r
7340 #define USB_OTG_HPRT_PLSTS_0 ((uint32_t)0x00000400) /*!<Bit 0 */
\r
7341 #define USB_OTG_HPRT_PLSTS_1 ((uint32_t)0x00000800) /*!<Bit 1 */
\r
7342 #define USB_OTG_HPRT_PPWR ((uint32_t)0x00001000) /*!< Port power */
\r
7344 #define USB_OTG_HPRT_PTCTL ((uint32_t)0x0001E000) /*!< Port test control */
\r
7345 #define USB_OTG_HPRT_PTCTL_0 ((uint32_t)0x00002000) /*!<Bit 0 */
\r
7346 #define USB_OTG_HPRT_PTCTL_1 ((uint32_t)0x00004000) /*!<Bit 1 */
\r
7347 #define USB_OTG_HPRT_PTCTL_2 ((uint32_t)0x00008000) /*!<Bit 2 */
\r
7348 #define USB_OTG_HPRT_PTCTL_3 ((uint32_t)0x00010000) /*!<Bit 3 */
\r
7350 #define USB_OTG_HPRT_PSPD ((uint32_t)0x00060000) /*!< Port speed */
\r
7351 #define USB_OTG_HPRT_PSPD_0 ((uint32_t)0x00020000) /*!<Bit 0 */
\r
7352 #define USB_OTG_HPRT_PSPD_1 ((uint32_t)0x00040000) /*!<Bit 1 */
\r
7354 /******************** Bit definition forUSB_OTG_DOEPEACHMSK1 register ********************/
\r
7355 #define USB_OTG_DOEPEACHMSK1_XFRCM ((uint32_t)0x00000001) /*!< Transfer completed interrupt mask */
\r
7356 #define USB_OTG_DOEPEACHMSK1_EPDM ((uint32_t)0x00000002) /*!< Endpoint disabled interrupt mask */
\r
7357 #define USB_OTG_DOEPEACHMSK1_TOM ((uint32_t)0x00000008) /*!< Timeout condition mask */
\r
7358 #define USB_OTG_DOEPEACHMSK1_ITTXFEMSK ((uint32_t)0x00000010) /*!< IN token received when TxFIFO empty mask */
\r
7359 #define USB_OTG_DOEPEACHMSK1_INEPNMM ((uint32_t)0x00000020) /*!< IN token received with EP mismatch mask */
\r
7360 #define USB_OTG_DOEPEACHMSK1_INEPNEM ((uint32_t)0x00000040) /*!< IN endpoint NAK effective mask */
\r
7361 #define USB_OTG_DOEPEACHMSK1_TXFURM ((uint32_t)0x00000100) /*!< OUT packet error mask */
\r
7362 #define USB_OTG_DOEPEACHMSK1_BIM ((uint32_t)0x00000200) /*!< BNA interrupt mask */
\r
7363 #define USB_OTG_DOEPEACHMSK1_BERRM ((uint32_t)0x00001000) /*!< Bubble error interrupt mask */
\r
7364 #define USB_OTG_DOEPEACHMSK1_NAKM ((uint32_t)0x00002000) /*!< NAK interrupt mask */
\r
7365 #define USB_OTG_DOEPEACHMSK1_NYETM ((uint32_t)0x00004000) /*!< NYET interrupt mask */
\r
7367 /******************** Bit definition forUSB_OTG_HPTXFSIZ register ********************/
\r
7368 #define USB_OTG_HPTXFSIZ_PTXSA ((uint32_t)0x0000FFFF) /*!< Host periodic TxFIFO start address */
\r
7369 #define USB_OTG_HPTXFSIZ_PTXFD ((uint32_t)0xFFFF0000) /*!< Host periodic TxFIFO depth */
\r
7371 /******************** Bit definition forUSB_OTG_DIEPCTL register ********************/
\r
7372 #define USB_OTG_DIEPCTL_MPSIZ ((uint32_t)0x000007FF) /*!< Maximum packet size */
\r
7373 #define USB_OTG_DIEPCTL_USBAEP ((uint32_t)0x00008000) /*!< USB active endpoint */
\r
7374 #define USB_OTG_DIEPCTL_EONUM_DPID ((uint32_t)0x00010000) /*!< Even/odd frame */
\r
7375 #define USB_OTG_DIEPCTL_NAKSTS ((uint32_t)0x00020000) /*!< NAK status */
\r
7377 #define USB_OTG_DIEPCTL_EPTYP ((uint32_t)0x000C0000) /*!< Endpoint type */
\r
7378 #define USB_OTG_DIEPCTL_EPTYP_0 ((uint32_t)0x00040000) /*!<Bit 0 */
\r
7379 #define USB_OTG_DIEPCTL_EPTYP_1 ((uint32_t)0x00080000) /*!<Bit 1 */
\r
7380 #define USB_OTG_DIEPCTL_STALL ((uint32_t)0x00200000) /*!< STALL handshake */
\r
7382 #define USB_OTG_DIEPCTL_TXFNUM ((uint32_t)0x03C00000) /*!< TxFIFO number */
\r
7383 #define USB_OTG_DIEPCTL_TXFNUM_0 ((uint32_t)0x00400000) /*!<Bit 0 */
\r
7384 #define USB_OTG_DIEPCTL_TXFNUM_1 ((uint32_t)0x00800000) /*!<Bit 1 */
\r
7385 #define USB_OTG_DIEPCTL_TXFNUM_2 ((uint32_t)0x01000000) /*!<Bit 2 */
\r
7386 #define USB_OTG_DIEPCTL_TXFNUM_3 ((uint32_t)0x02000000) /*!<Bit 3 */
\r
7387 #define USB_OTG_DIEPCTL_CNAK ((uint32_t)0x04000000) /*!< Clear NAK */
\r
7388 #define USB_OTG_DIEPCTL_SNAK ((uint32_t)0x08000000) /*!< Set NAK */
\r
7389 #define USB_OTG_DIEPCTL_SD0PID_SEVNFRM ((uint32_t)0x10000000) /*!< Set DATA0 PID */
\r
7390 #define USB_OTG_DIEPCTL_SODDFRM ((uint32_t)0x20000000) /*!< Set odd frame */
\r
7391 #define USB_OTG_DIEPCTL_EPDIS ((uint32_t)0x40000000) /*!< Endpoint disable */
\r
7392 #define USB_OTG_DIEPCTL_EPENA ((uint32_t)0x80000000) /*!< Endpoint enable */
\r
7394 /******************** Bit definition forUSB_OTG_HCCHAR register ********************/
\r
7395 #define USB_OTG_HCCHAR_MPSIZ ((uint32_t)0x000007FF) /*!< Maximum packet size */
\r
7397 #define USB_OTG_HCCHAR_EPNUM ((uint32_t)0x00007800) /*!< Endpoint number */
\r
7398 #define USB_OTG_HCCHAR_EPNUM_0 ((uint32_t)0x00000800) /*!<Bit 0 */
\r
7399 #define USB_OTG_HCCHAR_EPNUM_1 ((uint32_t)0x00001000) /*!<Bit 1 */
\r
7400 #define USB_OTG_HCCHAR_EPNUM_2 ((uint32_t)0x00002000) /*!<Bit 2 */
\r
7401 #define USB_OTG_HCCHAR_EPNUM_3 ((uint32_t)0x00004000) /*!<Bit 3 */
\r
7402 #define USB_OTG_HCCHAR_EPDIR ((uint32_t)0x00008000) /*!< Endpoint direction */
\r
7403 #define USB_OTG_HCCHAR_LSDEV ((uint32_t)0x00020000) /*!< Low-speed device */
\r
7405 #define USB_OTG_HCCHAR_EPTYP ((uint32_t)0x000C0000) /*!< Endpoint type */
\r
7406 #define USB_OTG_HCCHAR_EPTYP_0 ((uint32_t)0x00040000) /*!<Bit 0 */
\r
7407 #define USB_OTG_HCCHAR_EPTYP_1 ((uint32_t)0x00080000) /*!<Bit 1 */
\r
7409 #define USB_OTG_HCCHAR_MC ((uint32_t)0x00300000) /*!< Multi Count (MC) / Error Count (EC) */
\r
7410 #define USB_OTG_HCCHAR_MC_0 ((uint32_t)0x00100000) /*!<Bit 0 */
\r
7411 #define USB_OTG_HCCHAR_MC_1 ((uint32_t)0x00200000) /*!<Bit 1 */
\r
7413 #define USB_OTG_HCCHAR_DAD ((uint32_t)0x1FC00000) /*!< Device address */
\r
7414 #define USB_OTG_HCCHAR_DAD_0 ((uint32_t)0x00400000) /*!<Bit 0 */
\r
7415 #define USB_OTG_HCCHAR_DAD_1 ((uint32_t)0x00800000) /*!<Bit 1 */
\r
7416 #define USB_OTG_HCCHAR_DAD_2 ((uint32_t)0x01000000) /*!<Bit 2 */
\r
7417 #define USB_OTG_HCCHAR_DAD_3 ((uint32_t)0x02000000) /*!<Bit 3 */
\r
7418 #define USB_OTG_HCCHAR_DAD_4 ((uint32_t)0x04000000) /*!<Bit 4 */
\r
7419 #define USB_OTG_HCCHAR_DAD_5 ((uint32_t)0x08000000) /*!<Bit 5 */
\r
7420 #define USB_OTG_HCCHAR_DAD_6 ((uint32_t)0x10000000) /*!<Bit 6 */
\r
7421 #define USB_OTG_HCCHAR_ODDFRM ((uint32_t)0x20000000) /*!< Odd frame */
\r
7422 #define USB_OTG_HCCHAR_CHDIS ((uint32_t)0x40000000) /*!< Channel disable */
\r
7423 #define USB_OTG_HCCHAR_CHENA ((uint32_t)0x80000000) /*!< Channel enable */
\r
7425 /******************** Bit definition forUSB_OTG_HCSPLT register ********************/
\r
7427 #define USB_OTG_HCSPLT_PRTADDR ((uint32_t)0x0000007F) /*!< Port address */
\r
7428 #define USB_OTG_HCSPLT_PRTADDR_0 ((uint32_t)0x00000001) /*!<Bit 0 */
\r
7429 #define USB_OTG_HCSPLT_PRTADDR_1 ((uint32_t)0x00000002) /*!<Bit 1 */
\r
7430 #define USB_OTG_HCSPLT_PRTADDR_2 ((uint32_t)0x00000004) /*!<Bit 2 */
\r
7431 #define USB_OTG_HCSPLT_PRTADDR_3 ((uint32_t)0x00000008) /*!<Bit 3 */
\r
7432 #define USB_OTG_HCSPLT_PRTADDR_4 ((uint32_t)0x00000010) /*!<Bit 4 */
\r
7433 #define USB_OTG_HCSPLT_PRTADDR_5 ((uint32_t)0x00000020) /*!<Bit 5 */
\r
7434 #define USB_OTG_HCSPLT_PRTADDR_6 ((uint32_t)0x00000040) /*!<Bit 6 */
\r
7436 #define USB_OTG_HCSPLT_HUBADDR ((uint32_t)0x00003F80) /*!< Hub address */
\r
7437 #define USB_OTG_HCSPLT_HUBADDR_0 ((uint32_t)0x00000080) /*!<Bit 0 */
\r
7438 #define USB_OTG_HCSPLT_HUBADDR_1 ((uint32_t)0x00000100) /*!<Bit 1 */
\r
7439 #define USB_OTG_HCSPLT_HUBADDR_2 ((uint32_t)0x00000200) /*!<Bit 2 */
\r
7440 #define USB_OTG_HCSPLT_HUBADDR_3 ((uint32_t)0x00000400) /*!<Bit 3 */
\r
7441 #define USB_OTG_HCSPLT_HUBADDR_4 ((uint32_t)0x00000800) /*!<Bit 4 */
\r
7442 #define USB_OTG_HCSPLT_HUBADDR_5 ((uint32_t)0x00001000) /*!<Bit 5 */
\r
7443 #define USB_OTG_HCSPLT_HUBADDR_6 ((uint32_t)0x00002000) /*!<Bit 6 */
\r
7445 #define USB_OTG_HCSPLT_XACTPOS ((uint32_t)0x0000C000) /*!< XACTPOS */
\r
7446 #define USB_OTG_HCSPLT_XACTPOS_0 ((uint32_t)0x00004000) /*!<Bit 0 */
\r
7447 #define USB_OTG_HCSPLT_XACTPOS_1 ((uint32_t)0x00008000) /*!<Bit 1 */
\r
7448 #define USB_OTG_HCSPLT_COMPLSPLT ((uint32_t)0x00010000) /*!< Do complete split */
\r
7449 #define USB_OTG_HCSPLT_SPLITEN ((uint32_t)0x80000000) /*!< Split enable */
\r
7451 /******************** Bit definition forUSB_OTG_HCINT register ********************/
\r
7452 #define USB_OTG_HCINT_XFRC ((uint32_t)0x00000001) /*!< Transfer completed */
\r
7453 #define USB_OTG_HCINT_CHH ((uint32_t)0x00000002) /*!< Channel halted */
\r
7454 #define USB_OTG_HCINT_AHBERR ((uint32_t)0x00000004) /*!< AHB error */
\r
7455 #define USB_OTG_HCINT_STALL ((uint32_t)0x00000008) /*!< STALL response received interrupt */
\r
7456 #define USB_OTG_HCINT_NAK ((uint32_t)0x00000010) /*!< NAK response received interrupt */
\r
7457 #define USB_OTG_HCINT_ACK ((uint32_t)0x00000020) /*!< ACK response received/transmitted interrupt */
\r
7458 #define USB_OTG_HCINT_NYET ((uint32_t)0x00000040) /*!< Response received interrupt */
\r
7459 #define USB_OTG_HCINT_TXERR ((uint32_t)0x00000080) /*!< Transaction error */
\r
7460 #define USB_OTG_HCINT_BBERR ((uint32_t)0x00000100) /*!< Babble error */
\r
7461 #define USB_OTG_HCINT_FRMOR ((uint32_t)0x00000200) /*!< Frame overrun */
\r
7462 #define USB_OTG_HCINT_DTERR ((uint32_t)0x00000400) /*!< Data toggle error */
\r
7464 /******************** Bit definition forUSB_OTG_DIEPINT register ********************/
\r
7465 #define USB_OTG_DIEPINT_XFRC ((uint32_t)0x00000001) /*!< Transfer completed interrupt */
\r
7466 #define USB_OTG_DIEPINT_EPDISD ((uint32_t)0x00000002) /*!< Endpoint disabled interrupt */
\r
7467 #define USB_OTG_DIEPINT_TOC ((uint32_t)0x00000008) /*!< Timeout condition */
\r
7468 #define USB_OTG_DIEPINT_ITTXFE ((uint32_t)0x00000010) /*!< IN token received when TxFIFO is empty */
\r
7469 #define USB_OTG_DIEPINT_INEPNE ((uint32_t)0x00000040) /*!< IN endpoint NAK effective */
\r
7470 #define USB_OTG_DIEPINT_TXFE ((uint32_t)0x00000080) /*!< Transmit FIFO empty */
\r
7471 #define USB_OTG_DIEPINT_TXFIFOUDRN ((uint32_t)0x00000100) /*!< Transmit Fifo Underrun */
\r
7472 #define USB_OTG_DIEPINT_BNA ((uint32_t)0x00000200) /*!< Buffer not available interrupt */
\r
7473 #define USB_OTG_DIEPINT_PKTDRPSTS ((uint32_t)0x00000800) /*!< Packet dropped status */
\r
7474 #define USB_OTG_DIEPINT_BERR ((uint32_t)0x00001000) /*!< Babble error interrupt */
\r
7475 #define USB_OTG_DIEPINT_NAK ((uint32_t)0x00002000) /*!< NAK interrupt */
\r
7477 /******************** Bit definition forUSB_OTG_HCINTMSK register ********************/
\r
7478 #define USB_OTG_HCINTMSK_XFRCM ((uint32_t)0x00000001) /*!< Transfer completed mask */
\r
7479 #define USB_OTG_HCINTMSK_CHHM ((uint32_t)0x00000002) /*!< Channel halted mask */
\r
7480 #define USB_OTG_HCINTMSK_AHBERR ((uint32_t)0x00000004) /*!< AHB error */
\r
7481 #define USB_OTG_HCINTMSK_STALLM ((uint32_t)0x00000008) /*!< STALL response received interrupt mask */
\r
7482 #define USB_OTG_HCINTMSK_NAKM ((uint32_t)0x00000010) /*!< NAK response received interrupt mask */
\r
7483 #define USB_OTG_HCINTMSK_ACKM ((uint32_t)0x00000020) /*!< ACK response received/transmitted interrupt mask */
\r
7484 #define USB_OTG_HCINTMSK_NYET ((uint32_t)0x00000040) /*!< response received interrupt mask */
\r
7485 #define USB_OTG_HCINTMSK_TXERRM ((uint32_t)0x00000080) /*!< Transaction error mask */
\r
7486 #define USB_OTG_HCINTMSK_BBERRM ((uint32_t)0x00000100) /*!< Babble error mask */
\r
7487 #define USB_OTG_HCINTMSK_FRMORM ((uint32_t)0x00000200) /*!< Frame overrun mask */
\r
7488 #define USB_OTG_HCINTMSK_DTERRM ((uint32_t)0x00000400) /*!< Data toggle error mask */
\r
7490 /******************** Bit definition for USB_OTG_DIEPTSIZ register ********************/
\r
7492 #define USB_OTG_DIEPTSIZ_XFRSIZ ((uint32_t)0x0007FFFF) /*!< Transfer size */
\r
7493 #define USB_OTG_DIEPTSIZ_PKTCNT ((uint32_t)0x1FF80000) /*!< Packet count */
\r
7494 #define USB_OTG_DIEPTSIZ_MULCNT ((uint32_t)0x60000000) /*!< Packet count */
\r
7495 /******************** Bit definition forUSB_OTG_HCTSIZ register ********************/
\r
7496 #define USB_OTG_HCTSIZ_XFRSIZ ((uint32_t)0x0007FFFF) /*!< Transfer size */
\r
7497 #define USB_OTG_HCTSIZ_PKTCNT ((uint32_t)0x1FF80000) /*!< Packet count */
\r
7498 #define USB_OTG_HCTSIZ_DOPING ((uint32_t)0x80000000) /*!< Do PING */
\r
7499 #define USB_OTG_HCTSIZ_DPID ((uint32_t)0x60000000) /*!< Data PID */
\r
7500 #define USB_OTG_HCTSIZ_DPID_0 ((uint32_t)0x20000000) /*!<Bit 0 */
\r
7501 #define USB_OTG_HCTSIZ_DPID_1 ((uint32_t)0x40000000) /*!<Bit 1 */
\r
7503 /******************** Bit definition forUSB_OTG_DIEPDMA register ********************/
\r
7504 #define USB_OTG_DIEPDMA_DMAADDR ((uint32_t)0xFFFFFFFF) /*!< DMA address */
\r
7506 /******************** Bit definition forUSB_OTG_HCDMA register ********************/
\r
7507 #define USB_OTG_HCDMA_DMAADDR ((uint32_t)0xFFFFFFFF) /*!< DMA address */
\r
7509 /******************** Bit definition forUSB_OTG_DTXFSTS register ********************/
\r
7510 #define USB_OTG_DTXFSTS_INEPTFSAV ((uint32_t)0x0000FFFF) /*!< IN endpoint TxFIFO space avail */
\r
7512 /******************** Bit definition forUSB_OTG_DIEPTXF register ********************/
\r
7513 #define USB_OTG_DIEPTXF_INEPTXSA ((uint32_t)0x0000FFFF) /*!< IN endpoint FIFOx transmit RAM start address */
\r
7514 #define USB_OTG_DIEPTXF_INEPTXFD ((uint32_t)0xFFFF0000) /*!< IN endpoint TxFIFO depth */
\r
7516 /******************** Bit definition forUSB_OTG_DOEPCTL register ********************/
\r
7518 #define USB_OTG_DOEPCTL_MPSIZ ((uint32_t)0x000007FF) /*!< Maximum packet size */ /*!<Bit 1 */
\r
7519 #define USB_OTG_DOEPCTL_USBAEP ((uint32_t)0x00008000) /*!< USB active endpoint */
\r
7520 #define USB_OTG_DOEPCTL_NAKSTS ((uint32_t)0x00020000) /*!< NAK status */
\r
7521 #define USB_OTG_DOEPCTL_SD0PID_SEVNFRM ((uint32_t)0x10000000) /*!< Set DATA0 PID */
\r
7522 #define USB_OTG_DOEPCTL_SODDFRM ((uint32_t)0x20000000) /*!< Set odd frame */
\r
7523 #define USB_OTG_DOEPCTL_EPTYP ((uint32_t)0x000C0000) /*!< Endpoint type */
\r
7524 #define USB_OTG_DOEPCTL_EPTYP_0 ((uint32_t)0x00040000) /*!<Bit 0 */
\r
7525 #define USB_OTG_DOEPCTL_EPTYP_1 ((uint32_t)0x00080000) /*!<Bit 1 */
\r
7526 #define USB_OTG_DOEPCTL_SNPM ((uint32_t)0x00100000) /*!< Snoop mode */
\r
7527 #define USB_OTG_DOEPCTL_STALL ((uint32_t)0x00200000) /*!< STALL handshake */
\r
7528 #define USB_OTG_DOEPCTL_CNAK ((uint32_t)0x04000000) /*!< Clear NAK */
\r
7529 #define USB_OTG_DOEPCTL_SNAK ((uint32_t)0x08000000) /*!< Set NAK */
\r
7530 #define USB_OTG_DOEPCTL_EPDIS ((uint32_t)0x40000000) /*!< Endpoint disable */
\r
7531 #define USB_OTG_DOEPCTL_EPENA ((uint32_t)0x80000000) /*!< Endpoint enable */
\r
7533 /******************** Bit definition forUSB_OTG_DOEPINT register ********************/
\r
7534 #define USB_OTG_DOEPINT_XFRC ((uint32_t)0x00000001) /*!< Transfer completed interrupt */
\r
7535 #define USB_OTG_DOEPINT_EPDISD ((uint32_t)0x00000002) /*!< Endpoint disabled interrupt */
\r
7536 #define USB_OTG_DOEPINT_STUP ((uint32_t)0x00000008) /*!< SETUP phase done */
\r
7537 #define USB_OTG_DOEPINT_OTEPDIS ((uint32_t)0x00000010) /*!< OUT token received when endpoint disabled */
\r
7538 #define USB_OTG_DOEPINT_B2BSTUP ((uint32_t)0x00000040) /*!< Back-to-back SETUP packets received */
\r
7539 #define USB_OTG_DOEPINT_NYET ((uint32_t)0x00004000) /*!< NYET interrupt */
\r
7541 /******************** Bit definition forUSB_OTG_DOEPTSIZ register ********************/
\r
7543 #define USB_OTG_DOEPTSIZ_XFRSIZ ((uint32_t)0x0007FFFF) /*!< Transfer size */
\r
7544 #define USB_OTG_DOEPTSIZ_PKTCNT ((uint32_t)0x1FF80000) /*!< Packet count */
\r
7546 #define USB_OTG_DOEPTSIZ_STUPCNT ((uint32_t)0x60000000) /*!< SETUP packet count */
\r
7547 #define USB_OTG_DOEPTSIZ_STUPCNT_0 ((uint32_t)0x20000000) /*!<Bit 0 */
\r
7548 #define USB_OTG_DOEPTSIZ_STUPCNT_1 ((uint32_t)0x40000000) /*!<Bit 1 */
\r
7550 /******************** Bit definition for PCGCCTL register ********************/
\r
7551 #define USB_OTG_PCGCCTL_STOPCLK ((uint32_t)0x00000001) /*!< SETUP packet count */
\r
7552 #define USB_OTG_PCGCCTL_GATECLK ((uint32_t)0x00000002) /*!<Bit 0 */
\r
7553 #define USB_OTG_PCGCCTL_PHYSUSP ((uint32_t)0x00000010) /*!<Bit 1 */
\r
7563 /** @addtogroup Exported_macros
\r
7567 /******************************* ADC Instances ********************************/
\r
7568 #define IS_ADC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == ADC1) || \
\r
7569 ((INSTANCE) == ADC2) || \
\r
7570 ((INSTANCE) == ADC3))
\r
7572 /******************************* CAN Instances ********************************/
\r
7573 #define IS_CAN_ALL_INSTANCE(INSTANCE) (((INSTANCE) == CAN1) || \
\r
7574 ((INSTANCE) == CAN2))
\r
7576 /******************************* CRC Instances ********************************/
\r
7577 #define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)
\r
7579 /******************************* DAC Instances ********************************/
\r
7580 #define IS_DAC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DAC)
\r
7582 /******************************* DCMI Instances *******************************/
\r
7583 #define IS_DCMI_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DCMI)
\r
7585 /******************************** DMA Instances *******************************/
\r
7586 #define IS_DMA_STREAM_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Stream0) || \
\r
7587 ((INSTANCE) == DMA1_Stream1) || \
\r
7588 ((INSTANCE) == DMA1_Stream2) || \
\r
7589 ((INSTANCE) == DMA1_Stream3) || \
\r
7590 ((INSTANCE) == DMA1_Stream4) || \
\r
7591 ((INSTANCE) == DMA1_Stream5) || \
\r
7592 ((INSTANCE) == DMA1_Stream6) || \
\r
7593 ((INSTANCE) == DMA1_Stream7) || \
\r
7594 ((INSTANCE) == DMA2_Stream0) || \
\r
7595 ((INSTANCE) == DMA2_Stream1) || \
\r
7596 ((INSTANCE) == DMA2_Stream2) || \
\r
7597 ((INSTANCE) == DMA2_Stream3) || \
\r
7598 ((INSTANCE) == DMA2_Stream4) || \
\r
7599 ((INSTANCE) == DMA2_Stream5) || \
\r
7600 ((INSTANCE) == DMA2_Stream6) || \
\r
7601 ((INSTANCE) == DMA2_Stream7))
\r
7603 /******************************* GPIO Instances *******************************/
\r
7604 #define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
\r
7605 ((INSTANCE) == GPIOB) || \
\r
7606 ((INSTANCE) == GPIOC) || \
\r
7607 ((INSTANCE) == GPIOD) || \
\r
7608 ((INSTANCE) == GPIOE) || \
\r
7609 ((INSTANCE) == GPIOF) || \
\r
7610 ((INSTANCE) == GPIOG) || \
\r
7611 ((INSTANCE) == GPIOH) || \
\r
7612 ((INSTANCE) == GPIOI))
\r
7614 /******************************** I2C Instances *******************************/
\r
7615 #define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
\r
7616 ((INSTANCE) == I2C2) || \
\r
7617 ((INSTANCE) == I2C3))
\r
7619 /******************************** I2S Instances *******************************/
\r
7620 #define IS_I2S_INSTANCE(INSTANCE) (((INSTANCE) == SPI2) || \
\r
7621 ((INSTANCE) == SPI3))
\r
7623 /*************************** I2S Extended Instances ***************************/
\r
7624 #define IS_I2S_INSTANCE_EXT(PERIPH) (((INSTANCE) == SPI2) || \
\r
7625 ((INSTANCE) == SPI3) || \
\r
7626 ((INSTANCE) == I2S2ext) || \
\r
7627 ((INSTANCE) == I2S3ext))
\r
7629 /******************************* RNG Instances ********************************/
\r
7630 #define IS_RNG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RNG)
\r
7632 /****************************** RTC Instances *********************************/
\r
7633 #define IS_RTC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RTC)
\r
7635 /******************************** SPI Instances *******************************/
\r
7636 #define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
\r
7637 ((INSTANCE) == SPI2) || \
\r
7638 ((INSTANCE) == SPI3))
\r
7640 /*************************** SPI Extended Instances ***************************/
\r
7641 #define IS_SPI_ALL_INSTANCE_EXT(INSTANCE) (((INSTANCE) == SPI1) || \
\r
7642 ((INSTANCE) == SPI2) || \
\r
7643 ((INSTANCE) == SPI3) || \
\r
7644 ((INSTANCE) == I2S2ext) || \
\r
7645 ((INSTANCE) == I2S3ext))
\r
7647 /****************** TIM Instances : All supported instances *******************/
\r
7648 #define IS_TIM_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
\r
7649 ((INSTANCE) == TIM2) || \
\r
7650 ((INSTANCE) == TIM3) || \
\r
7651 ((INSTANCE) == TIM4) || \
\r
7652 ((INSTANCE) == TIM5) || \
\r
7653 ((INSTANCE) == TIM6) || \
\r
7654 ((INSTANCE) == TIM7) || \
\r
7655 ((INSTANCE) == TIM8) || \
\r
7656 ((INSTANCE) == TIM9) || \
\r
7657 ((INSTANCE) == TIM10) || \
\r
7658 ((INSTANCE) == TIM11) || \
\r
7659 ((INSTANCE) == TIM12) || \
\r
7660 ((INSTANCE) == TIM13) || \
\r
7661 ((INSTANCE) == TIM14))
\r
7663 /************* TIM Instances : at least 1 capture/compare channel *************/
\r
7664 #define IS_TIM_CC1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
\r
7665 ((INSTANCE) == TIM2) || \
\r
7666 ((INSTANCE) == TIM3) || \
\r
7667 ((INSTANCE) == TIM4) || \
\r
7668 ((INSTANCE) == TIM5) || \
\r
7669 ((INSTANCE) == TIM8) || \
\r
7670 ((INSTANCE) == TIM9) || \
\r
7671 ((INSTANCE) == TIM10) || \
\r
7672 ((INSTANCE) == TIM11) || \
\r
7673 ((INSTANCE) == TIM12) || \
\r
7674 ((INSTANCE) == TIM13) || \
\r
7675 ((INSTANCE) == TIM14))
\r
7677 /************ TIM Instances : at least 2 capture/compare channels *************/
\r
7678 #define IS_TIM_CC2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
\r
7679 ((INSTANCE) == TIM2) || \
\r
7680 ((INSTANCE) == TIM3) || \
\r
7681 ((INSTANCE) == TIM4) || \
\r
7682 ((INSTANCE) == TIM5) || \
\r
7683 ((INSTANCE) == TIM8) || \
\r
7684 ((INSTANCE) == TIM9) || \
\r
7685 ((INSTANCE) == TIM12))
\r
7687 /************ TIM Instances : at least 3 capture/compare channels *************/
\r
7688 #define IS_TIM_CC3_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
\r
7689 ((INSTANCE) == TIM2) || \
\r
7690 ((INSTANCE) == TIM3) || \
\r
7691 ((INSTANCE) == TIM4) || \
\r
7692 ((INSTANCE) == TIM5) || \
\r
7693 ((INSTANCE) == TIM8))
\r
7695 /************ TIM Instances : at least 4 capture/compare channels *************/
\r
7696 #define IS_TIM_CC4_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
\r
7697 ((INSTANCE) == TIM2) || \
\r
7698 ((INSTANCE) == TIM3) || \
\r
7699 ((INSTANCE) == TIM4) || \
\r
7700 ((INSTANCE) == TIM5) || \
\r
7701 ((INSTANCE) == TIM8))
\r
7703 /******************** TIM Instances : Advanced-control timers *****************/
\r
7704 #define IS_TIM_ADVANCED_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
\r
7705 ((INSTANCE) == TIM8))
\r
7707 /******************* TIM Instances : Timer input XOR function *****************/
\r
7708 #define IS_TIM_XOR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
\r
7709 ((INSTANCE) == TIM2) || \
\r
7710 ((INSTANCE) == TIM3) || \
\r
7711 ((INSTANCE) == TIM4) || \
\r
7712 ((INSTANCE) == TIM5) || \
\r
7713 ((INSTANCE) == TIM8))
\r
7715 /****************** TIM Instances : DMA requests generation (UDE) *************/
\r
7716 #define IS_TIM_DMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
\r
7717 ((INSTANCE) == TIM2) || \
\r
7718 ((INSTANCE) == TIM3) || \
\r
7719 ((INSTANCE) == TIM4) || \
\r
7720 ((INSTANCE) == TIM5) || \
\r
7721 ((INSTANCE) == TIM6) || \
\r
7722 ((INSTANCE) == TIM7) || \
\r
7723 ((INSTANCE) == TIM8))
\r
7725 /************ TIM Instances : DMA requests generation (CCxDE) *****************/
\r
7726 #define IS_TIM_DMA_CC_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
\r
7727 ((INSTANCE) == TIM2) || \
\r
7728 ((INSTANCE) == TIM3) || \
\r
7729 ((INSTANCE) == TIM4) || \
\r
7730 ((INSTANCE) == TIM5) || \
\r
7731 ((INSTANCE) == TIM8))
\r
7733 /************ TIM Instances : DMA requests generation (COMDE) *****************/
\r
7734 #define IS_TIM_CCDMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
\r
7735 ((INSTANCE) == TIM2) || \
\r
7736 ((INSTANCE) == TIM3) || \
\r
7737 ((INSTANCE) == TIM4) || \
\r
7738 ((INSTANCE) == TIM5) || \
\r
7739 ((INSTANCE) == TIM8))
\r
7741 /******************** TIM Instances : DMA burst feature ***********************/
\r
7742 #define IS_TIM_DMABURST_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
\r
7743 ((INSTANCE) == TIM2) || \
\r
7744 ((INSTANCE) == TIM3) || \
\r
7745 ((INSTANCE) == TIM4) || \
\r
7746 ((INSTANCE) == TIM5) || \
\r
7747 ((INSTANCE) == TIM8))
\r
7749 /****** TIM Instances : master mode available (TIMx_CR2.MMS available )********/
\r
7750 #define IS_TIM_MASTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
\r
7751 ((INSTANCE) == TIM2) || \
\r
7752 ((INSTANCE) == TIM3) || \
\r
7753 ((INSTANCE) == TIM4) || \
\r
7754 ((INSTANCE) == TIM5) || \
\r
7755 ((INSTANCE) == TIM6) || \
\r
7756 ((INSTANCE) == TIM7) || \
\r
7757 ((INSTANCE) == TIM8) || \
\r
7758 ((INSTANCE) == TIM9) || \
\r
7759 ((INSTANCE) == TIM12))
\r
7761 /*********** TIM Instances : Slave mode available (TIMx_SMCR available )*******/
\r
7762 #define IS_TIM_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
\r
7763 ((INSTANCE) == TIM2) || \
\r
7764 ((INSTANCE) == TIM3) || \
\r
7765 ((INSTANCE) == TIM4) || \
\r
7766 ((INSTANCE) == TIM5) || \
\r
7767 ((INSTANCE) == TIM8) || \
\r
7768 ((INSTANCE) == TIM9) || \
\r
7769 ((INSTANCE) == TIM12))
\r
7771 /********************** TIM Instances : 32 bit Counter ************************/
\r
7772 #define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE)(((INSTANCE) == TIM2) || \
\r
7773 ((INSTANCE) == TIM5))
\r
7775 /***************** TIM Instances : external trigger input availabe ************/
\r
7776 #define IS_TIM_ETR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
\r
7777 ((INSTANCE) == TIM2) || \
\r
7778 ((INSTANCE) == TIM3) || \
\r
7779 ((INSTANCE) == TIM4) || \
\r
7780 ((INSTANCE) == TIM5) || \
\r
7781 ((INSTANCE) == TIM8))
\r
7783 /****************** TIM Instances : remapping capability **********************/
\r
7784 #define IS_TIM_REMAP_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
\r
7785 ((INSTANCE) == TIM5) || \
\r
7786 ((INSTANCE) == TIM11))
\r
7788 /******************* TIM Instances : output(s) available **********************/
\r
7789 #define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
\r
7790 ((((INSTANCE) == TIM1) && \
\r
7791 (((CHANNEL) == TIM_CHANNEL_1) || \
\r
7792 ((CHANNEL) == TIM_CHANNEL_2) || \
\r
7793 ((CHANNEL) == TIM_CHANNEL_3) || \
\r
7794 ((CHANNEL) == TIM_CHANNEL_4))) \
\r
7796 (((INSTANCE) == TIM2) && \
\r
7797 (((CHANNEL) == TIM_CHANNEL_1) || \
\r
7798 ((CHANNEL) == TIM_CHANNEL_2) || \
\r
7799 ((CHANNEL) == TIM_CHANNEL_3) || \
\r
7800 ((CHANNEL) == TIM_CHANNEL_4))) \
\r
7802 (((INSTANCE) == TIM3) && \
\r
7803 (((CHANNEL) == TIM_CHANNEL_1) || \
\r
7804 ((CHANNEL) == TIM_CHANNEL_2) || \
\r
7805 ((CHANNEL) == TIM_CHANNEL_3) || \
\r
7806 ((CHANNEL) == TIM_CHANNEL_4))) \
\r
7808 (((INSTANCE) == TIM4) && \
\r
7809 (((CHANNEL) == TIM_CHANNEL_1) || \
\r
7810 ((CHANNEL) == TIM_CHANNEL_2) || \
\r
7811 ((CHANNEL) == TIM_CHANNEL_3) || \
\r
7812 ((CHANNEL) == TIM_CHANNEL_4))) \
\r
7814 (((INSTANCE) == TIM5) && \
\r
7815 (((CHANNEL) == TIM_CHANNEL_1) || \
\r
7816 ((CHANNEL) == TIM_CHANNEL_2) || \
\r
7817 ((CHANNEL) == TIM_CHANNEL_3) || \
\r
7818 ((CHANNEL) == TIM_CHANNEL_4))) \
\r
7820 (((INSTANCE) == TIM8) && \
\r
7821 (((CHANNEL) == TIM_CHANNEL_1) || \
\r
7822 ((CHANNEL) == TIM_CHANNEL_2) || \
\r
7823 ((CHANNEL) == TIM_CHANNEL_3) || \
\r
7824 ((CHANNEL) == TIM_CHANNEL_4))) \
\r
7826 (((INSTANCE) == TIM9) && \
\r
7827 (((CHANNEL) == TIM_CHANNEL_1) || \
\r
7828 ((CHANNEL) == TIM_CHANNEL_2))) \
\r
7830 (((INSTANCE) == TIM10) && \
\r
7831 (((CHANNEL) == TIM_CHANNEL_1))) \
\r
7833 (((INSTANCE) == TIM11) && \
\r
7834 (((CHANNEL) == TIM_CHANNEL_1))) \
\r
7836 (((INSTANCE) == TIM12) && \
\r
7837 (((CHANNEL) == TIM_CHANNEL_1) || \
\r
7838 ((CHANNEL) == TIM_CHANNEL_2))) \
\r
7840 (((INSTANCE) == TIM13) && \
\r
7841 (((CHANNEL) == TIM_CHANNEL_1))) \
\r
7843 (((INSTANCE) == TIM14) && \
\r
7844 (((CHANNEL) == TIM_CHANNEL_1))))
\r
7846 /************ TIM Instances : complementary output(s) available ***************/
\r
7847 #define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) \
\r
7848 ((((INSTANCE) == TIM1) && \
\r
7849 (((CHANNEL) == TIM_CHANNEL_1) || \
\r
7850 ((CHANNEL) == TIM_CHANNEL_2) || \
\r
7851 ((CHANNEL) == TIM_CHANNEL_3))) \
\r
7853 (((INSTANCE) == TIM8) && \
\r
7854 (((CHANNEL) == TIM_CHANNEL_1) || \
\r
7855 ((CHANNEL) == TIM_CHANNEL_2) || \
\r
7856 ((CHANNEL) == TIM_CHANNEL_3))))
\r
7858 /******************** USART Instances : Synchronous mode **********************/
\r
7859 #define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
\r
7860 ((INSTANCE) == USART2) || \
\r
7861 ((INSTANCE) == USART3) || \
\r
7862 ((INSTANCE) == USART6))
\r
7864 /******************** UART Instances : Asynchronous mode **********************/
\r
7865 #define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
\r
7866 ((INSTANCE) == USART2) || \
\r
7867 ((INSTANCE) == USART3) || \
\r
7868 ((INSTANCE) == UART4) || \
\r
7869 ((INSTANCE) == UART5) || \
\r
7870 ((INSTANCE) == USART6))
\r
7872 /****************** UART Instances : Hardware Flow control ********************/
\r
7873 #define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
\r
7874 ((INSTANCE) == USART2) || \
\r
7875 ((INSTANCE) == USART3) || \
\r
7876 ((INSTANCE) == USART6))
\r
7878 /********************* UART Instances : Smard card mode ***********************/
\r
7879 #define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
\r
7880 ((INSTANCE) == USART2) || \
\r
7881 ((INSTANCE) == USART3) || \
\r
7882 ((INSTANCE) == USART6))
\r
7884 /*********************** UART Instances : IRDA mode ***************************/
\r
7885 #define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
\r
7886 ((INSTANCE) == USART2) || \
\r
7887 ((INSTANCE) == USART3) || \
\r
7888 ((INSTANCE) == UART4) || \
\r
7889 ((INSTANCE) == UART5) || \
\r
7890 ((INSTANCE) == USART6))
\r
7892 /****************************** IWDG Instances ********************************/
\r
7893 #define IS_IWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == IWDG)
\r
7895 /****************************** WWDG Instances ********************************/
\r
7896 #define IS_WWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == WWDG)
\r
7911 #ifdef __cplusplus
\r
7913 #endif /* __cplusplus */
\r
7915 #endif /* __STM32F407xx_H */
\r
7919 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
\r
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