2 ******************************************************************************
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3 * @file stm32f4xx_hal_nand.h
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4 * @author MCD Application Team
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6 * @date 18-February-2014
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7 * @brief Header file of NAND HAL module.
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8 ******************************************************************************
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11 * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
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13 * Redistribution and use in source and binary forms, with or without modification,
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14 * are permitted provided that the following conditions are met:
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15 * 1. Redistributions of source code must retain the above copyright notice,
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16 * this list of conditions and the following disclaimer.
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17 * 2. Redistributions in binary form must reproduce the above copyright notice,
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18 * this list of conditions and the following disclaimer in the documentation
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19 * and/or other materials provided with the distribution.
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20 * 3. Neither the name of STMicroelectronics nor the names of its contributors
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21 * may be used to endorse or promote products derived from this software
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22 * without specific prior written permission.
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24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
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28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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35 ******************************************************************************
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38 /* Define to prevent recursive inclusion -------------------------------------*/
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39 #ifndef __STM32F4xx_HAL_NAND_H
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40 #define __STM32F4xx_HAL_NAND_H
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46 /* Includes ------------------------------------------------------------------*/
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47 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx)|| defined(STM32F417xx)
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48 #include "stm32f4xx_ll_fsmc.h"
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49 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */
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51 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx)
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52 #include "stm32f4xx_ll_fmc.h"
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53 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
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55 /** @addtogroup STM32F4xx_HAL_Driver
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59 /** @addtogroup NAND
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63 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
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65 /* Exported typedef ----------------------------------------------------------*/
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66 /* Exported types ------------------------------------------------------------*/
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69 * @brief HAL NAND State structures definition
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73 HAL_NAND_STATE_RESET = 0x00, /*!< NAND not yet initialized or disabled */
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74 HAL_NAND_STATE_READY = 0x01, /*!< NAND initialized and ready for use */
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75 HAL_NAND_STATE_BUSY = 0x02, /*!< NAND internal process is ongoing */
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76 HAL_NAND_STATE_ERROR = 0x03 /*!< NAND error state */
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78 }HAL_NAND_StateTypeDef;
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81 * @brief NAND Memory electronic signature Structure definition
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85 /*<! NAND memory electronic signature maker and device IDs */
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98 * @brief NAND Memory address Structure definition
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102 uint16_t Page; /*!< NAND memory Page address */
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104 uint16_t Zone; /*!< NAND memory Zone address */
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106 uint16_t Block; /*!< NAND memory Block address */
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108 }NAND_AddressTypedef;
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111 * @brief NAND Memory info Structure definition
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115 uint32_t PageSize; /*!< NAND memory page (without spare area) size measured in K. bytes */
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117 uint32_t SpareAreaSize; /*!< NAND memory spare area size measured in K. bytes */
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119 uint32_t BlockSize; /*!< NAND memory block size number of pages */
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121 uint32_t BlockNbr; /*!< NAND memory number of blocks */
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123 uint32_t ZoneSize; /*!< NAND memory zone size measured in number of blocks */
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128 * @brief NAND handle Structure definition
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132 FMC_NAND_TypeDef *Instance; /*!< Register base address */
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134 FMC_NAND_InitTypeDef Init; /*!< NAND device control configuration parameters */
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136 HAL_LockTypeDef Lock; /*!< NAND locking object */
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138 __IO HAL_NAND_StateTypeDef State; /*!< NAND device access state */
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140 NAND_InfoTypeDef Info; /*!< NAND characteristic information structure */
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142 }NAND_HandleTypeDef;
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145 /* Exported constants --------------------------------------------------------*/
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146 /** @defgroup NAND_Exported_Constants
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149 #define NAND_DEVICE1 ((uint32_t)0x70000000)
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150 #define NAND_DEVICE2 ((uint32_t)0x80000000)
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151 #define NAND_WRITE_TIMEOUT ((uint32_t)0x01000000)
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153 #define CMD_AREA ((uint32_t)(1<<16)) /* A16 = CLE high */
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154 #define ADDR_AREA ((uint32_t)(1<<17)) /* A17 = ALE high */
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156 #define NAND_CMD_AREA_A ((uint8_t)0x00)
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157 #define NAND_CMD_AREA_B ((uint8_t)0x01)
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158 #define NAND_CMD_AREA_C ((uint8_t)0x50)
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160 /* NAND memory status */
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161 #define NAND_VALID_ADDRESS ((uint32_t)0x00000100)
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162 #define NAND_INVALID_ADDRESS ((uint32_t)0x00000200)
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163 #define NAND_TIMEOUT_ERROR ((uint32_t)0x00000400)
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164 #define NAND_BUSY ((uint32_t)0x00000000)
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165 #define NAND_ERROR ((uint32_t)0x00000001)
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166 #define NAND_READY ((uint32_t)0x00000040)
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172 /* Exported macro ------------------------------------------------------------*/
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174 * @brief NAND memory address computation.
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175 * @param __ADDRESS__: NAND memory address.
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176 * @param __HANDLE__ : NAND handle.
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177 * @retval NAND Raw address value
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179 #define ARRAY_ADDRESS(__ADDRESS__ , __HANDLE__) ((__ADDRESS__)->Page + (((__ADDRESS__)->Block + (((__ADDRESS__)->Zone) * ((__HANDLE__)->Info.BlockSize)))* ((__HANDLE__)->Info.ZoneSize)))
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182 * @brief NAND memory address cycling.
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183 * @param __ADDRESS__: NAND memory address.
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184 * @retval NAND address cycling value.
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186 #define ADDR_1st_CYCLE(__ADDRESS__) (uint8_t)((__ADDRESS__)& 0xFF) /* 1st addressing cycle */
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187 #define ADDR_2nd_CYCLE(__ADDRESS__) (uint8_t)(((__ADDRESS__)& 0xFF00) >> 8) /* 2nd addressing cycle */
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188 #define ADDR_3rd_CYCLE(__ADDRESS__) (uint8_t)(((__ADDRESS__)& 0xFF0000) >> 16) /* 3rd addressing cycle */
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189 #define ADDR_4th_CYCLE(__ADDRESS__) (uint8_t)(((__ADDRESS__)& 0xFF000000) >> 24) /* 4th addressing cycle */
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191 /* Exported functions --------------------------------------------------------*/
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193 /* Initialization/de-initialization functions **********************************/
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194 HAL_StatusTypeDef HAL_NAND_Init(NAND_HandleTypeDef *hnand, FMC_NAND_PCC_TimingTypeDef *ComSpace_Timing, FMC_NAND_PCC_TimingTypeDef *AttSpace_Timing);
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195 HAL_StatusTypeDef HAL_NAND_DeInit(NAND_HandleTypeDef *hnand);
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196 void HAL_NAND_MspInit(NAND_HandleTypeDef *hnand);
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197 void HAL_NAND_MspDeInit(NAND_HandleTypeDef *hnand);
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198 void HAL_NAND_IRQHandler(NAND_HandleTypeDef *hnand);
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199 void HAL_NAND_ITCallback(NAND_HandleTypeDef *hnand);
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201 /* IO operation functions *****************************************************/
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202 HAL_StatusTypeDef HAL_NAND_Read_ID(NAND_HandleTypeDef *hnand, NAND_IDTypeDef *pNAND_ID);
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203 HAL_StatusTypeDef HAL_NAND_Reset(NAND_HandleTypeDef *hnand);
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204 HAL_StatusTypeDef HAL_NAND_Read_Page(NAND_HandleTypeDef *hnand, NAND_AddressTypedef *pAddress, uint8_t *pBuffer, uint32_t NumPageToRead);
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205 HAL_StatusTypeDef HAL_NAND_Write_Page(NAND_HandleTypeDef *hnand, NAND_AddressTypedef *pAddress, uint8_t *pBuffer, uint32_t NumPageToWrite);
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206 HAL_StatusTypeDef HAL_NAND_Read_SpareArea(NAND_HandleTypeDef *hnand, NAND_AddressTypedef *pAddress, uint8_t *pBuffer, uint32_t NumSpareAreaToRead);
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207 HAL_StatusTypeDef HAL_NAND_Write_SpareArea(NAND_HandleTypeDef *hnand, NAND_AddressTypedef *pAddress, uint8_t *pBuffer, uint32_t NumSpareAreaTowrite);
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208 HAL_StatusTypeDef HAL_NAND_Erase_Block(NAND_HandleTypeDef *hnand, NAND_AddressTypedef *pAddress);
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209 uint32_t HAL_NAND_Read_Status(NAND_HandleTypeDef *hnand);
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210 uint32_t HAL_NAND_Address_Inc(NAND_HandleTypeDef *hnand, NAND_AddressTypedef *pAddress);
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212 /* NAND Control functions ******************************************************/
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213 HAL_StatusTypeDef HAL_NAND_ECC_Enable(NAND_HandleTypeDef *hnand);
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214 HAL_StatusTypeDef HAL_NAND_ECC_Disable(NAND_HandleTypeDef *hnand);
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215 HAL_StatusTypeDef HAL_NAND_GetECC(NAND_HandleTypeDef *hnand, uint32_t *ECCval, uint32_t Timeout);
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217 /* NAND State functions *********************************************************/
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218 HAL_NAND_StateTypeDef HAL_NAND_GetState(NAND_HandleTypeDef *hnand);
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219 uint32_t HAL_NAND_Read_Status(NAND_HandleTypeDef *hnand);
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221 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
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234 #endif /* __STM32F4xx_HAL_NAND_H */
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236 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
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