2 ******************************************************************************
\r
3 * @file stm32f4xx_ll_sdmmc.h
\r
4 * @author MCD Application Team
\r
6 * @date 18-February-2014
\r
7 * @brief Header file of SDMMC HAL module.
\r
8 ******************************************************************************
\r
11 * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
\r
13 * Redistribution and use in source and binary forms, with or without modification,
\r
14 * are permitted provided that the following conditions are met:
\r
15 * 1. Redistributions of source code must retain the above copyright notice,
\r
16 * this list of conditions and the following disclaimer.
\r
17 * 2. Redistributions in binary form must reproduce the above copyright notice,
\r
18 * this list of conditions and the following disclaimer in the documentation
\r
19 * and/or other materials provided with the distribution.
\r
20 * 3. Neither the name of STMicroelectronics nor the names of its contributors
\r
21 * may be used to endorse or promote products derived from this software
\r
22 * without specific prior written permission.
\r
24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
\r
25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
\r
26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
\r
27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
\r
28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
\r
29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
\r
30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
\r
31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
\r
32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
\r
33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
\r
35 ******************************************************************************
\r
38 /* Define to prevent recursive inclusion -------------------------------------*/
\r
39 #ifndef __STM32F4xx_LL_SDMMC_H
\r
40 #define __STM32F4xx_LL_SDMMC_H
\r
46 /* Includes ------------------------------------------------------------------*/
\r
47 #include "stm32f4xx_hal_def.h"
\r
49 /** @addtogroup STM32F4xx_Driver
\r
53 /** @addtogroup SDMMC
\r
57 /* Exported types ------------------------------------------------------------*/
\r
60 * @brief SDMMC Configuration Structure definition
\r
64 uint32_t ClockEdge; /*!< Specifies the clock transition on which the bit capture is made.
\r
65 This parameter can be a value of @ref SDIO_Clock_Edge */
\r
67 uint32_t ClockBypass; /*!< Specifies whether the SDIO Clock divider bypass is
\r
68 enabled or disabled.
\r
69 This parameter can be a value of @ref SDIO_Clock_Bypass */
\r
71 uint32_t ClockPowerSave; /*!< Specifies whether SDIO Clock output is enabled or
\r
72 disabled when the bus is idle.
\r
73 This parameter can be a value of @ref SDIO_Clock_Power_Save */
\r
75 uint32_t BusWide; /*!< Specifies the SDIO bus width.
\r
76 This parameter can be a value of @ref SDIO_Bus_Wide */
\r
78 uint32_t HardwareFlowControl; /*!< Specifies whether the SDIO hardware flow control is enabled or disabled.
\r
79 This parameter can be a value of @ref SDIO_Hardware_Flow_Control */
\r
81 uint32_t ClockDiv; /*!< Specifies the clock frequency of the SDIO controller.
\r
82 This parameter can be a value between Min_Data = 0 and Max_Data = 255 */
\r
88 * @brief SDIO Command Control structure
\r
92 uint32_t Argument; /*!< Specifies the SDIO command argument which is sent
\r
93 to a card as part of a command message. If a command
\r
94 contains an argument, it must be loaded into this register
\r
95 before writing the command to the command register. */
\r
97 uint32_t CmdIndex; /*!< Specifies the SDIO command index. It must be Min_Data = 0 and
\r
100 uint32_t Response; /*!< Specifies the SDIO response type.
\r
101 This parameter can be a value of @ref SDIO_Response_Type */
\r
103 uint32_t WaitForInterrupt; /*!< Specifies whether SDIO wait for interrupt request is
\r
104 enabled or disabled.
\r
105 This parameter can be a value of @ref SDIO_Wait_Interrupt_State */
\r
107 uint32_t CPSM; /*!< Specifies whether SDIO Command path state machine (CPSM)
\r
108 is enabled or disabled.
\r
109 This parameter can be a value of @ref SDIO_CPSM_State */
\r
110 }SDIO_CmdInitTypeDef;
\r
114 * @brief SDIO Data Control structure
\r
118 uint32_t DataTimeOut; /*!< Specifies the data timeout period in card bus clock periods. */
\r
120 uint32_t DataLength; /*!< Specifies the number of data bytes to be transferred. */
\r
122 uint32_t DataBlockSize; /*!< Specifies the data block size for block transfer.
\r
123 This parameter can be a value of @ref SDIO_Data_Block_Size */
\r
125 uint32_t TransferDir; /*!< Specifies the data transfer direction, whether the transfer
\r
126 is a read or write.
\r
127 This parameter can be a value of @ref SDIO_Transfer_Direction */
\r
129 uint32_t TransferMode; /*!< Specifies whether data transfer is in stream or block mode.
\r
130 This parameter can be a value of @ref SDIO_Transfer_Type */
\r
132 uint32_t DPSM; /*!< Specifies whether SDIO Data path state machine (DPSM)
\r
133 is enabled or disabled.
\r
134 This parameter can be a value of @ref SDIO_DPSM_State */
\r
135 }SDIO_DataInitTypeDef;
\r
137 /* Exported constants --------------------------------------------------------*/
\r
139 /** @defgroup SDIO_Exported_Constants
\r
143 /** @defgroup SDIO_Clock_Edge
\r
146 #define SDIO_CLOCK_EDGE_RISING ((uint32_t)0x00000000)
\r
147 #define SDIO_CLOCK_EDGE_FALLING ((uint32_t)0x00002000)
\r
149 #define IS_SDIO_CLOCK_EDGE(EDGE) (((EDGE) == SDIO_CLOCK_EDGE_RISING) || \
\r
150 ((EDGE) == SDIO_CLOCK_EDGE_FALLING))
\r
155 /** @defgroup SDIO_Clock_Bypass
\r
158 #define SDIO_CLOCK_BYPASS_DISABLE ((uint32_t)0x00000000)
\r
159 #define SDIO_CLOCK_BYPASS_ENABLE ((uint32_t)0x00000400)
\r
161 #define IS_SDIO_CLOCK_BYPASS(BYPASS) (((BYPASS) == SDIO_CLOCK_BYPASS_DISABLE) || \
\r
162 ((BYPASS) == SDIO_CLOCK_BYPASS_ENABLE))
\r
167 /** @defgroup SDIO_Clock_Power_Save
\r
170 #define SDIO_CLOCK_POWER_SAVE_DISABLE ((uint32_t)0x00000000)
\r
171 #define SDIO_CLOCK_POWER_SAVE_ENABLE ((uint32_t)0x00000200)
\r
173 #define IS_SDIO_CLOCK_POWER_SAVE(SAVE) (((SAVE) == SDIO_CLOCK_POWER_SAVE_DISABLE) || \
\r
174 ((SAVE) == SDIO_CLOCK_POWER_SAVE_ENABLE))
\r
179 /** @defgroup SDIO_Bus_Wide
\r
182 #define SDIO_BUS_WIDE_1B ((uint32_t)0x00000000)
\r
183 #define SDIO_BUS_WIDE_4B ((uint32_t)0x00000800)
\r
184 #define SDIO_BUS_WIDE_8B ((uint32_t)0x00001000)
\r
186 #define IS_SDIO_BUS_WIDE(WIDE) (((WIDE) == SDIO_BUS_WIDE_1B) || \
\r
187 ((WIDE) == SDIO_BUS_WIDE_4B) || \
\r
188 ((WIDE) == SDIO_BUS_WIDE_8B))
\r
193 /** @defgroup SDIO_Hardware_Flow_Control
\r
196 #define SDIO_HARDWARE_FLOW_CONTROL_DISABLE ((uint32_t)0x00000000)
\r
197 #define SDIO_HARDWARE_FLOW_CONTROL_ENABLE ((uint32_t)0x00004000)
\r
199 #define IS_SDIO_HARDWARE_FLOW_CONTROL(CONTROL) (((CONTROL) == SDIO_HARDWARE_FLOW_CONTROL_DISABLE) || \
\r
200 ((CONTROL) == SDIO_HARDWARE_FLOW_CONTROL_ENABLE))
\r
205 /** @defgroup SDIO_Clock_Division
\r
208 #define IS_SDIO_CLKDIV(DIV) ((DIV) <= 0xFF)
\r
217 /** @defgroup SDIO_Command_Index
\r
220 #define IS_SDIO_CMD_INDEX(INDEX) ((INDEX) < 0x40)
\r
225 /** @defgroup SDIO_Response_Type
\r
228 #define SDIO_RESPONSE_NO ((uint32_t)0x00000000)
\r
229 #define SDIO_RESPONSE_SHORT ((uint32_t)0x00000040)
\r
230 #define SDIO_RESPONSE_LONG ((uint32_t)0x000000C0)
\r
232 #define IS_SDIO_RESPONSE(RESPONSE) (((RESPONSE) == SDIO_RESPONSE_NO) || \
\r
233 ((RESPONSE) == SDIO_RESPONSE_SHORT) || \
\r
234 ((RESPONSE) == SDIO_RESPONSE_LONG))
\r
239 /** @defgroup SDIO_Wait_Interrupt_State
\r
242 #define SDIO_WAIT_NO ((uint32_t)0x00000000)
\r
243 #define SDIO_WAIT_IT ((uint32_t)0x00000100)
\r
244 #define SDIO_WAIT_PEND ((uint32_t)0x00000200)
\r
246 #define IS_SDIO_WAIT(WAIT) (((WAIT) == SDIO_WAIT_NO) || \
\r
247 ((WAIT) == SDIO_WAIT_IT) || \
\r
248 ((WAIT) == SDIO_WAIT_PEND))
\r
253 /** @defgroup SDIO_CPSM_State
\r
256 #define SDIO_CPSM_DISABLE ((uint32_t)0x00000000)
\r
257 #define SDIO_CPSM_ENABLE ((uint32_t)0x00000400)
\r
259 #define IS_SDIO_CPSM(CPSM) (((CPSM) == SDIO_CPSM_DISABLE) || \
\r
260 ((CPSM) == SDIO_CPSM_ENABLE))
\r
265 /** @defgroup SDIO_Response_Registers
\r
268 #define SDIO_RESP1 ((uint32_t)0x00000000)
\r
269 #define SDIO_RESP2 ((uint32_t)0x00000004)
\r
270 #define SDIO_RESP3 ((uint32_t)0x00000008)
\r
271 #define SDIO_RESP4 ((uint32_t)0x0000000C)
\r
273 #define IS_SDIO_RESP(RESP) (((RESP) == SDIO_RESP1) || \
\r
274 ((RESP) == SDIO_RESP2) || \
\r
275 ((RESP) == SDIO_RESP3) || \
\r
276 ((RESP) == SDIO_RESP4))
\r
281 /** @defgroup SDIO_Data_Length
\r
284 #define IS_SDIO_DATA_LENGTH(LENGTH) ((LENGTH) <= 0x01FFFFFF)
\r
289 /** @defgroup SDIO_Data_Block_Size
\r
292 #define SDIO_DATABLOCK_SIZE_1B ((uint32_t)0x00000000)
\r
293 #define SDIO_DATABLOCK_SIZE_2B ((uint32_t)0x00000010)
\r
294 #define SDIO_DATABLOCK_SIZE_4B ((uint32_t)0x00000020)
\r
295 #define SDIO_DATABLOCK_SIZE_8B ((uint32_t)0x00000030)
\r
296 #define SDIO_DATABLOCK_SIZE_16B ((uint32_t)0x00000040)
\r
297 #define SDIO_DATABLOCK_SIZE_32B ((uint32_t)0x00000050)
\r
298 #define SDIO_DATABLOCK_SIZE_64B ((uint32_t)0x00000060)
\r
299 #define SDIO_DATABLOCK_SIZE_128B ((uint32_t)0x00000070)
\r
300 #define SDIO_DATABLOCK_SIZE_256B ((uint32_t)0x00000080)
\r
301 #define SDIO_DATABLOCK_SIZE_512B ((uint32_t)0x00000090)
\r
302 #define SDIO_DATABLOCK_SIZE_1024B ((uint32_t)0x000000A0)
\r
303 #define SDIO_DATABLOCK_SIZE_2048B ((uint32_t)0x000000B0)
\r
304 #define SDIO_DATABLOCK_SIZE_4096B ((uint32_t)0x000000C0)
\r
305 #define SDIO_DATABLOCK_SIZE_8192B ((uint32_t)0x000000D0)
\r
306 #define SDIO_DATABLOCK_SIZE_16384B ((uint32_t)0x000000E0)
\r
308 #define IS_SDIO_BLOCK_SIZE(SIZE) (((SIZE) == SDIO_DATABLOCK_SIZE_1B) || \
\r
309 ((SIZE) == SDIO_DATABLOCK_SIZE_2B) || \
\r
310 ((SIZE) == SDIO_DATABLOCK_SIZE_4B) || \
\r
311 ((SIZE) == SDIO_DATABLOCK_SIZE_8B) || \
\r
312 ((SIZE) == SDIO_DATABLOCK_SIZE_16B) || \
\r
313 ((SIZE) == SDIO_DATABLOCK_SIZE_32B) || \
\r
314 ((SIZE) == SDIO_DATABLOCK_SIZE_64B) || \
\r
315 ((SIZE) == SDIO_DATABLOCK_SIZE_128B) || \
\r
316 ((SIZE) == SDIO_DATABLOCK_SIZE_256B) || \
\r
317 ((SIZE) == SDIO_DATABLOCK_SIZE_512B) || \
\r
318 ((SIZE) == SDIO_DATABLOCK_SIZE_1024B) || \
\r
319 ((SIZE) == SDIO_DATABLOCK_SIZE_2048B) || \
\r
320 ((SIZE) == SDIO_DATABLOCK_SIZE_4096B) || \
\r
321 ((SIZE) == SDIO_DATABLOCK_SIZE_8192B) || \
\r
322 ((SIZE) == SDIO_DATABLOCK_SIZE_16384B))
\r
327 /** @defgroup SDIO_Transfer_Direction
\r
330 #define SDIO_TRANSFER_DIR_TO_CARD ((uint32_t)0x00000000)
\r
331 #define SDIO_TRANSFER_DIR_TO_SDIO ((uint32_t)0x00000002)
\r
333 #define IS_SDIO_TRANSFER_DIR(DIR) (((DIR) == SDIO_TRANSFER_DIR_TO_CARD) || \
\r
334 ((DIR) == SDIO_TRANSFER_DIR_TO_SDIO))
\r
339 /** @defgroup SDIO_Transfer_Type
\r
342 #define SDIO_TRANSFER_MODE_BLOCK ((uint32_t)0x00000000)
\r
343 #define SDIO_TRANSFER_MODE_STREAM ((uint32_t)0x00000004)
\r
345 #define IS_SDIO_TRANSFER_MODE(MODE) (((MODE) == SDIO_TRANSFER_MODE_BLOCK) || \
\r
346 ((MODE) == SDIO_TRANSFER_MODE_STREAM))
\r
351 /** @defgroup SDIO_DPSM_State
\r
354 #define SDIO_DPSM_DISABLE ((uint32_t)0x00000000)
\r
355 #define SDIO_DPSM_ENABLE ((uint32_t)0x00000001)
\r
357 #define IS_SDIO_DPSM(DPSM) (((DPSM) == SDIO_DPSM_DISABLE) ||\
\r
358 ((DPSM) == SDIO_DPSM_ENABLE))
\r
363 /** @defgroup SDIO_Read_Wait_Mode
\r
366 #define SDIO_READ_WAIT_MODE_CLK ((uint32_t)0x00000000)
\r
367 #define SDIO_READ_WAIT_MODE_DATA2 ((uint32_t)0x00000001)
\r
369 #define IS_SDIO_READWAIT_MODE(MODE) (((MODE) == SDIO_READ_WAIT_MODE_CLK) || \
\r
370 ((MODE) == SDIO_READ_WAIT_MODE_DATA2))
\r
375 /** @defgroup SDIO_Interrupt_sources
\r
378 #define SDIO_IT_CCRCFAIL ((uint32_t)0x00000001)
\r
379 #define SDIO_IT_DCRCFAIL ((uint32_t)0x00000002)
\r
380 #define SDIO_IT_CTIMEOUT ((uint32_t)0x00000004)
\r
381 #define SDIO_IT_DTIMEOUT ((uint32_t)0x00000008)
\r
382 #define SDIO_IT_TXUNDERR ((uint32_t)0x00000010)
\r
383 #define SDIO_IT_RXOVERR ((uint32_t)0x00000020)
\r
384 #define SDIO_IT_CMDREND ((uint32_t)0x00000040)
\r
385 #define SDIO_IT_CMDSENT ((uint32_t)0x00000080)
\r
386 #define SDIO_IT_DATAEND ((uint32_t)0x00000100)
\r
387 #define SDIO_IT_STBITERR ((uint32_t)0x00000200)
\r
388 #define SDIO_IT_DBCKEND ((uint32_t)0x00000400)
\r
389 #define SDIO_IT_CMDACT ((uint32_t)0x00000800)
\r
390 #define SDIO_IT_TXACT ((uint32_t)0x00001000)
\r
391 #define SDIO_IT_RXACT ((uint32_t)0x00002000)
\r
392 #define SDIO_IT_TXFIFOHE ((uint32_t)0x00004000)
\r
393 #define SDIO_IT_RXFIFOHF ((uint32_t)0x00008000)
\r
394 #define SDIO_IT_TXFIFOF ((uint32_t)0x00010000)
\r
395 #define SDIO_IT_RXFIFOF ((uint32_t)0x00020000)
\r
396 #define SDIO_IT_TXFIFOE ((uint32_t)0x00040000)
\r
397 #define SDIO_IT_RXFIFOE ((uint32_t)0x00080000)
\r
398 #define SDIO_IT_TXDAVL ((uint32_t)0x00100000)
\r
399 #define SDIO_IT_RXDAVL ((uint32_t)0x00200000)
\r
400 #define SDIO_IT_SDIOIT ((uint32_t)0x00400000)
\r
401 #define SDIO_IT_CEATAEND ((uint32_t)0x00800000)
\r
403 #define IS_SDIO_IT(IT) ((((IT) & (uint32_t)0xFF000000) == 0x00) && ((IT) != (uint32_t)0x00))
\r
408 /** @defgroup SDIO_Flags
\r
411 #define SDIO_FLAG_CCRCFAIL ((uint32_t)0x00000001)
\r
412 #define SDIO_FLAG_DCRCFAIL ((uint32_t)0x00000002)
\r
413 #define SDIO_FLAG_CTIMEOUT ((uint32_t)0x00000004)
\r
414 #define SDIO_FLAG_DTIMEOUT ((uint32_t)0x00000008)
\r
415 #define SDIO_FLAG_TXUNDERR ((uint32_t)0x00000010)
\r
416 #define SDIO_FLAG_RXOVERR ((uint32_t)0x00000020)
\r
417 #define SDIO_FLAG_CMDREND ((uint32_t)0x00000040)
\r
418 #define SDIO_FLAG_CMDSENT ((uint32_t)0x00000080)
\r
419 #define SDIO_FLAG_DATAEND ((uint32_t)0x00000100)
\r
420 #define SDIO_FLAG_STBITERR ((uint32_t)0x00000200)
\r
421 #define SDIO_FLAG_DBCKEND ((uint32_t)0x00000400)
\r
422 #define SDIO_FLAG_CMDACT ((uint32_t)0x00000800)
\r
423 #define SDIO_FLAG_TXACT ((uint32_t)0x00001000)
\r
424 #define SDIO_FLAG_RXACT ((uint32_t)0x00002000)
\r
425 #define SDIO_FLAG_TXFIFOHE ((uint32_t)0x00004000)
\r
426 #define SDIO_FLAG_RXFIFOHF ((uint32_t)0x00008000)
\r
427 #define SDIO_FLAG_TXFIFOF ((uint32_t)0x00010000)
\r
428 #define SDIO_FLAG_RXFIFOF ((uint32_t)0x00020000)
\r
429 #define SDIO_FLAG_TXFIFOE ((uint32_t)0x00040000)
\r
430 #define SDIO_FLAG_RXFIFOE ((uint32_t)0x00080000)
\r
431 #define SDIO_FLAG_TXDAVL ((uint32_t)0x00100000)
\r
432 #define SDIO_FLAG_RXDAVL ((uint32_t)0x00200000)
\r
433 #define SDIO_FLAG_SDIOIT ((uint32_t)0x00400000)
\r
434 #define SDIO_FLAG_CEATAEND ((uint32_t)0x00800000)
\r
436 #define IS_SDIO_FLAG(FLAG) (((FLAG) == SDIO_FLAG_CCRCFAIL) || \
\r
437 ((FLAG) == SDIO_FLAG_DCRCFAIL) || \
\r
438 ((FLAG) == SDIO_FLAG_CTIMEOUT) || \
\r
439 ((FLAG) == SDIO_FLAG_DTIMEOUT) || \
\r
440 ((FLAG) == SDIO_FLAG_TXUNDERR) || \
\r
441 ((FLAG) == SDIO_FLAG_RXOVERR) || \
\r
442 ((FLAG) == SDIO_FLAG_CMDREND) || \
\r
443 ((FLAG) == SDIO_FLAG_CMDSENT) || \
\r
444 ((FLAG) == SDIO_FLAG_DATAEND) || \
\r
445 ((FLAG) == SDIO_FLAG_STBITERR) || \
\r
446 ((FLAG) == SDIO_FLAG_DBCKEND) || \
\r
447 ((FLAG) == SDIO_FLAG_CMDACT) || \
\r
448 ((FLAG) == SDIO_FLAG_TXACT) || \
\r
449 ((FLAG) == SDIO_FLAG_RXACT) || \
\r
450 ((FLAG) == SDIO_FLAG_TXFIFOHE) || \
\r
451 ((FLAG) == SDIO_FLAG_RXFIFOHF) || \
\r
452 ((FLAG) == SDIO_FLAG_TXFIFOF) || \
\r
453 ((FLAG) == SDIO_FLAG_RXFIFOF) || \
\r
454 ((FLAG) == SDIO_FLAG_TXFIFOE) || \
\r
455 ((FLAG) == SDIO_FLAG_RXFIFOE) || \
\r
456 ((FLAG) == SDIO_FLAG_TXDAVL) || \
\r
457 ((FLAG) == SDIO_FLAG_RXDAVL) || \
\r
458 ((FLAG) == SDIO_FLAG_SDIOIT) || \
\r
459 ((FLAG) == SDIO_FLAG_CEATAEND))
\r
461 #define IS_SDIO_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0xFF3FF800) == 0x00) && ((FLAG) != (uint32_t)0x00))
\r
463 #define IS_SDIO_GET_IT(IT) (((IT) == SDIO_IT_CCRCFAIL) || \
\r
464 ((IT) == SDIO_IT_DCRCFAIL) || \
\r
465 ((IT) == SDIO_IT_CTIMEOUT) || \
\r
466 ((IT) == SDIO_IT_DTIMEOUT) || \
\r
467 ((IT) == SDIO_IT_TXUNDERR) || \
\r
468 ((IT) == SDIO_IT_RXOVERR) || \
\r
469 ((IT) == SDIO_IT_CMDREND) || \
\r
470 ((IT) == SDIO_IT_CMDSENT) || \
\r
471 ((IT) == SDIO_IT_DATAEND) || \
\r
472 ((IT) == SDIO_IT_STBITERR) || \
\r
473 ((IT) == SDIO_IT_DBCKEND) || \
\r
474 ((IT) == SDIO_IT_CMDACT) || \
\r
475 ((IT) == SDIO_IT_TXACT) || \
\r
476 ((IT) == SDIO_IT_RXACT) || \
\r
477 ((IT) == SDIO_IT_TXFIFOHE) || \
\r
478 ((IT) == SDIO_IT_RXFIFOHF) || \
\r
479 ((IT) == SDIO_IT_TXFIFOF) || \
\r
480 ((IT) == SDIO_IT_RXFIFOF) || \
\r
481 ((IT) == SDIO_IT_TXFIFOE) || \
\r
482 ((IT) == SDIO_IT_RXFIFOE) || \
\r
483 ((IT) == SDIO_IT_TXDAVL) || \
\r
484 ((IT) == SDIO_IT_RXDAVL) || \
\r
485 ((IT) == SDIO_IT_SDIOIT) || \
\r
486 ((IT) == SDIO_IT_CEATAEND))
\r
488 #define IS_SDIO_CLEAR_IT(IT) ((((IT) & (uint32_t)0xFF3FF800) == 0x00) && ((IT) != (uint32_t)0x00))
\r
495 /** @defgroup SDIO_Instance_definition
\r
498 #define IS_SDIO_ALL_INSTANCE(INSTANCE) ((INSTANCE) == SDIO)
\r
504 /* Exported macro ------------------------------------------------------------*/
\r
505 /* ------------ SDIO registers bit address in the alias region -------------- */
\r
506 #define SDIO_OFFSET (SDIO_BASE - PERIPH_BASE)
\r
508 /* --- CLKCR Register ---*/
\r
509 /* Alias word address of CLKEN bit */
\r
510 #define CLKCR_OFFSET (SDIO_OFFSET + 0x04)
\r
511 #define CLKEN_BitNumber 0x08
\r
512 #define CLKCR_CLKEN_BB (PERIPH_BB_BASE + (CLKCR_OFFSET * 32) + (CLKEN_BitNumber * 4))
\r
514 /* --- CMD Register ---*/
\r
515 /* Alias word address of SDIOSUSPEND bit */
\r
516 #define CMD_OFFSET (SDIO_OFFSET + 0x0C)
\r
517 #define SDIOSUSPEND_BitNumber 0x0B
\r
518 #define CMD_SDIOSUSPEND_BB (PERIPH_BB_BASE + (CMD_OFFSET * 32) + (SDIOSUSPEND_BitNumber * 4))
\r
520 /* Alias word address of ENCMDCOMPL bit */
\r
521 #define ENCMDCOMPL_BitNumber 0x0C
\r
522 #define CMD_ENCMDCOMPL_BB (PERIPH_BB_BASE + (CMD_OFFSET * 32) + (ENCMDCOMPL_BitNumber * 4))
\r
524 /* Alias word address of NIEN bit */
\r
525 #define NIEN_BitNumber 0x0D
\r
526 #define CMD_NIEN_BB (PERIPH_BB_BASE + (CMD_OFFSET * 32) + (NIEN_BitNumber * 4))
\r
528 /* Alias word address of ATACMD bit */
\r
529 #define ATACMD_BitNumber 0x0E
\r
530 #define CMD_ATACMD_BB (PERIPH_BB_BASE + (CMD_OFFSET * 32) + (ATACMD_BitNumber * 4))
\r
532 /* --- DCTRL Register ---*/
\r
533 /* Alias word address of DMAEN bit */
\r
534 #define DCTRL_OFFSET (SDIO_OFFSET + 0x2C)
\r
535 #define DMAEN_BitNumber 0x03
\r
536 #define DCTRL_DMAEN_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (DMAEN_BitNumber * 4))
\r
538 /* Alias word address of RWSTART bit */
\r
539 #define RWSTART_BitNumber 0x08
\r
540 #define DCTRL_RWSTART_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (RWSTART_BitNumber * 4))
\r
542 /* Alias word address of RWSTOP bit */
\r
543 #define RWSTOP_BitNumber 0x09
\r
544 #define DCTRL_RWSTOP_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (RWSTOP_BitNumber * 4))
\r
546 /* Alias word address of RWMOD bit */
\r
547 #define RWMOD_BitNumber 0x0A
\r
548 #define DCTRL_RWMOD_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (RWMOD_BitNumber * 4))
\r
550 /* Alias word address of SDIOEN bit */
\r
551 #define SDIOEN_BitNumber 0x0B
\r
552 #define DCTRL_SDIOEN_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (SDIOEN_BitNumber * 4))
\r
554 /* ---------------------- SDIO registers bit mask --------------------------- */
\r
555 /* --- CLKCR Register ---*/
\r
556 /* CLKCR register clear mask */
\r
557 #define CLKCR_CLEAR_MASK ((uint32_t)0xFFFF8100)
\r
559 /* --- PWRCTRL Register ---*/
\r
560 /* SDIO PWRCTRL Mask */
\r
561 #define PWR_PWRCTRL_MASK ((uint32_t)0xFFFFFFFC)
\r
563 /* --- DCTRL Register ---*/
\r
564 /* SDIO DCTRL Clear Mask */
\r
565 #define DCTRL_CLEAR_MASK ((uint32_t)0xFFFFFF08)
\r
567 /* --- CMD Register ---*/
\r
568 /* CMD Register clear mask */
\r
569 #define CMD_CLEAR_MASK ((uint32_t)0xFFFFF800)
\r
571 /* SDIO RESP Registers Address */
\r
572 #define SDIO_RESP_ADDR ((uint32_t)(SDIO_BASE + 0x14))
\r
574 /* SD FLASH SDIO Interface */
\r
575 #define SDIO_FIFO_ADDRESS ((uint32_t)0x40012C80)
\r
577 /* SDIO Intialization Frequency (400KHz max) */
\r
578 #define SDIO_INIT_CLK_DIV ((uint8_t)0x76)
\r
580 /* SDIO Data Transfer Frequency (25MHz max) */
\r
581 #define SDIO_TRANSFER_CLK_DIV ((uint8_t)0x0)
\r
583 /** @defgroup SDIO_Interrupt_Clock
\r
584 * @brief macros to handle interrupts and specific clock configurations
\r
589 * @brief Enable the SDIO device.
\r
593 #define __SDIO_ENABLE() (*(__IO uint32_t *)CLKCR_CLKEN_BB = ENABLE)
\r
596 * @brief Disable the SDIO device.
\r
600 #define __SDIO_DISABLE() (*(__IO uint32_t *)CLKCR_CLKEN_BB = DISABLE)
\r
603 * @brief Enable the SDIO DMA transfer.
\r
607 #define __SDIO_DMA_ENABLE() (*(__IO uint32_t *)DCTRL_DMAEN_BB = ENABLE)
\r
610 * @brief Disable the SDIO DMA transfer.
\r
614 #define __SDIO_DMA_DISABLE() (*(__IO uint32_t *)DCTRL_DMAEN_BB = DISABLE)
\r
617 * @brief Enable the SDIO device interrupt.
\r
618 * @param __INSTANCE__ : Pointer to SDIO register base
\r
619 * @param __INTERRUPT__ : specifies the SDIO interrupt sources to be enabled.
\r
620 * This parameter can be one or a combination of the following values:
\r
621 * @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
\r
622 * @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
\r
623 * @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt
\r
624 * @arg SDIO_IT_DTIMEOUT: Data timeout interrupt
\r
625 * @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt
\r
626 * @arg SDIO_IT_RXOVERR: Received FIFO overrun error interrupt
\r
627 * @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt
\r
628 * @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt
\r
629 * @arg SDIO_IT_DATAEND: Data end (data counter, SDIDCOUNT, is zero) interrupt
\r
630 * @arg SDIO_IT_STBITERR: Start bit not detected on all data signals in wide
\r
631 * bus mode interrupt
\r
632 * @arg SDIO_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt
\r
633 * @arg SDIO_IT_CMDACT: Command transfer in progress interrupt
\r
634 * @arg SDIO_IT_TXACT: Data transmit in progress interrupt
\r
635 * @arg SDIO_IT_RXACT: Data receive in progress interrupt
\r
636 * @arg SDIO_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt
\r
637 * @arg SDIO_IT_RXFIFOHF: Receive FIFO Half Full interrupt
\r
638 * @arg SDIO_IT_TXFIFOF: Transmit FIFO full interrupt
\r
639 * @arg SDIO_IT_RXFIFOF: Receive FIFO full interrupt
\r
640 * @arg SDIO_IT_TXFIFOE: Transmit FIFO empty interrupt
\r
641 * @arg SDIO_IT_RXFIFOE: Receive FIFO empty interrupt
\r
642 * @arg SDIO_IT_TXDAVL: Data available in transmit FIFO interrupt
\r
643 * @arg SDIO_IT_RXDAVL: Data available in receive FIFO interrupt
\r
644 * @arg SDIO_IT_SDIOIT: SD I/O interrupt received interrupt
\r
645 * @arg SDIO_IT_CEATAEND: CE-ATA command completion signal received for CMD61 interrupt
\r
648 #define __SDIO_ENABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->MASK |= (__INTERRUPT__))
\r
651 * @brief Disable the SDIO device interrupt.
\r
652 * @param __INSTANCE__ : Pointer to SDIO register base
\r
653 * @param __INTERRUPT__ : specifies the SDIO interrupt sources to be disabled.
\r
654 * This parameter can be one or a combination of the following values:
\r
655 * @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
\r
656 * @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
\r
657 * @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt
\r
658 * @arg SDIO_IT_DTIMEOUT: Data timeout interrupt
\r
659 * @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt
\r
660 * @arg SDIO_IT_RXOVERR: Received FIFO overrun error interrupt
\r
661 * @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt
\r
662 * @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt
\r
663 * @arg SDIO_IT_DATAEND: Data end (data counter, SDIDCOUNT, is zero) interrupt
\r
664 * @arg SDIO_IT_STBITERR: Start bit not detected on all data signals in wide
\r
665 * bus mode interrupt
\r
666 * @arg SDIO_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt
\r
667 * @arg SDIO_IT_CMDACT: Command transfer in progress interrupt
\r
668 * @arg SDIO_IT_TXACT: Data transmit in progress interrupt
\r
669 * @arg SDIO_IT_RXACT: Data receive in progress interrupt
\r
670 * @arg SDIO_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt
\r
671 * @arg SDIO_IT_RXFIFOHF: Receive FIFO Half Full interrupt
\r
672 * @arg SDIO_IT_TXFIFOF: Transmit FIFO full interrupt
\r
673 * @arg SDIO_IT_RXFIFOF: Receive FIFO full interrupt
\r
674 * @arg SDIO_IT_TXFIFOE: Transmit FIFO empty interrupt
\r
675 * @arg SDIO_IT_RXFIFOE: Receive FIFO empty interrupt
\r
676 * @arg SDIO_IT_TXDAVL: Data available in transmit FIFO interrupt
\r
677 * @arg SDIO_IT_RXDAVL: Data available in receive FIFO interrupt
\r
678 * @arg SDIO_IT_SDIOIT: SD I/O interrupt received interrupt
\r
679 * @arg SDIO_IT_CEATAEND: CE-ATA command completion signal received for CMD61 interrupt
\r
682 #define __SDIO_DISABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->MASK &= ~(__INTERRUPT__))
\r
685 * @brief Checks whether the specified SDIO flag is set or not.
\r
686 * @param __INSTANCE__ : Pointer to SDIO register base
\r
687 * @param __FLAG__: specifies the flag to check.
\r
688 * This parameter can be one of the following values:
\r
689 * @arg SDIO_FLAG_CCRCFAIL: Command response received (CRC check failed)
\r
690 * @arg SDIO_FLAG_DCRCFAIL: Data block sent/received (CRC check failed)
\r
691 * @arg SDIO_FLAG_CTIMEOUT: Command response timeout
\r
692 * @arg SDIO_FLAG_DTIMEOUT: Data timeout
\r
693 * @arg SDIO_FLAG_TXUNDERR: Transmit FIFO underrun error
\r
694 * @arg SDIO_FLAG_RXOVERR: Received FIFO overrun error
\r
695 * @arg SDIO_FLAG_CMDREND: Command response received (CRC check passed)
\r
696 * @arg SDIO_FLAG_CMDSENT: Command sent (no response required)
\r
697 * @arg SDIO_FLAG_DATAEND: Data end (data counter, SDIDCOUNT, is zero)
\r
698 * @arg SDIO_FLAG_STBITERR: Start bit not detected on all data signals in wide bus mode.
\r
699 * @arg SDIO_FLAG_DBCKEND: Data block sent/received (CRC check passed)
\r
700 * @arg SDIO_FLAG_CMDACT: Command transfer in progress
\r
701 * @arg SDIO_FLAG_TXACT: Data transmit in progress
\r
702 * @arg SDIO_FLAG_RXACT: Data receive in progress
\r
703 * @arg SDIO_FLAG_TXFIFOHE: Transmit FIFO Half Empty
\r
704 * @arg SDIO_FLAG_RXFIFOHF: Receive FIFO Half Full
\r
705 * @arg SDIO_FLAG_TXFIFOF: Transmit FIFO full
\r
706 * @arg SDIO_FLAG_RXFIFOF: Receive FIFO full
\r
707 * @arg SDIO_FLAG_TXFIFOE: Transmit FIFO empty
\r
708 * @arg SDIO_FLAG_RXFIFOE: Receive FIFO empty
\r
709 * @arg SDIO_FLAG_TXDAVL: Data available in transmit FIFO
\r
710 * @arg SDIO_FLAG_RXDAVL: Data available in receive FIFO
\r
711 * @arg SDIO_FLAG_SDIOIT: SD I/O interrupt received
\r
712 * @arg SDIO_FLAG_CEATAEND: CE-ATA command completion signal received for CMD61
\r
713 * @retval The new state of SDIO_FLAG (SET or RESET).
\r
715 #define __SDIO_GET_FLAG(__INSTANCE__, __FLAG__) (((__INSTANCE__)->STA &(__FLAG__)) != RESET)
\r
719 * @brief Clears the SDIO's pending flags.
\r
720 * @param __INSTANCE__ : Pointer to SDIO register base
\r
721 * @param __FLAG__: specifies the flag to clear.
\r
722 * This parameter can be one or a combination of the following values:
\r
723 * @arg SDIO_FLAG_CCRCFAIL: Command response received (CRC check failed)
\r
724 * @arg SDIO_FLAG_DCRCFAIL: Data block sent/received (CRC check failed)
\r
725 * @arg SDIO_FLAG_CTIMEOUT: Command response timeout
\r
726 * @arg SDIO_FLAG_DTIMEOUT: Data timeout
\r
727 * @arg SDIO_FLAG_TXUNDERR: Transmit FIFO underrun error
\r
728 * @arg SDIO_FLAG_RXOVERR: Received FIFO overrun error
\r
729 * @arg SDIO_FLAG_CMDREND: Command response received (CRC check passed)
\r
730 * @arg SDIO_FLAG_CMDSENT: Command sent (no response required)
\r
731 * @arg SDIO_FLAG_DATAEND: Data end (data counter, SDIDCOUNT, is zero)
\r
732 * @arg SDIO_FLAG_STBITERR: Start bit not detected on all data signals in wide bus mode
\r
733 * @arg SDIO_FLAG_DBCKEND: Data block sent/received (CRC check passed)
\r
734 * @arg SDIO_FLAG_SDIOIT: SD I/O interrupt received
\r
735 * @arg SDIO_FLAG_CEATAEND: CE-ATA command completion signal received for CMD61
\r
738 #define __SDIO_CLEAR_FLAG(__INSTANCE__, __FLAG__) ((__INSTANCE__)->ICR = (__FLAG__))
\r
741 * @brief Checks whether the specified SDIO interrupt has occurred or not.
\r
742 * @param __INSTANCE__ : Pointer to SDIO register base
\r
743 * @param __INTERRUPT__: specifies the SDIO interrupt source to check.
\r
744 * This parameter can be one of the following values:
\r
745 * @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
\r
746 * @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
\r
747 * @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt
\r
748 * @arg SDIO_IT_DTIMEOUT: Data timeout interrupt
\r
749 * @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt
\r
750 * @arg SDIO_IT_RXOVERR: Received FIFO overrun error interrupt
\r
751 * @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt
\r
752 * @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt
\r
753 * @arg SDIO_IT_DATAEND: Data end (data counter, SDIDCOUNT, is zero) interrupt
\r
754 * @arg SDIO_IT_STBITERR: Start bit not detected on all data signals in wide
\r
755 * bus mode interrupt
\r
756 * @arg SDIO_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt
\r
757 * @arg SDIO_IT_CMDACT: Command transfer in progress interrupt
\r
758 * @arg SDIO_IT_TXACT: Data transmit in progress interrupt
\r
759 * @arg SDIO_IT_RXACT: Data receive in progress interrupt
\r
760 * @arg SDIO_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt
\r
761 * @arg SDIO_IT_RXFIFOHF: Receive FIFO Half Full interrupt
\r
762 * @arg SDIO_IT_TXFIFOF: Transmit FIFO full interrupt
\r
763 * @arg SDIO_IT_RXFIFOF: Receive FIFO full interrupt
\r
764 * @arg SDIO_IT_TXFIFOE: Transmit FIFO empty interrupt
\r
765 * @arg SDIO_IT_RXFIFOE: Receive FIFO empty interrupt
\r
766 * @arg SDIO_IT_TXDAVL: Data available in transmit FIFO interrupt
\r
767 * @arg SDIO_IT_RXDAVL: Data available in receive FIFO interrupt
\r
768 * @arg SDIO_IT_SDIOIT: SD I/O interrupt received interrupt
\r
769 * @arg SDIO_IT_CEATAEND: CE-ATA command completion signal received for CMD61 interrupt
\r
770 * @retval The new state of SDIO_IT (SET or RESET).
\r
772 #define __SDIO_GET_IT (__INSTANCE__, __INTERRUPT__) (((__INSTANCE__)->STA &(__INTERRUPT__)) == (__INTERRUPT__))
\r
775 * @brief Clears the SDIO's interrupt pending bits.
\r
776 * @param __INSTANCE__ : Pointer to SDIO register base
\r
777 * @param __INTERRUPT__: specifies the interrupt pending bit to clear.
\r
778 * This parameter can be one or a combination of the following values:
\r
779 * @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
\r
780 * @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
\r
781 * @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt
\r
782 * @arg SDIO_IT_DTIMEOUT: Data timeout interrupt
\r
783 * @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt
\r
784 * @arg SDIO_IT_RXOVERR: Received FIFO overrun error interrupt
\r
785 * @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt
\r
786 * @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt
\r
787 * @arg SDIO_IT_DATAEND: Data end (data counter, SDIO_DCOUNT, is zero) interrupt
\r
788 * @arg SDIO_IT_STBITERR: Start bit not detected on all data signals in wide
\r
789 * bus mode interrupt
\r
790 * @arg SDIO_IT_SDIOIT: SD I/O interrupt received interrupt
\r
791 * @arg SDIO_IT_CEATAEND: CE-ATA command completion signal received for CMD61
\r
794 #define __SDIO_CLEAR_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->ICR = (__INTERRUPT__))
\r
797 * @brief Enable Start the SD I/O Read Wait operation.
\r
801 #define __SDIO_START_READWAIT_ENABLE() (*(__IO uint32_t *) DCTRL_RWSTART_BB = ENABLE)
\r
804 * @brief Disable Start the SD I/O Read Wait operations.
\r
808 #define __SDIO_START_READWAIT_DISABLE() (*(__IO uint32_t *) DCTRL_RWSTART_BB = DISABLE)
\r
811 * @brief Enable Start the SD I/O Read Wait operation.
\r
815 #define __SDIO_STOP_READWAIT_ENABLE() (*(__IO uint32_t *) DCTRL_RWSTOP_BB = ENABLE)
\r
818 * @brief Disable Stop the SD I/O Read Wait operations.
\r
822 #define __SDIO_STOP_READWAIT_DISABLE() (*(__IO uint32_t *) DCTRL_RWSTOP_BB = DISABLE)
\r
825 * @brief Enable the SD I/O Mode Operation.
\r
829 #define __SDIO_OPERATION_ENABLE() (*(__IO uint32_t *) DCTRL_SDIOEN_BB = ENABLE)
\r
832 * @brief Disable the SD I/O Mode Operation.
\r
836 #define __SDIO_OPERATION_DISABLE() (*(__IO uint32_t *) DCTRL_SDIOEN_BB = DISABLE)
\r
839 * @brief Enable the SD I/O Suspend command sending.
\r
843 #define __SDIO_SUSPEND_CMD_ENABLE() (*(__IO uint32_t *) CMD_SDIOSUSPEND_BB = ENABLE)
\r
846 * @brief Disable the SD I/O Suspend command sending.
\r
850 #define __SDIO_SUSPEND_CMD_DISABLE() (*(__IO uint32_t *) CMD_SDIOSUSPEND_BB = DISABLE)
\r
853 * @brief Enable the command completion signal.
\r
857 #define __SDIO_CEATA_CMD_COMPLETION_ENABLE() (*(__IO uint32_t *) CMD_ENCMDCOMPL_BB = ENABLE)
\r
860 * @brief Disable the command completion signal.
\r
864 #define __SDIO_CEATA_CMD_COMPLETION_DISABLE() (*(__IO uint32_t *) CMD_ENCMDCOMPL_BB = DISABLE)
\r
867 * @brief Enable the CE-ATA interrupt.
\r
871 #define __SDIO_CEATA_ENABLE_IT() (*(__IO uint32_t *) CMD_NIEN_BB = (uint32_t)0)
\r
874 * @brief Disable the CE-ATA interrupt.
\r
878 #define __SDIO_CEATA_DISABLE_IT() (*(__IO uint32_t *) CMD_NIEN_BB = (uint32_t)1)
\r
881 * @brief Enable send CE-ATA command (CMD61).
\r
885 #define __SDIO_CEATA_SENDCMD_ENABLE() (*(__IO uint32_t *) CMD_ATACMD_BB = ENABLE)
\r
888 * @brief Disable send CE-ATA command (CMD61).
\r
892 #define __SDIO_CEATA_SENDCMD_DISABLE() (*(__IO uint32_t *) CMD_ATACMD_BB = DISABLE)
\r
898 /* Exported functions --------------------------------------------------------*/
\r
900 /* Initialization/de-initialization functions **********************************/
\r
901 HAL_StatusTypeDef SDIO_Init(SDIO_TypeDef *SDIOx, SDIO_InitTypeDef Init);
\r
903 /* I/O operation functions *****************************************************/
\r
904 /* Blocking mode: Polling */
\r
905 uint32_t SDIO_ReadFIFO(SDIO_TypeDef *SDIOx);
\r
906 HAL_StatusTypeDef SDIO_WriteFIFO(SDIO_TypeDef *SDIOx, uint32_t *pWriteData);
\r
908 /* Peripheral Control functions ************************************************/
\r
909 HAL_StatusTypeDef SDIO_PowerState_ON(SDIO_TypeDef *SDIOx);
\r
910 HAL_StatusTypeDef SDIO_PowerState_OFF(SDIO_TypeDef *SDIOx);
\r
911 uint32_t SDIO_GetPowerState(SDIO_TypeDef *SDIOx);
\r
913 /* Command path state machine (CPSM) management functions */
\r
914 HAL_StatusTypeDef SDIO_SendCommand(SDIO_TypeDef *SDIOx, SDIO_CmdInitTypeDef *SDIO_CmdInitStruct);
\r
915 uint8_t SDIO_GetCommandResponse(SDIO_TypeDef *SDIOx);
\r
916 uint32_t SDIO_GetResponse(uint32_t SDIO_RESP);
\r
918 /* Data path state machine (DPSM) management functions */
\r
919 HAL_StatusTypeDef SDIO_DataConfig(SDIO_TypeDef *SDIOx, SDIO_DataInitTypeDef* SDIO_DataInitStruct);
\r
920 uint32_t SDIO_GetDataCounter(SDIO_TypeDef *SDIOx);
\r
921 uint32_t SDIO_GetFIFOCount(SDIO_TypeDef *SDIOx);
\r
923 /* SDIO IO Cards mode management functions */
\r
924 HAL_StatusTypeDef SDIO_SetSDIOReadWaitMode(uint32_t SDIO_ReadWaitMode);
\r
930 #endif /* __STM32F4xx_LL_SDMMC_H */
\r
940 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
\r