#define LCD_FRAME_BUFFER_LAYER1 LCD_FRAME_BUFFER\r
#define CONVERTED_FRAME_BUFFER (LCD_FRAME_BUFFER+0x260000)\r
\r
+static void SystemClock_Config(void)\r
+{\r
+ RCC_ClkInitTypeDef RCC_ClkInitStruct;\r
+ RCC_OscInitTypeDef RCC_OscInitStruct;\r
+\r
+ /* Enable Power Control clock */\r
+ __PWR_CLK_ENABLE();\r
+\r
+ /* The voltage scaling allows optimizing the power consumption when the device is\r
+ clocked below the maximum system frequency, to update the voltage scaling value\r
+ regarding system frequency refer to product datasheet. */\r
+ __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);\r
+\r
+ /* Enable HSE Oscillator and activate PLL with HSE as source */\r
+ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;\r
+ RCC_OscInitStruct.HSEState = RCC_HSE_ON;\r
+ RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;\r
+ RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;\r
+ RCC_OscInitStruct.PLL.PLLM = 8;\r
+ RCC_OscInitStruct.PLL.PLLN = 336;\r
+ RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2;\r
+ RCC_OscInitStruct.PLL.PLLQ = 7;\r
+ HAL_RCC_OscConfig (&RCC_OscInitStruct);\r
+\r
+ /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2\r
+ clocks dividers */\r
+ RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);\r
+ RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;\r
+ RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;\r
+ RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV4;\r
+ RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV2;\r
+ HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_5);\r
+}\r
+\r
+\r
void hw_init(void)\r
{\r
- pll_init();\r
+ SystemInit();\r
HAL_Init();\r
+ SystemClock_Config();\r
\r
/* Initialize the LEDs */\r
BSP_LED_Init(LED3);\r