+++ /dev/null
-/**\r
- ******************************************************************************\r
- * @file stm32f4xx_hal_pwr_ex.c\r
- * @author MCD Application Team\r
- * @version V1.0.0\r
- * @date 18-February-2014\r
- * @brief Extended PWR HAL module driver.\r
- * This file provides firmware functions to manage the following \r
- * functionalities of PWR extension peripheral: \r
- * + Peripheral Extended features functions\r
- * \r
- ******************************************************************************\r
- * @attention\r
- *\r
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>\r
- *\r
- * Redistribution and use in source and binary forms, with or without modification,\r
- * are permitted provided that the following conditions are met:\r
- * 1. Redistributions of source code must retain the above copyright notice,\r
- * this list of conditions and the following disclaimer.\r
- * 2. Redistributions in binary form must reproduce the above copyright notice,\r
- * this list of conditions and the following disclaimer in the documentation\r
- * and/or other materials provided with the distribution.\r
- * 3. Neither the name of STMicroelectronics nor the names of its contributors\r
- * may be used to endorse or promote products derived from this software\r
- * without specific prior written permission.\r
- *\r
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\r
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
- *\r
- ******************************************************************************\r
- */ \r
-\r
-/* Includes ------------------------------------------------------------------*/\r
-#include "stm32f4xx_hal.h"\r
-\r
-/** @addtogroup STM32F4xx_HAL_Driver\r
- * @{\r
- */\r
-\r
-/** @defgroup PWREx \r
- * @brief PWR HAL module driver\r
- * @{\r
- */\r
-\r
-#ifdef HAL_PWR_MODULE_ENABLED\r
-\r
-/* Private typedef -----------------------------------------------------------*/\r
-/* Private define ------------------------------------------------------------*/\r
-#define PWR_OVERDRIVE_TIMEOUT_VALUE 1000\r
-#define PWR_BKPREG_TIMEOUT_VALUE 1000\r
-/* Private macro -------------------------------------------------------------*/\r
-/* Private variables ---------------------------------------------------------*/\r
-/* Private function prototypes -----------------------------------------------*/\r
-/* Private functions ---------------------------------------------------------*/\r
-\r
-/** @defgroup PWREx_Private_Functions\r
- * @{\r
- */\r
-\r
-/** @defgroup PWREx_Group1 Peripheral Extended features functions \r
- * @brief Peripheral Extended features functions \r
- *\r
-@verbatim \r
-\r
- ===============================================================================\r
- ##### Peripheral extended features functions #####\r
- ===============================================================================\r
-\r
- *** Main and Backup Regulators configuration ***\r
- ================================================\r
- [..] \r
- (+) The backup domain includes 4 Kbytes of backup SRAM accessible only from \r
- the CPU, and address in 32-bit, 16-bit or 8-bit mode. Its content is \r
- retained even in Standby or VBAT mode when the low power backup regulator\r
- is enabled. It can be considered as an internal EEPROM when VBAT is \r
- always present. You can use the HAL_PWR_EnableBkUpReg() function to \r
- enable the low power backup regulator. \r
-\r
- (+) When the backup domain is supplied by VDD (analog switch connected to VDD) \r
- the backup SRAM is powered from VDD which replaces the VBAT power supply to \r
- save battery life.\r
-\r
- (+) The backup SRAM is not mass erased by a tamper event. It is read \r
- protected to prevent confidential data, such as cryptographic private \r
- key, from being accessed. The backup SRAM can be erased only through \r
- the Flash interface when a protection level change from level 1 to \r
- level 0 is requested. \r
- -@- Refer to the description of Read protection (RDP) in the Flash \r
- programming manual.\r
-\r
- (+) The main internal regulator can be configured to have a tradeoff between \r
- performance and power consumption when the device does not operate at \r
- the maximum frequency. This is done through __HAL_PWR_MAINREGULATORMODE_CONFIG() \r
- macro which configure VOS bit in PWR_CR register\r
- \r
- Refer to the product datasheets for more details.\r
-\r
- *** FLASH Power Down configuration ****\r
- =======================================\r
- [..] \r
- (+) By setting the FPDS bit in the PWR_CR register by using the \r
- HAL_PWR_EnableFlashPowerDown() function, the Flash memory also enters power \r
- down mode when the device enters Stop mode. When the Flash memory \r
- is in power down mode, an additional startup delay is incurred when \r
- waking up from Stop mode.\r
- \r
- (+) For STM32F42xxx/43xxx Devices, the scale can be modified only when the PLL \r
- is OFF and the HSI or HSE clock source is selected as system clock. \r
- The new value programmed is active only when the PLL is ON.\r
- When the PLL is OFF, the voltage scale 3 is automatically selected. \r
- Refer to the datasheets for more details.\r
-\r
- *** Over-Drive and Under-Drive configuration ****\r
- =================================================\r
- [..] \r
- (+) For STM32F42xxx/43xxx Devices, in Run mode: the main regulator has\r
- 2 operating modes available:\r
- (++) Normal mode: The CPU and core logic operate at maximum frequency at a given \r
- voltage scaling (scale 1, scale 2 or scale 3)\r
- (++) Over-drive mode: This mode allows the CPU and the core logic to operate at a \r
- higher frequency than the normal mode for a given voltage scaling (scale 1, \r
- scale 2 or scale 3). This mode is enabled through HAL_PWREx_EnableOverDrive() function and\r
- disabled by HAL_PWREx_DisableOverDrive() function, to enter or exit from Over-drive mode please follow \r
- the sequence described in Reference manual.\r
- \r
- (+) For STM32F42xxx/43xxx Devices, in Stop mode: the main regulator or low power regulator \r
- supplies a low power voltage to the 1.2V domain, thus preserving the content of registers \r
- and internal SRAM. 2 operating modes are available:\r
- (++) Normal mode: the 1.2V domain is preserved in nominal leakage mode. This mode is only \r
- available when the main regulator or the low power regulator is used in Scale 3 or \r
- low voltage mode.\r
- (++) Under-drive mode: the 1.2V domain is preserved in reduced leakage mode. This mode is only\r
- available when the main regulator or the low power regulator is in low voltage mode.\r
-\r
-@endverbatim\r
- * @{\r
- */\r
-\r
-/**\r
- * @brief Enables the Backup Regulator.\r
- * @param None\r
- * @retval HAL status\r
- */\r
-HAL_StatusTypeDef HAL_PWREx_EnableBkUpReg(void)\r
-{\r
- uint32_t timeout = 0; \r
-\r
- *(__IO uint32_t *) CSR_BRE_BB = (uint32_t)ENABLE;\r
-\r
- /* Get timeout */\r
- timeout = HAL_GetTick() + PWR_BKPREG_TIMEOUT_VALUE;\r
- /* Wait till Backup regulator ready flag is set */ \r
- while(__HAL_PWR_GET_FLAG(PWR_FLAG_BRR) == RESET)\r
- {\r
- if(HAL_GetTick() >= timeout)\r
- {\r
- return HAL_TIMEOUT;\r
- } \r
- }\r
- return HAL_OK;\r
-}\r
-\r
-/**\r
- * @brief Disables the Backup Regulator.\r
- * @param None\r
- * @retval None\r
- */\r
-HAL_StatusTypeDef HAL_PWREx_DisableBkUpReg(void)\r
-{\r
- uint32_t timeout = 0; \r
-\r
- *(__IO uint32_t *) CSR_BRE_BB = (uint32_t)DISABLE;\r
-\r
- /* Get timeout */\r
- timeout = HAL_GetTick() + PWR_BKPREG_TIMEOUT_VALUE;\r
- /* Wait till Backup regulator ready flag is set */ \r
- while(__HAL_PWR_GET_FLAG(PWR_FLAG_BRR) != RESET)\r
- {\r
- if(HAL_GetTick() >= timeout)\r
- {\r
- return HAL_TIMEOUT;\r
- } \r
- }\r
- return HAL_OK;\r
-}\r
-\r
-/**\r
- * @brief Enables the Flash Power Down in Stop mode.\r
- * @param None\r
- * @retval None\r
- */\r
-void HAL_PWREx_EnableFlashPowerDown(void)\r
-{\r
- *(__IO uint32_t *) CR_FPDS_BB = (uint32_t)ENABLE;\r
-}\r
-\r
-/**\r
- * @brief Disables the Flash Power Down in Stop mode.\r
- * @param None\r
- * @retval None\r
- */\r
-void HAL_PWREx_DisableFlashPowerDown(void)\r
-{\r
- *(__IO uint32_t *) CR_FPDS_BB = (uint32_t)DISABLE;\r
-}\r
-\r
-#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)\r
-/**\r
- * @brief Activates the Over-Drive mode.\r
- * @note These macros can be used only for STM32F42xx/STM32F43xx devices.\r
- * This mode allows the CPU and the core logic to operate at a higher frequency\r
- * than the normal mode for a given voltage scaling (scale 1, scale 2 or scale 3). \r
- * @note It is recommended to enter or exit Over-drive mode when the application is not running \r
- * critical tasks and when the system clock source is either HSI or HSE. \r
- * During the Over-drive switch activation, no peripheral clocks should be enabled. \r
- * The peripheral clocks must be enabled once the Over-drive mode is activated. \r
- * @param None\r
- * @retval HAL status\r
- */\r
-HAL_StatusTypeDef HAL_PWREx_ActivateOverDrive(void)\r
-{\r
- uint32_t timeout = 0;\r
- \r
- __PWR_CLK_ENABLE();\r
- \r
- /* Enable the Over-drive to extend the clock frequency to 180 Mhz */\r
- __HAL_PWR_OVERDRIVE_ENABLE();\r
- \r
- /* Get timeout */\r
- timeout = HAL_GetTick() + PWR_OVERDRIVE_TIMEOUT_VALUE;\r
- while(!__HAL_PWR_GET_FLAG(PWR_FLAG_ODRDY))\r
- {\r
- if(HAL_GetTick() >= timeout)\r
- {\r
- return HAL_TIMEOUT;\r
- }\r
- }\r
- \r
- /* Enable the Over-drive switch */\r
- __HAL_PWR_OVERDRIVESWITCHING_ENABLE();\r
- \r
- /* Get timeout */\r
- timeout = HAL_GetTick() + PWR_OVERDRIVE_TIMEOUT_VALUE;\r
- while(!__HAL_PWR_GET_FLAG(PWR_FLAG_ODSWRDY))\r
- {\r
- if(HAL_GetTick() >= timeout)\r
- {\r
- return HAL_TIMEOUT;\r
- }\r
- } \r
- return HAL_OK;\r
-}\r
-\r
-/**\r
- * @brief Deactivates the Over-Drive mode.\r
- * @note These macros can be used only for STM32F42xx/STM32F43xx devices.\r
- * This mode allows the CPU and the core logic to operate at a higher frequency\r
- * than the normal mode for a given voltage scaling (scale 1, scale 2 or scale 3). \r
- * @note It is recommended to enter or exit Over-drive mode when the application is not running \r
- * critical tasks and when the system clock source is either HSI or HSE. \r
- * During the Over-drive switch activation, no peripheral clocks should be enabled. \r
- * The peripheral clocks must be enabled once the Over-drive mode is activated.\r
- * @param None\r
- * @retval HAL status\r
- */\r
-HAL_StatusTypeDef HAL_PWREx_DeactivateOverDrive(void)\r
-{\r
- uint32_t timeout = 0;\r
- \r
- __PWR_CLK_ENABLE();\r
- \r
- /* Disable the Over-drive switch */\r
- __HAL_PWR_OVERDRIVESWITCHING_DISABLE();\r
- \r
- /* Get timeout */\r
- timeout = HAL_GetTick() + PWR_OVERDRIVE_TIMEOUT_VALUE;\r
- \r
- while(__HAL_PWR_GET_FLAG(PWR_FLAG_ODSWRDY))\r
- {\r
- if(HAL_GetTick() >= timeout)\r
- {\r
- return HAL_TIMEOUT;\r
- }\r
- } \r
- \r
- /* Disable the Over-drive */\r
- __HAL_PWR_OVERDRIVE_DISABLE();\r
-\r
- /* Get timeout */\r
- timeout = HAL_GetTick() + PWR_OVERDRIVE_TIMEOUT_VALUE; \r
-\r
- while(__HAL_PWR_GET_FLAG(PWR_FLAG_ODRDY))\r
- {\r
- if(HAL_GetTick() >= timeout)\r
- {\r
- return HAL_TIMEOUT;\r
- }\r
- }\r
- \r
- return HAL_OK;\r
-}\r
-#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */\r
-/**\r
- * @}\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-#endif /* HAL_PWR_MODULE_ENABLED */\r
-/**\r
- * @}\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
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