+++ /dev/null
-/**\r
- ******************************************************************************\r
- * @file stm32f4xx_ll_sdmmc.c\r
- * @author MCD Application Team\r
- * @version V1.0.0\r
- * @date 18-February-2014\r
- * @brief SDMMC Low Layer HAL module driver.\r
- * \r
- * This file provides firmware functions to manage the following \r
- * functionalities of the SDMMC peripheral:\r
- * + Initialization/de-initialization functions\r
- * + I/O operation functions\r
- * + Peripheral Control functions \r
- * + Peripheral State functions\r
- * \r
- @verbatim\r
- ==============================================================================\r
- ##### SDMMC peripheral features #####\r
- ============================================================================== \r
- [..] The SD/SDIO MMC card host interface (SDIO) provides an interface between the APB2\r
- peripheral bus and MultiMedia cards (MMCs), SD memory cards, SDIO cards and CE-ATA\r
- devices.\r
-\r
- [..] The MultiMedia Card system specifications are available through the MultiMedia Card\r
- Association website at www.mmca.org, published by the MMCA technical committee.\r
- SD memory card and SD I/O card system specifications are available through the SD card\r
- Association website at www.sdcard.org.\r
- CE-ATA system specifications are available through the CE-ATA work group web site at\r
- www.ce-ata.org.\r
- \r
- [..] The SDIO features include the following:\r
- (+) Full compliance with MultiMedia Card System Specification Version 4.2. Card support\r
- for three different databus modes: 1-bit (default), 4-bit and 8-bit\r
- (+) Full compatibility with previous versions of MultiMedia Cards (forward compatibility)\r
- (+) Full compliance with SD Memory Card Specifications Version 2.0\r
- (+) Full compliance with SD I/O Card Specification Version 2.0: card support for two\r
- different data bus modes: 1-bit (default) and 4-bit\r
- (+) Full support of the CE-ATA features (full compliance with CE-ATA digital protocol\r
- Rev1.1)\r
- (+) Data transfer up to 48 MHz for the 8 bit mode\r
- (+) Data and command output enable signals to control external bidirectional drivers.\r
- \r
- \r
- ##### How to use this driver #####\r
- ==============================================================================\r
- [..]\r
- This driver is a considered as a driver of service for external devices drivers \r
- that interfaces with the SDIO peripheral.\r
- According to the device used (SD card/ MMC card / SDIO card ...), a set of APIs \r
- is used in the device's driver to perform SDIO operations and functionalities.\r
- \r
- This driver is almost transparent for the final user, it is only used to implement other\r
- functionalities of the external device.\r
- \r
- [..]\r
- (+) The SDIO clock (SDIOCLK = 48 MHz) is coming from a specific output of PLL \r
- (PLL48CLK). Before start working with SDIO peripheral make sure that the\r
- PLL is well configured.\r
- The SDIO peripheral uses two clock signals:\r
- (++) SDIO adapter clock (SDIOCLK = 48 MHz)\r
- (++) APB2 bus clock (PCLK2)\r
- \r
- -@@- PCLK2 and SDIO_CK clock frequencies must respect the following condition:\r
- Frequency(PCLK2) >= (3 / 8 x Frequency(SDIO_CK))\r
- \r
- (+) Enable/Disable peripheral clock using RCC peripheral macros related to SDIO\r
- peripheral.\r
-\r
- (+) Enable the Power ON State using the HAL_SDIO_PowerState_ON(hsdio) \r
- function and disable it using the function HAL_SDIO_PowerState_OFF(hsdio).\r
- \r
- (+) Enable/Disable the clock using the __SDIO_ENABLE()/__SDIO_DISABLE() macros.\r
- \r
- (+) Enable/Disable the peripheral interrupts using the macros __SDIO_ENABLE_IT(hsdio, IT) \r
- and __SDIO_DISABLE_IT(hsdio, IT) if you need to use interrupt mode. \r
- \r
- (+) When using the DMA mode \r
- (++) Configure the DMA in the MSP layer of the external device\r
- (++) Active the needed channel Request \r
- (++) Enable the DMA using __SDIO_DMA_ENABLE() macro or Disable it using the macro\r
- __SDIO_DMA_DISABLE().\r
- \r
- (+) To control the CPSM (Command Path State Machine) and send \r
- commands to the card use the HAL_SDIO_SendCommand(), \r
- HAL_SDIO_GetCommandResponse() and HAL_SDIO_GetResponse() functions. First, user has\r
- to fill the command structure (pointer to SDIO_CmdInitTypeDef) according \r
- to the selected command to be sent.\r
- The parameters that should be filled are:\r
- (++) Command Argument\r
- (++) Command Index\r
- (++) Command Response type\r
- (++) Command Wait\r
- (++) CPSM Status (Enable or Disable).\r
- \r
- -@@- To check if the command is well received, read the SDIO_CMDRESP\r
- register using the HAL_SDIO_GetCommandResponse().\r
- The SDIO responses registers (SDIO_RESP1 to SDIO_RESP2), use the\r
- HAL_SDIO_GetResponse() function.\r
- \r
- (+) To control the DPSM (Data Path State Machine) and send/receive \r
- data to/from the card use the HAL_SDIO_DataConfig(), HAL_SDIO_GetDataCounter(), \r
- HAL_SDIO_ReadFIFO(), HAL_SDIO_WriteFIFO() and HAL_SDIO_GetFIFOCount() functions.\r
- \r
- *** Read Operations ***\r
- =======================\r
- [..]\r
- (#) First, user has to fill the data structure (pointer to\r
- SDIO_DataInitTypeDef) according to the selected data type to be received.\r
- The parameters that should be filled are:\r
- (++) Data TimeOut\r
- (++) Data Length\r
- (++) Data Block size\r
- (++) Data Transfer direction: should be from card (To SDIO)\r
- (++) Data Transfer mode\r
- (++) DPSM Status (Enable or Disable)\r
- \r
- (#) Configure the SDIO resources to receive the data from the card\r
- according to selected transfer mode (Refer to Step 8, 9 and 10).\r
- \r
- (#) Send the selected Read command (refer to step 11).\r
- \r
- (#) Use the SDIO flags/interrupts to check the transfer status.\r
- \r
- *** Write Operations ***\r
- ========================\r
- [..]\r
- (#) First, user has to fill the data structure (pointer to\r
- SDIO_DataInitTypeDef) according to the selected data type to be received.\r
- The parameters that should be filled are:\r
- (++) Data TimeOut\r
- (++) Data Length\r
- (++) Data Block size\r
- (++) Data Transfer direction: should be to card (To CARD)\r
- (++) Data Transfer mode\r
- (++) DPSM Status (Enable or Disable)\r
- \r
- (#) Configure the SDIO resources to send the data to the card according to \r
- selected transfer mode (Refer to Step 8, 9 and 10).\r
- \r
- (#) Send the selected Write command (refer to step 11).\r
- \r
- (#) Use the SDIO flags/interrupts to check the transfer status.\r
- \r
- @endverbatim\r
- ******************************************************************************\r
- * @attention\r
- *\r
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>\r
- *\r
- * Redistribution and use in source and binary forms, with or without modification,\r
- * are permitted provided that the following conditions are met:\r
- * 1. Redistributions of source code must retain the above copyright notice,\r
- * this list of conditions and the following disclaimer.\r
- * 2. Redistributions in binary form must reproduce the above copyright notice,\r
- * this list of conditions and the following disclaimer in the documentation\r
- * and/or other materials provided with the distribution.\r
- * 3. Neither the name of STMicroelectronics nor the names of its contributors\r
- * may be used to endorse or promote products derived from this software\r
- * without specific prior written permission.\r
- *\r
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\r
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
- *\r
- ******************************************************************************\r
- */ \r
-\r
-/* Includes ------------------------------------------------------------------*/\r
-#include "stm32f4xx_hal.h"\r
-\r
-/** @addtogroup STM32F4xx_HAL_Driver\r
- * @{\r
- */\r
-\r
-/** @defgroup SDMMC \r
- * @brief SDMMC HAL module driver\r
- * @{\r
- */\r
-\r
-#if defined (HAL_SD_MODULE_ENABLED) || defined(HAL_MMC_MODULE_ENABLED)\r
-\r
-/* Private typedef -----------------------------------------------------------*/\r
-/* Private define ------------------------------------------------------------*/\r
-/* Private macro -------------------------------------------------------------*/\r
-/* Private variables ---------------------------------------------------------*/\r
-/* Private function prototypes -----------------------------------------------*/\r
-/* Private functions ---------------------------------------------------------*/\r
-\r
-/** @defgroup SDIO_Private_Functions\r
- * @{\r
- */\r
-\r
-/** @defgroup HAL_SDIO_Group1 Initialization/de-initialization functions \r
- * @brief Initialization and Configuration functions \r
- *\r
-@verbatim \r
- ===============================================================================\r
- ##### Initialization/de-initialization functions #####\r
- ===============================================================================\r
- [..] This section provides functions allowing to:\r
- \r
-@endverbatim\r
- * @{\r
- */\r
-\r
-/**\r
- * @brief Initializes the SDIO according to the specified\r
- * parameters in the SDIO_InitTypeDef and create the associated handle.\r
- * @param SDIOx: Pointer to SDIO register base\r
- * @param Init: SDIO initialization structure \r
- * @retval HAL status\r
- */\r
-HAL_StatusTypeDef SDIO_Init(SDIO_TypeDef *SDIOx, SDIO_InitTypeDef Init)\r
-{\r
- __IO uint32_t tmpreg = 0; \r
-\r
- /* Check the parameters */\r
- assert_param(IS_SDIO_ALL_INSTANCE(SDIOx));\r
- assert_param(IS_SDIO_CLOCK_EDGE(Init.ClockEdge)); \r
- assert_param(IS_SDIO_CLOCK_BYPASS(Init.ClockBypass));\r
- assert_param(IS_SDIO_CLOCK_POWER_SAVE(Init.ClockPowerSave));\r
- assert_param(IS_SDIO_BUS_WIDE(Init.BusWide));\r
- assert_param(IS_SDIO_HARDWARE_FLOW_CONTROL(Init.HardwareFlowControl));\r
- assert_param(IS_SDIO_CLKDIV(Init.ClockDiv));\r
- \r
- /* Get the SDIO CLKCR value */\r
- tmpreg = SDIOx->CLKCR;\r
- \r
- /* Clear CLKDIV, PWRSAV, BYPASS, WIDBUS, NEGEDGE, HWFC_EN bits */\r
- tmpreg &= CLKCR_CLEAR_MASK;\r
- \r
- /* Set SDIO configuration parameters */\r
- tmpreg |= (Init.ClockEdge |\\r
- Init.ClockBypass |\\r
- Init.ClockPowerSave |\\r
- Init.BusWide |\\r
- Init.HardwareFlowControl |\\r
- Init.ClockDiv\r
- ); \r
- \r
- /* Write to SDIO CLKCR */\r
- SDIOx->CLKCR = tmpreg; \r
-\r
- return HAL_OK;\r
-}\r
-\r
-\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup HAL_SDIO_Group2 I/O operation functions \r
- * @brief Data transfers functions \r
- *\r
-@verbatim \r
- ===============================================================================\r
- ##### I/O operation functions #####\r
- =============================================================================== \r
- [..]\r
- This subsection provides a set of functions allowing to manage the SDIO data \r
- transfers.\r
-\r
-@endverbatim\r
- * @{\r
- */\r
-\r
-/**\r
- * @brief Read data (word) from Rx FIFO in blocking mode (polling) \r
- * @param SDIOx: Pointer to SDIO register base\r
- * @param ReadData: Data to read\r
- * @retval HAL status\r
- */\r
-uint32_t SDIO_ReadFIFO(SDIO_TypeDef *SDIOx)\r
-{\r
- /* Read data from Rx FIFO */ \r
- return (SDIOx->FIFO);\r
-}\r
-\r
-/**\r
- * @brief Write data (word) to Tx FIFO in blocking mode (polling) \r
- * @param SDIOx: Pointer to SDIO register base\r
- * @param pWriteData: pointer to data to write\r
- * @retval HAL status\r
- */\r
-HAL_StatusTypeDef SDIO_WriteFIFO(SDIO_TypeDef *SDIOx, uint32_t *pWriteData)\r
-{ \r
- /* Write data to FIFO */ \r
- SDIOx->FIFO = *pWriteData;\r
-\r
- return HAL_OK;\r
-}\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup HAL_SDIO_Group3 Peripheral Control functions \r
- * @brief management functions \r
- *\r
-@verbatim \r
- ===============================================================================\r
- ##### Peripheral Control functions #####\r
- =============================================================================== \r
- [..]\r
- This subsection provides a set of functions allowing to control the SDIO data \r
- transfers.\r
-\r
-@endverbatim\r
- * @{\r
- */\r
-\r
-/**\r
- * @brief Set SDIO Power state to ON. \r
- * @param SDIOx: Pointer to SDIO register base\r
- * @retval HAL status\r
- */\r
-HAL_StatusTypeDef SDIO_PowerState_ON(SDIO_TypeDef *SDIOx)\r
-{ \r
- /* Set power state to ON */ \r
- SDIOx->POWER = (uint32_t)0x00000003;\r
- \r
- return HAL_OK; \r
-}\r
-\r
-/**\r
- * @brief Set SDIO Power state to OFF. \r
- * @param SDIOx: Pointer to SDIO register base\r
- * @retval HAL status\r
- */\r
-HAL_StatusTypeDef SDIO_PowerState_OFF(SDIO_TypeDef *SDIOx)\r
-{\r
- /* Set power state to OFF */\r
- SDIOx->POWER = (uint32_t)0x00000000;\r
- \r
- return HAL_OK;\r
-}\r
-\r
-/**\r
- * @brief Get SDIO Power state. \r
- * @param SDIOx: Pointer to SDIO register base\r
- * @retval Power status of the controller. The returned value can be one of the \r
- * following values:\r
- * - 0x00: Power OFF\r
- * - 0x02: Power UP\r
- * - 0x03: Power ON \r
- */\r
-uint32_t SDIO_GetPowerState(SDIO_TypeDef *SDIOx) \r
-{\r
- return (SDIOx->POWER & (~PWR_PWRCTRL_MASK));\r
-}\r
-\r
-/**\r
- * @brief Configure the SDIO command path according to the specified parameters in\r
- * SDIO_CmdInitTypeDef structure and send the command \r
- * @param SDIOx: Pointer to SDIO register base\r
- * @param SDIO_CmdInitStruct: pointer to a SDIO_CmdInitTypeDef structure that contains \r
- * the configuration information for the SDIO command\r
- * @retval HAL status\r
- */\r
-HAL_StatusTypeDef SDIO_SendCommand(SDIO_TypeDef *SDIOx, SDIO_CmdInitTypeDef *SDIO_CmdInitStruct)\r
-{\r
- uint32_t tmpreg = 0;\r
- \r
- /* Check the parameters */\r
- assert_param(IS_SDIO_CMD_INDEX(SDIO_CmdInitStruct->CmdIndex));\r
- assert_param(IS_SDIO_RESPONSE(SDIO_CmdInitStruct->Response));\r
- assert_param(IS_SDIO_WAIT(SDIO_CmdInitStruct->WaitForInterrupt));\r
- assert_param(IS_SDIO_CPSM(SDIO_CmdInitStruct->CPSM));\r
-\r
- /* Set the SDIO Argument value */\r
- SDIOx->ARG = SDIO_CmdInitStruct->Argument;\r
- \r
- /* SDIO CMD Configuration */ \r
- /* Get the SDIO CMD value */\r
- tmpreg = SDIOx->CMD;\r
- \r
- /* Clear CMDINDEX, WAITRESP, WAITINT, WAITPEND, CPSMEN bits */\r
- tmpreg &= CMD_CLEAR_MASK;\r
- \r
- /* Set SDIO command parameters */\r
- tmpreg |= (uint32_t)(SDIO_CmdInitStruct->CmdIndex |\\r
- SDIO_CmdInitStruct->Response |\\r
- SDIO_CmdInitStruct->WaitForInterrupt |\\r
- SDIO_CmdInitStruct->CPSM);\r
- \r
- /* Write to SDIO CMD register */\r
- SDIOx->CMD = tmpreg;\r
- \r
- return HAL_OK; \r
-}\r
-\r
-/**\r
- * @brief Return the command index of last command for which response received\r
- * @param SDIOx: Pointer to SDIO register base\r
- * @retval Command index of the last command response received\r
- */\r
-uint8_t SDIO_GetCommandResponse(SDIO_TypeDef *SDIOx)\r
-{\r
- return (uint8_t)(SDIOx->RESPCMD);\r
-}\r
-\r
-\r
-/**\r
- * @brief Return the response received from the card for the last command\r
- * @param SDIO_RESP: Specifies the SDIO response register. \r
- * This parameter can be one of the following values:\r
- * @arg SDIO_RESP1: Response Register 1\r
- * @arg SDIO_RESP2: Response Register 2\r
- * @arg SDIO_RESP3: Response Register 3\r
- * @arg SDIO_RESP4: Response Register 4 \r
- * @retval The Corresponding response register value\r
- */\r
-uint32_t SDIO_GetResponse(uint32_t SDIO_RESP)\r
-{\r
- __IO uint32_t tmp = 0;\r
-\r
- /* Check the parameters */\r
- assert_param(IS_SDIO_RESP(SDIO_RESP));\r
-\r
- /* Get the response */\r
- tmp = SDIO_RESP_ADDR + SDIO_RESP;\r
- \r
- return (*(__IO uint32_t *) tmp);\r
-} \r
-\r
-/**\r
- * @brief Configure the SDIO data path according to the specified \r
- * parameters in the SDIO_DataInitTypeDef.\r
- * @param SDIOx: Pointer to SDIO register base \r
- * @param SDIO_DataInitStruct : pointer to a SDIO_DataInitTypeDef structure \r
- * that contains the configuration information for the SDIO command.\r
- * @retval HAL status\r
- */\r
-HAL_StatusTypeDef SDIO_DataConfig(SDIO_TypeDef *SDIOx, SDIO_DataInitTypeDef* SDIO_DataInitStruct)\r
-{\r
- uint32_t tmpreg = 0;\r
- \r
- /* Check the parameters */\r
- assert_param(IS_SDIO_DATA_LENGTH(SDIO_DataInitStruct->DataLength));\r
- assert_param(IS_SDIO_BLOCK_SIZE(SDIO_DataInitStruct->DataBlockSize));\r
- assert_param(IS_SDIO_TRANSFER_DIR(SDIO_DataInitStruct->TransferDir));\r
- assert_param(IS_SDIO_TRANSFER_MODE(SDIO_DataInitStruct->TransferMode));\r
- assert_param(IS_SDIO_DPSM(SDIO_DataInitStruct->DPSM));\r
-\r
- /* Set the SDIO Data TimeOut value */\r
- SDIOx->DTIMER = SDIO_DataInitStruct->DataTimeOut;\r
-\r
- /* Set the SDIO DataLength value */\r
- SDIOx->DLEN = SDIO_DataInitStruct->DataLength;\r
-\r
-/* SDIO DCTRL Configuration */ \r
- /* Get the SDIO DCTRL value */\r
- tmpreg = SDIOx->DCTRL;\r
- \r
- /* Clear DEN, DTMODE, DTDIR and DBCKSIZE bits */\r
- tmpreg &= DCTRL_CLEAR_MASK;\r
- \r
- /* Set the SDIO data configuration parameters */\r
- tmpreg |= (uint32_t)(SDIO_DataInitStruct->DataBlockSize |\\r
- SDIO_DataInitStruct->TransferDir |\\r
- SDIO_DataInitStruct->TransferMode |\\r
- SDIO_DataInitStruct->DPSM);\r
-\r
- /* Write to SDIO DCTRL */\r
- SDIOx->DCTRL = tmpreg;\r
-\r
- return HAL_OK;\r
-\r
-}\r
-\r
-/**\r
- * @brief Returns number of remaining data bytes to be transferred.\r
- * @param SDIOx: Pointer to SDIO register base\r
- * @retval Number of remaining data bytes to be transferred\r
- */\r
-uint32_t SDIO_GetDataCounter(SDIO_TypeDef *SDIOx)\r
-{\r
- return (SDIOx->DCOUNT);\r
-}\r
-\r
-/**\r
- * @brief Get the FIFO data\r
- * @param hsdio: SDIO handle\r
- * @retval Data received\r
- */\r
-uint32_t SDIO_GetFIFOCount(SDIO_TypeDef *SDIOx)\r
-{\r
- return (SDIOx->FIFO);\r
-}\r
-\r
-\r
-/**\r
- * @brief Sets one of the two options of inserting read wait interval.\r
- * @param SDIO_ReadWaitMode: SD I/O Read Wait operation mode.\r
- * This parameter can be:\r
- * @arg SDIO_READ_WAIT_MODE_CLK: Read Wait control by stopping SDIOCLK\r
- * @arg SDIO_READ_WAIT_MODE_DATA2: Read Wait control using SDIO_DATA2\r
- * @retval None\r
- */\r
-HAL_StatusTypeDef SDIO_SetSDIOReadWaitMode(uint32_t SDIO_ReadWaitMode)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_SDIO_READWAIT_MODE(SDIO_ReadWaitMode));\r
- \r
- *(__IO uint32_t *)DCTRL_RWMOD_BB = SDIO_ReadWaitMode;\r
- \r
- return HAL_OK; \r
-}\r
-\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup HAL_SDIO_Group3 Peripheral State functions \r
- * @brief Peripheral State functions \r
- *\r
-@verbatim \r
- ===============================================================================\r
- ##### Peripheral State functions #####\r
- =============================================================================== \r
- [..]\r
- This subsection permit to get in runtime the status of the SDIO peripheral \r
- and the data flow.\r
-\r
-@endverbatim\r
- * @{\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-#endif /* (HAL_SD_MODULE_ENABLED) || (HAL_MMC_MODULE_ENABLED) */\r
-/**\r
- * @}\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
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