+++ /dev/null
-/*\r
- * Copyright (c) 2013 Grzegorz Kostka (kostka.grzegorz@gmail.com)\r
- * All rights reserved.\r
- *\r
- * Redistribution and use in source and binary forms, with or without\r
- * modification, are permitted provided that the following conditions\r
- * are met:\r
- *\r
- * - Redistributions of source code must retain the above copyright\r
- * notice, this list of conditions and the following disclaimer.\r
- * - Redistributions in binary form must reproduce the above copyright\r
- * notice, this list of conditions and the following disclaimer in the\r
- * documentation and/or other materials provided with the distribution.\r
- * - The name of the author may not be used to endorse or promote products\r
- * derived from this software without specific prior written permission.\r
- *\r
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR\r
- * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES\r
- * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.\r
- * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,\r
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT\r
- * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\r
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\r
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\r
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF\r
- * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
- */\r
-\r
-#include <config.h>\r
-#include <pll.h>\r
-\r
-#include <stm32f4xx.h>\r
-\r
-\r
-#define PLL_FREQUENCY CFG_CCLK_FREQ\r
-#define PLL_CRYSTAL 8000000UL\r
-\r
-static void flash_latency(uint32_t frequency)\r
-{\r
- uint32_t wait_states;\r
-\r
- wait_states = frequency / 30000000ul; // calculate wait_states (30M is valid for 2.7V to 3.6V voltage range, use 24M for 2.4V to 2.7V, 18M for 2.1V to 2.4V or 16M for 1.8V to 2.1V)\r
- wait_states &= 7; // trim to max allowed value - 7\r
-\r
- FLASH->ACR = wait_states; // set wait_states, disable all caches and prefetch\r
- FLASH->ACR = FLASH_ACR_DCRST | FLASH_ACR_ICRST | wait_states; // reset caches\r
- FLASH->ACR = FLASH_ACR_DCEN | FLASH_ACR_ICEN | FLASH_ACR_PRFTEN | wait_states; // enable caches and prefetch\r
-}\r
-\r
-static void fpu_enable(void)\r
-{\r
-#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)\r
- SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); // set CP10 and CP11 Full Access\r
-#endif\r
-}\r
-\r
-void pll_init(void)\r
-{\r
- uint32_t div, mul, div_core, vco_input_frequency, vco_output_frequency, frequency_core;\r
- uint32_t best_div = 0, best_mul = 0, best_div_core = 0, best_frequency_core = 0;\r
-\r
- fpu_enable();\r
- RCC->CR |= ((uint32_t)RCC_CR_HSEON); // enable HSE clock\r
- flash_latency(PLL_FREQUENCY); // configure Flash latency for desired frequency\r
-\r
- for (div = 2; div <= 63; div++) // PLLM in [2; 63]\r
- {\r
- vco_input_frequency = PLL_CRYSTAL / div;\r
-\r
- if ((vco_input_frequency < 1000000ul) || (vco_input_frequency > 2000000)) // skip invalid settings\r
- continue;\r
-\r
- for (mul = 64; mul <= 432; mul++) // PLLN in [64; 432]\r
- {\r
- vco_output_frequency = vco_input_frequency * mul;\r
-\r
- if ((vco_output_frequency < 64000000ul) || (vco_output_frequency > 432000000ul)) // skip invalid settings\r
- continue;\r
-\r
- for (div_core = 2; div_core <= 8; div_core += 2) // PLLP in {2, 4, 6, 8}\r
- {\r
- frequency_core = vco_output_frequency / div_core;\r
-\r
- if (frequency_core > CFG_CCLK_FREQ) // skip values over desired frequency\r
- continue;\r
-\r
- if (frequency_core > best_frequency_core) // is this configuration better than previous one?\r
- {\r
- best_frequency_core = frequency_core; // yes - save values\r
- best_div = div;\r
- best_mul = mul;\r
- best_div_core = div_core;\r
- }\r
- }\r
- }\r
- }\r
-\r
- /* Configure PLL factors, always divide USB clock by 9 */\r
- RCC->PLLCFGR = (best_div << 0) |\r
- (best_mul << 6) |\r
- ((best_div_core / 2 - 1) << 16) |\r
- (9 << 24) |\r
- RCC_PLLCFGR_PLLSRC_HSE;\r
-\r
- /* AHB - no prescaler, APB1 - divide by 4, APB2 - divide by 2 */\r
- RCC->CFGR = RCC_CFGR_PPRE2_DIV2 |\r
- RCC_CFGR_PPRE1_DIV4 |\r
- RCC_CFGR_HPRE_DIV1;\r
-\r
-\r
- /* Wait for stable clock */\r
- while (!(RCC->CR & RCC_CR_HSERDY))\r
- ;\r
-\r
- /* Enable the main PLL */\r
- RCC->CR |= RCC_CR_PLLON;\r
-\r
- /* Wait for PLL lock */\r
- while (!(RCC->CR & RCC_CR_PLLRDY))\r
- ;\r
-\r
- /* Change SYSCLK to PLL */\r
- RCC->CFGR |= RCC_CFGR_SW_PLL;\r
-\r
- /* Wait for switch */\r
- while (((RCC->CFGR) & RCC_CFGR_SWS) != RCC_CFGR_SWS_PLL)\r
- ;\r
-}\r
+++ /dev/null
-/*\r
- * Copyright (c) 2013 Grzegorz Kostka (kostka.grzegorz@gmail.com)\r
- * All rights reserved.\r
- *\r
- * Redistribution and use in source and binary forms, with or without\r
- * modification, are permitted provided that the following conditions\r
- * are met:\r
- *\r
- * - Redistributions of source code must retain the above copyright\r
- * notice, this list of conditions and the following disclaimer.\r
- * - Redistributions in binary form must reproduce the above copyright\r
- * notice, this list of conditions and the following disclaimer in the\r
- * documentation and/or other materials provided with the distribution.\r
- * - The name of the author may not be used to endorse or promote products\r
- * derived from this software without specific prior written permission.\r
- *\r
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR\r
- * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES\r
- * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.\r
- * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,\r
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT\r
- * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\r
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\r
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\r
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF\r
- * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
- */\r
-\r
-\r
-#ifndef PLL_H_\r
-#define PLL_H_\r
-\r
-#include <config.h>\r
-\r
-/**@brief Clock initialization.*/\r
-void pll_init(void);\r
-\r
-#endif /* PLL_H_ */\r
-\r
projects / lwext4.git / commitdiff